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Summary This paper presents an ultrahigh input impedance, low noise, and wide bandwidth four‐channels analog front‐end (AFE) for low‐power neural recording systems. To achieve high input impedance, the buffer channels are placed between the electrodes and the main amplifier stage of the AFE. The buffer is designed with low noise and low power consumption to obtain high input impedance of overall AFE while maintaining low input‐referred noise and low power consumption. A chopper capacitively coupled chopper instrumentation amplifier (CCIA) is placed after the buffer as the main amplifier stage of the AFE to improve the common mode rejection ratio (CMRR) and the input‐referred noise of the overall AFE design. A new chopper stabilization control technique is proposed and used in the CCIA stage to reduce the charge injection and clock feedthrough and consequently the high‐frequency ripple of the AFE output signal. A programmable gain amplifier (PGA) is designed as the third stage to adjust the overall gain of the AFE. Benefiting from PGA, the AFE can adapt its gain with both action potential and local field potential signals. To reduce the number of the electrode to be implanted and reduce the impedance mismatch that causes the degradation on overall CMRR performance, two AFE channels shared a reference electrode followed by a reference buffer. The proposed AFE is designed and simulated using a standard 180 nm CMOS process and operates in a wide frequency band of 2.1 to 2500 Hz with low input‐referred noise of 1.6 μVrms and a CMRR over 80 dB at 2.1 Hz. The total power consumption is lower than 4.3 μW per channel. With the proposed structure of AFE, the input impedance is 35 GΩ @ 21 Hz and the minimum impedance over operational bandwidth is 75 MΩ @ 2.5 kHz. [ABSTRACT FROM AUTHOR]

This paper presents the behavioral modeling of three circuit architectures, which are suitable for heartbeat detection in wireless healthcare applications. The developed front-end models implement an analog system that detects the heartbeats for lower power consumption and higher detection accuracy without digital signal processing. Therefore, the circuit blocks and their critical specifications specifically regarding the noise and bandwidth are evaluated. The architectures are implemented in Verilog-A and their behavior simulations use real electrocardiogram (ECG) signals with different characteristics and conditions. All architectures have amplification, band-pass and notch response blocks as their first three stages. Then, the first circuit architecture detects the heartbeat using an adaptive threshold based on a pulse width approach. The second heartbeat detection scheme finds the maximum and minimum values of each beat using a sample-and-hold-based peak detector. The third model uses a similar peak detection scheme, but delays the analog signal for better precision. The simulation results show that all models can detect heartbeats when the input noise is less than $20 \mu V$ , the third having the highest noise tolerance of around $50 \mu V$ . For the ECG signal to maintain its characteristics with respect to its positive and negative peak, the bandpass response should present a low cutoff frequency below 10 Hz.

This article presents a programmable gain current amplifier (CA) for ultrasound sensing applications. The design proposed consists of a current divider and a close-loop current amplifier. The CA utilizes switches to adjust the resistance of the shunt resistors and feedback resistors to achieve variable gain, thus realizing the time gain compensation (TGC) function. The proposed CA implemented in 180-nm BCD technology occupies an active area of 0.059 mm 2. Measurement results show that the CA achieves a maximum gain of 36.6 dB and a gain range of 60 dB. The average input-referred noise spectral density is 0.32 pA/ √ Hz at maximum gain condition while consuming a power of 1.07 mW. [ABSTRACT FROM AUTHOR]

The past century has seen the ongoing development of amplifiers for different electrophysiological signals to study the work of the heart. Since the vacuum tube era, engineers and designers of bioamplifiers for recording electrophysiological signals have been trying to achieve similar objectives: increasing the input impedance and common-mode rejection ratio, as well as reducing power consumption and the size of the bioamplifier. This review traces the evolution of bioamplifiers, starting from circuits on vacuum tubes and discrete transistors through circuits on operational and instrumental amplifiers, and to combined analog-digital solutions on analog front-end integrated circuits. Examples of circuits and their technical features are provided for each stage of the bioamplifier development. Special emphasis is placed on the review of modern analog front-end solutions for biopotential registration, including their generalized structural diagram and table of comparative characteristics. A detailed review of analog front-end circuit integration in various practical applications is provided, with examples of the latest achievements in the field of electrocardiogram, electroencephalogram, and electromyogram registration. The review concludes with key points and insights for the future development of the analog front-end concept applied to bioelectric signal registration. [ABSTRACT FROM AUTHOR]

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

Isolated current sensing is fundamental in several contexts, including power electronics, automotive, and smart buildings. In order to meet the requirements of modern applications, current sensors should feature ever larger bandwidth and dynamic range, as well as reduced power consumption and dimension. Among the available current sensing technologies, Hall-based current sensors have gained an increased popularity owing to their advantages in terms of size, economic feasibility, low power consumption, high dynamic range, and integrability with standard CMOS technologies. This tutorial aims at providing a comprehensive insight into the interdisciplinary world of Hall-effect current sensors, encompassing the fundamental principles of operation, the design of the semiconductor device, the implementation techniques, as well as the methods for sensor modeling and characterization. In particular, this manuscript focuses on Hall-effect sensors realized on standard silicon technologies, and it reviews some typical architectures for the transduction of the measurand current into a magnetic field, as well as the electronic front-end. While this tutorial is mainly addressed to students and non-expert readers, specific design aspects and dispersion effects due to temperature and other external phenomena are also discussed. [ABSTRACT FROM AUTHOR]

Recent years have seen fast advances in neural recording circuits and systems as they offer a promising way to investigate real-time brain monitoring and the closed-loop modulation of psychological disorders and neurodegenerative diseases. In this context, this tutorial brief presents a concise overview of concepts and design methodologies of neural recording, highlighting neural signal characteristics, system-level specifications and architectures, circuit-level implementation, and noise reduction techniques. Future trends and challenges of neural recording are finally discussed. [ABSTRACT FROM AUTHOR]

Wearable biomedical systems allow doctors to continuously monitor their patients over longer periods, which is especially useful to detect rarely occurring events such as cardiac arrhythmias. Recent monitoring systems often embed signal processing capabilities to directly identify events and reduce the amount of data. This work is the first to document a complete beat-to-beat arrhythmia classification system implemented on a custom ultra-low-power microcontroller. It includes a single-channel analog front-end (AFE) circuit for electrocardiogram (ECG) signal acquisition, and a digital back-end (DBE) processor to execute the support vector machine (SVM) classification software with a Cortex-M4 CPU. The low-noise instrumentation amplifier in the AFE consumes 1.4 $\mu$ W and has an input-referred noise of 0.9 $\mu$ V RMS. The all-digital time-based ADC achieves 10-bit effective resolution over a 250-Hz bandwidth with an area of only 900 $\mu$ m $^{2}$. The classification software reaches a sensitivity of 82.6% and 88.9% for supraventricular and ventricular arrhythmias respectively on the MIT-BIH arrhythmia database. The proposed system has been prototyped on the SleepRider SoC, a 28-nm fully-depleted silicon on insulator (FD-SOI) 3.1-mm $^{2}$ chip. It consumes 13.1 $\mu$ W on average from a 1.8-V supply. [ABSTRACT FROM AUTHOR]

A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance amplifier (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor Rm. A source-degenerated transconductance stage was adopted in the CTLE, and source follower and shunt feedback resistor stages were adopted in the TIA. The proposed CTLE could achieve high frequencies by altering the tail current with fixed degenerate capacitance CS and resistance RS. The proposed AFE achieved high bandwidth, and the use of a feedback resistor Rf and inductor Lf improved its high-frequency performance. Simulation results revealed that the CTLE can compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open closed eyes in a 6 Gb/s non-return-to-zero signal with a bit error rate of 0.16 × 10−12 for a 231 − 1 pseudorandom binary sequence input. The AFE could compensate for 12 dB of channel loss at a 15 GHz Nyquist frequency and can open closed eyes in a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power at 1.8 V. [ABSTRACT FROM AUTHOR]

In this paper, low-noise incremental delta–sigma analog front end (AFE) integrated circuit (IC) for capacitive microsensors is presented. A conventional capacitance-to-digital converter (CDC) mainly uses a multi-stage capacitive sensing amplified stage (CSA) and analog-to-digital converters. The multi-stage CSA is not suitable for application in various Internet of things (IoT) devices that require low power because the power consumption of the analog front-end circuit increases in proportion to the number of amplifiers and the chip area increases. So, the presented delta-sigma AFE can convert the capacitance changes to the digital codes directly. This structure can achieve a small active area and low power consumption. The delta–sigma AFE achieves low-noise and high linearity using a capacitor polarity swapping technique. The measured effective resolution is 16.2 bits, and the non-linearity is 0.05% full-scale output (FSO). The integrated circuit is implemented in a 0.18-µm standard CMOS process. All functional blocks, including the analog circuits (bandgap reference, voltage reference, and delta–sigma capacitance-to-digital converter) and digital block (accumulator and timing generator), are integrated on a chip. The proposed incremental delta–sigma AFE consumes 1.12 mW of power from a 3.3-V supply at a sampling frequency of 500 kHz and occupies a total active area of 0.42 mm2. [ABSTRACT FROM AUTHOR]

Electrooculogram (EOG) is a well-known physiological metric picked up by placing two or more electrodes around the eyeball. EOG signals are known to be extremely susceptible to motion artifacts. This paper presents a single channel, wireless, wearable flexible EOG monitoring system with motion artifacts sensing and reduction feature. The system uses two non-contact electrode pairs for EOG/motion artifacts detection and motion artifacts reduction. It is implemented on a four-layer flexible polyimide substrate. It is light-weight (only 8.75 gram), battery operated, and uses a microcontroller and a BLE 5.0 transceiver for wireless EOG data transmission, while consuming only 56 mW of power. The system metrics such as gain around 37 dB, bandwidth from 1 Hz to 40 Hz, and noise are evaluated. The system is tested for different electrode configurations and it is demonstrated that horizontally parallel electrode pairs achieve an acceptable motion artifact reduction at the output, while preserving perfect EOG features (such as eye-blinking). The average sensitivity for horizontally parallel non-contact electrodes is found out to be more than 50 times with respect to commercial gold electrodes, whereas the average response time of the sensor is around 380 mS. The flexible EOG system is comfortable to wear and the use of non-contact electrode eliminates the need of skin preparation. Therefore, the system can be easily integrated with eye-masks and headbands, thus making it an excellent prototype for many smart applications. [ABSTRACT FROM AUTHOR]

This paper presents an analog front-end channel for the readout of Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The circuit has been designed in a 65 nm CMOS technology. The charge generated by the detector is integrated by a Charge Sensitive Amplifier (CSA) with dynamic signal compression feature to achieve improved noise performance, along with enhanced time resolution capabilities over the wide range of input charge to be detected (from 45 fC to 16 pC). An RC-CR shaper with selectable shaping time, a fast discriminator and a Time-to-Amplitude Converter (TAC) complete the readout circuit. An SNR around 300, together with a time resolution of slightly below 60 ps, is achieved in post-layout simulations. [ABSTRACT FROM AUTHOR]

This paper presents a high-resolution analog front-end (AFE) circuit operating in the 25 kHz signal bandwidth. The AFE consists of a capacitively-coupled chopper instrumentation amplifier (CCIA) and a third-order delta-sigma modulator (DSM). Signal distortion often occurs at the junction of CCIA and DSM, so the resistor-based discrete-time DSM (RB DT–DSM) is proposed to solve this problem. Both conventional DT–DSM and the proposed RB DT–DSM are designed and compared through simulations and chip measurements. When a conventional DT–DSM is used, a switched-capacitor integrator with a large capacitor and switch are connected to the CCIA output node, so large switching noise, significant charge injection, and a long settling time occur at the CCIA output, resulting in harmonic distortions. Therefore, CCIA requires more power consumption to reduce the settling time for conventional DT–DSM architectures. On the other hand, when the proposed RB DT–DSM is used, only a resistor and a small switch are connected to the CCIA output. Due to this novel interface technique, the switching noise is very small at the CCIA output, and the settling of the CCIA becomes fast. As a result, it is possible to effectively eliminate harmonic distortions while reducing the power requirement of the CCIA. Both the conventional and proposed AFE circuits were manufactured by a 0.18- $\mu \text{m}$ complementary metal-oxide-semiconductor (CMOS) process. The conventional AFE shows a peak SNR of 101.1 dB and a peak SNDR of 91.2 dB. The proposed AFE with RB DT–DSM shows a peak SNR of 101.3 dB and a peak SNDR of 100.5 dB, which verifies the significant reduction in harmonic distortions.

There has been considerable interest in electrical impedance tomography (EIT) to provide low-cost, radiation-free, real-time and wearable means for physiological status monitoring. To be competitive with other well-established imaging modalities, it is important to understand the requirements of the specific application and determine a suitable system design. This paper presents an overview of EIT circuits and systems including architectures, current drivers, analog front-end and demodulation circuits, with emphasis on integrated circuit implementations. Commonly used circuit topologies are detailed, and tradeoffs are discussed to aid in choosing an appropriate design based on the application and system priorities. The paper also describes a number of integrated EIT systems for biomedical applications, as well as discussing current challenges and possible future directions.

This paper proposes a high frame rate analog front-end (AFE) IC combined with a piezoelectric micromachined ultrasonic transducer (PMUT) for ultrasound imaging systems (UISs). The proposed AFE IC, which consists of 8-channel transceivers and a peripheral circuit, employs analog multi-line acquisition (AMLA) based on sub-array beamforming. This AMLA generates multiple scanlines during a scan time by simultaneously and precisely controlling the delay of the AFE IC, thus achieving the high frame rate of the AFE IC. The sensitivities of the PMUT for transmitting and receiving ultrasound waves are simulated to be 67.5 kPa/V and 1.2 mV/kPa, respectively, which are high enough to mitigate the needs of the high-voltage electronics for UISs. The proposed AFE IC was fabricated using a 0.18- $\mu \text{m}$ silicon-on-insulator process and occupies an active area of 2.56 mm $\times1.68$ mm. The measurement results using the simulated PMUT parameters show that the proposed AFE IC with the AMLA precisely controls its delay up to $1~\mu \text{s}$ at a clock frequency of 40 MHz. It also acquires more than 9,000 scan/s even at a focal depth of 150 mm, which is at least twice greater than those of prior works, achieving a high frame rate of 93 Hz when 100 scanlines are used for a frame. In addition, a figure-of-merit, which considers the energy consumption per channel/scan and the energy loss, is achieved to be 20 nJ/scan/dB at a focal depth of 150 mm and a center frequency of 3.6 MHz; this is the best result compared to previously reported works. Therefore, the proposed AFE IC is suitable for UISs requiring a high frame rate.

In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18- $\mu$ m CMOS technology consumes the power of 756 $\mu$ W while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1 $\%$ and 1.9 $^{\circ }$ , respectively. [ABSTRACT FROM AUTHOR]

Abstract Background It is widely accepted by the scientific community that bioelectrical signals, which can be used for the identification of neurophysiological biomarkers indicative of a diseased or pathological state, could direct patient treatment towards more effective therapeutic strategies. However, the design and realisation of an instrument that can precisely record weak bioelectrical signals in the presence of strong interference stemming from a noisy clinical environment is one of the most difficult challenges associated with the strategy of monitoring bioelectrical signals for diagnostic purposes. Moreover, since patients often have to cope with the problem of limited mobility being connected to bulky and mains-powered instruments, there is a growing demand for small-sized, high-performance and ambulatory biopotential acquisition systems in the Intensive Care Unit (ICU) and in High-dependency wards. Finally, to the best of our knowledge, there are no commercial, small, battery-powered, wearable and wireless recording-only instruments that claim the capability of recording electrocorticographic (ECoG) signals. Methods To address this problem, we designed and developed a low-noise (8 nV/√Hz), eight-channel, battery-powered, wearable and wireless instrument (55 × 80 mm2). The performance of the realised instrument was assessed by conducting both ex vivo and in vivo experiments. Results To provide ex vivo proof-of-function, a wide variety of high-quality bioelectrical signal recordings are reported, including electroencephalographic (EEG), electromyographic (EMG), electrocardiographic (ECG), acceleration signals, and muscle fasciculations. Low-noise in vivo recordings of weak local field potentials (LFPs), which were wirelessly acquired in real time using segmented deep brain stimulation (DBS) electrodes implanted in the thalamus of a non-human primate, are also presented. Conclusions The combination of desirable features and capabilities of this instrument, namely its small size (~one business card), its enhanced recording capabilities, its increased processing capabilities, its manufacturability (since it was designed using discrete off-the-shelf components), the wide bandwidth it offers (0.5–500 Hz) and the plurality of bioelectrical signals it can precisely record, render it a versatile and reliable tool to be utilized in a wide range of applications and environments.

In this paper, we propose a structure of a portable cardiograph. Contents and functions of all blocks are overviewed. We describe two main structures of portable cardiographs, prepare a comparative table of characteristics for different analog front-ends. All individual features of the chips are listed as well. We register a test signal and try to improve its quality by means of digital filtration, taking the signal gained from certified Biopack equipment as a reference. We calculate device power consumption to compute required battery volume. Finally, energy efficient preprocessing algorithm is proposed.

Electroocugraphy (EOG) is a simple and non-invasive method in which biopotentials developed across the eyes are measured during various eye activities such as eye blinking, winking, and horizontal/vertical eyeball movements. The measured biopotential is called the electroculogram (EOG) signal. This paper presents a single channel EOG measurement system which is implemented on a four layer flexible polymide substrate. The EOG measurement system with its signal conditioning stages is implemented on the top layer of the flexible board whereas, the EOG measurement electrodes are printed on the bottom layer of the flexible board using gold. This eliminates the requirement of external long wires during EOG monitoring. The middle two layers of the flexible substrate are used for implementing the circuit ground plane and active shielding. The entire circuit is powered by a rechargeable Li-ion coin battery. It also uses a Bluetooth 5.0 transceiver module to send the EOG data wirelessly. The system is designed for an effective EOG signal bandwidth of 1.6 Hz to 47 Hz with an effective signal gain above 68.5 dB over the signal bandwidth. The system also has an excellent common-mode rejection ratio (CMRR) response above 70 dB. The system is validated with eight healthy subjects for the detection of different eye activities with an accuracy of 77.08 %. The mass of the entire flexible board along with its battery is only 7.7 g. Such light mass, flexible substrate, and integrated printed electrodes make this EOG monitoring prototype an ideal unit for long term monitoring of biopotentials, without causing any discomfort to the wearer. [ABSTRACT FROM AUTHOR]

This paper discusses a 56-Gb/s PAM4 receiver analog-front end (AFE) implemented in TSMC 40-nm CMOS process. The system consists of a differential 100-Ω termination, a two-stage continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA), and an output buffer. The source-degenerated transconductance stage and inverter-based transimpedance (TIA) with source follower structure are adopted for both CTLE and VGA. The utilization of source follower can solve the harsh DC operation problem in conventional inverter-based TIA and extend the bandwidth. By altering the source-degenerated resistors and capacitors in the two-stage CTLE, the proposed AFE can reach fixed peaking frequency with 9-dB compensation range at high frequency. Moreover, it can also achieve a fixed bandwidth at 14 GHz and 9.5-dB DC gain tuning range when altering the feedback resistors and negative capacitance compensation network (NCC) in VGA. Measurement results demonstrate that: it can compensate for 7.3-dB channel loss at 14-GHz Nyquist frequency and open the closed eye for 56-Gb/s PAM4 signal with BER < 10−8 from 215 – 1 PRBS input. The core of the AFE occupies 0.32-mm2 area and consumes 30-mW power from 1.1/1.2-V supply. [ABSTRACT FROM AUTHOR]

In this article, we present the design and analysis of a 785-nW multimodal sensor interface IC for ozone pollutant sensing and correlated cardiovascular disease monitoring based on electrocardiography (ECG) and photoplethysmography (PPG). The proposed hybrid dc offset current cancellation (DCOC) along with a 4-MΩ gain-regulated cascode transimpedance amplifier (RGC-TIA) enable PPG readout power reduction by 37 ×, compared with the state-of-the-art PPG sensor interfaces. The ozone sensing channel proposes an adaptive architecture to enable low VDD operation, achieving a 300 × power reduction, compared with the state-of-the-art gas sensing readouts. The ozone sensing channel’s performance was also verified using custom resistive metal-oxide sensors for concentrations from 50 to 900 ppb. The sensor interface IC is fabricated in a 65-nm CMOS, integrating a 165-nW voltage-mode ECG channel, a 532-nW current-mode PPG channel, 76-nW resistive-mode ozone channel, and 12.6-nW peripheral circuits, all at 0.6 V. The total system power consumption including the LED and a custom digital readout IC is 10.98– 5.51 μW, which is 41 × – 57 × less than prior ozone/CVD joint monitoring sensor interface systems. [ABSTRACT FROM AUTHOR]

In the application of AI speech interaction, the analog front-end(AFE) circuit in audio SoC is responsible for digitalization of microphone analog output, and it is a bridge between the analog signal and the digital processing unit. The AFE function and dynamic performance are greatly limited due to the influence of complex audio environment application, the device mismatch and other non-ideal factors. The audio SoC AFE is analyzed in this paper, and the circuit characteristics and current development is discussed in detail. Finally the research route for design challenge is presented and development trend is prospected.

This article presents a biopotential amplifier that has a large tolerance to common-mode interference (CMI) for a reliable two-electrode electrocardiogram (ECG) recording. To withstand large CMI without affecting the ECG signal, a common-mode charge pump (CMCP) that absorbs displacement current from the CMI and keeps the common-mode input within the desired range is proposed. This article also analyzes the effects of CMCP under non-ideal conditions and provides design guidelines for improved signal quality. A prototype chip fabricated in 180-nm CMOS achieves CMI tolerance of 15 $\text{V}_{\text {PP}}$ at 60 Hz while consuming 24.8 $\mu \text{W}$ from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

Abstract Schumann resonance oscillation detection is a complex procedure which requires customized and high-quality measurement systems. The primary objective of this work was to design and implement a stand-alone, portable, and low-cost receiver able to measure as much Schumann resonance harmonics as possible. Design, as well as detailed analysis of the efficient induction coil magnetic antenna and the low-noise amplifying-filtering chain, is presented. The detection system includes two coils back to back, resulting in a total coil length of 60 cm. The filtering and amplification chain exhibits an experimentally measured total passband gain equal to 112 dB at 10 Hz and as low as 2.88 nV/√Hz equivalent input noise. In order to validate the new portable ELF Schumann resonance detection and monitoring system, we took measurements at various spots “relatively” free from man-made electromagnetic pollution. Results have shown very clear Schumann resonance peaks for the first six modes with 10-min acquisition time.

Aiming at the requirement of the hybrid sky-surface network for radar receiver, the design of analog front-end for dual-band multi-channel digital radar receiver based on software radio idea is proposed and implemented. The design takes an analog-to-digital conversion chip as the core, which achieves the amplification and sampling of 8-channel dual-band receive signals , ensures the consistency of the channel gain, and simplifies the circuit when keeping the flexibility. Finally, through the system simulation and field test of the receiver, the correctness of the design is proved, and it can meet the practical application requirements.

In this study, a fully integrated electroencephalogram/functional near-infrared spectroscopy (EEG/fNIRS) brain monitoring system was designed to fulfill the demand for a miniaturized, light-weight, low-power-consumption, and low-cost brain monitoring system as a potential tool with which to screen for brain diseases. The system is based on the ADS1298IPAG Analog Front-End (AFE) and can simultaneously acquire two-channel EEG signals with a sampling rate of 250 SPS and six-channel fNIRS signals with a sampling rate of 8 SPS. AFE is controlled by Teensy 3.2 and powered by a lithium polymer battery connected to two protection circuits and regulators. The acquired EEG and fNIRS signals are monitored and stored using a Graphical User Interface (GUI). The system was evaluated by implementing several tests to verify its ability to simultaneously acquire EEG and fNIRS signals. The implemented system can acquire EEG and fNIRS signals with a CMRR of −115 dB, power consumption of 0.75 mW/ch, system weight of 70.5 g, probe weight of 3.1 g, and a total cost of USD 130. The results proved that this system can be qualified as a low-cost, light-weight, low-power-consumption, and fully integrated EEG/fNIRS brain monitoring system.

This paper presents an 8-channel energy-efficient analog front-end (AFE) for neural recording, with improvements in power supply rejection ratio (PSRR) and dynamic range. The input stage in the low noise amplifier (LNA) adopts low voltage supply (0.35 V) and current-reusing to achieve ultralow power. To maintain a high PSRR performance while using such a low-voltage supply, a replica-biasing scheme is proposed to generate a stable bias current for the input stage of the LNA despite large supply interference. By exploiting the signal characteristics in the tetrode recording, an averaged local field potential (A-LFP) servo loop is introduced to extend the dynamic range without consuming too much extra power and chip area. The A-LFP signal is generated by integrating the four-channel PGA outputs from the same tetrode. Furthermore, the outputs of the programmable gain amplifier (PGA) are level shifted to bias the input nodes of the amplifier through large pseudo resistors, thus increase the maximum output range without distortion under the low-voltage supply. The proof-of-concept prototype is fabricated in a 65 nm CMOS process. Each recording channel including an LNA and a PGA occupies 0.04 mm $^2$ and consumes 340 nW from the 0.35 V and 0.7 V supply. Each A-LFP servo loop, which is shared by four recording channels, occupies 0.04 mm $^2$ and consumes 190 nW. The maximum gain of the AFE is 54 dB, and the input-referred noise is 6.7 $\mu$ V over the passband from 0.5 Hz to 6.5 kHz. Measurement also shows that the 0.35 V replica-biasing input stage can tolerate a large interferer up to 200 mVpp with a PSRR of 74 dB, which has been improved to 110 dB with a silicon respin that shields critical wires in the layout. [ABSTRACT FROM AUTHOR]

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Background: It is widely accepted by the scientific community that bioelectrical signals, which can be used for the identification of neurophysiological biomarkers indicative of a diseased or pathological state, could direct patient treatment towards more effective therapeutic strategies. However, the design and realisation of an instrument that can precisely record weak bioelectrical signals in the presence of strong interference stemming from a noisy clinical environment is one of the most difficult challenges associated with the strategy of monitoring bioelectrical signals for diagnostic purposes. Moreover, since patients often have to cope with the problem of limited mobility being connected to bulky and mains-powered instruments, there is a growing demand for small-sized, high-performance and ambulatory biopotential acquisition systems in the Intensive Care Unit (ICU) and in High-dependency wards. Finally, to the best of our knowledge, there are no commercial, small, battery-powered, wearable and wireless recording-only instruments that claim the capability of recording electrocorticographic (ECoG) signals.Methods: To address this problem, we designed and developed a low-noise (8 nV/√Hz), eight-channel, battery-powered, wearable and wireless instrument (55 × 80 mm2). The performance of the realised instrument was assessed by conducting both ex vivo and in vivo experiments.Results: To provide ex vivo proof-of-function, a wide variety of high-quality bioelectrical signal recordings are reported, including electroencephalographic (EEG), electromyographic (EMG), electrocardiographic (ECG), acceleration signals, and muscle fasciculations. Low-noise in vivo recordings of weak local field potentials (LFPs), which were wirelessly acquired in real time using segmented deep brain stimulation (DBS) electrodes implanted in the thalamus of a non-human primate, are also presented.Conclusions: The combination of desirable features and capabilities of this instrument, namely its small size (~one business card), its enhanced recording capabilities, its increased processing capabilities, its manufacturability (since it was designed using discrete off-the-shelf components), the wide bandwidth it offers (0.5-500 Hz) and the plurality of bioelectrical signals it can precisely record, render it a versatile and reliable tool to be utilized in a wide range of applications and environments. [ABSTRACT FROM AUTHOR]

A new non-invasive and flexible sensor was fabricated to monitor the muscular activity of upper body muscles. It consists of a dry electrode made of multimaterial metal-polymer-glass hollow-core fiber electrodes connected to a custom made signal acquisition platform. This fiber electrode only adds a negligible contribution to the recording system’s internal noise ($7.626~\mu \text{V}$ peak-to-peak and $1.234~\mu \text{V}$ RMS; recording system noise: $6.901~\mu \text{V}$ peak-to-peak and $1.205~\mu \text{V}$ RMS). Surface electromyograms (sEMGs) of the biceps bracci and trapezius muscles were recorded during maximal voluntary contractions using the new sensor and compared to that obtained with medical grade commercial sensors. Frequency content and time domain analysis show that the new flexible sensor performs similarly to commercial devices in terms of sEMG signal amplitude discrimination and frequency shift evaluation during the development of muscle fatigue. The advantage of the new sensor is the high flexibility of the fibers allowing their easy integration into stretchable garments without compromising the user’s comfort. This will lead to the development of a new generation of smart textile with large application for telemedicine and assistive devices. [ABSTRACT FROM AUTHOR]

This brief presents an analog front-end (AFE) specially developed for a water conductivity measurement system for water network management applications. Water conductivity is one of the best ways to detect a problem with the water in the network. In order to trigger an alarm it is only required to detect a 10% variation, which allows to simplify the system design. The proposed sensor uses four platinum micro-machined electrodes, where a 6 kHz signal is applied to the outer electrodes and a voltage signal is read in the inner ones. A programmable switched-capacitor (SC) bandpass filter is included in the analog-to-digital (A/D) channel to attenuate the interference from the 50 Hz power network, that shares the same environment with the water network, and to allow using a square wave signal to drive the sensor, thus simplifying the overall system. The resulting sine wave is digitized using a passive continuous-time (CT) 2nd order $\Delta\Sigma$ modulator. The output bitstream is decimated, using a sinc filter, and the RMS value of the voltage is calculated. The A/D acquisition channel was implemented in a 130 nm CMOS technology, using a supply voltage of 0.9 V and a clock frequency of 1 MHz (SC amplifier and SC bandpass filter) and 4 MHz ($\Delta \Sigma $ modulator). Measurement results show a SNDR of 44.4 dB for an input signal of 6 kHz and an amplitude of −41 dBV. The channel dissipates 386 $\mu \text{W}$ and occupies an area of 0.27 mm2. [ABSTRACT FROM AUTHOR]

Analog Front-End (AFE) is a part of physical layer (PHY) at Visible Light Communications (VLC) system which has important things to transmit and receive the data. This research is a preliminary study in designing AFE transceiver which consists of LED driver and Trans-impedance Amplifier (TIA). The results are used as advanced reference design of AFE system and also to determine the modulations range (analog as well as digital). The design verification is based on data transmission which generated by signal generator. Square wave signal is used as digital modulation representative, and sinusoid signal as analog modulation representatitive. The range of VLC channels is about 50 cm with 0o angle. The result shows that digital modulation bandwidth is about 1 KHz to 10 KHz frequency, and analog modulation bandwidth is from 200 KHz to 600 KHz. We also find a significant impact by adding 1 pF capacitor to reduce noise gain. Furthermore, color filter testing is performed to investigate the design performance.

For low-power hearing aid device application, a fully integrated optimized hearing aid SoC structure is proposed in this paper. The SoC consists of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and Class-D amplifier. A novel peak-statistical algorithm is proposed to track signal amplitude and adjust automatic gain control loop gain precisely. A comparative DWA is applied to break the correlation of in-band tone and sequential selection scheme, which realizes second-order noise shaping and suppresses harmonic effectively. The SoC has been implemented with 0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio (SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three main algorithms of wide dynamic range compression, noise reduction, and feedback cancelation are executed through DSP platform. With 1 V supply voltage, total SoC power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device prototype is produced that shows its great potential for mass manufacture in the future. [ABSTRACT FROM AUTHOR]

A linear-array receiver analog front-end (AFE) circuit, which mainly consists of 16 transimpedance amplifiers (TIAs), is presented for pulsed time-of-flight (TOF) rotating scanner light detection and ranging (LiDAR) application. In particular, a single-channel TIA with a novel cascaded combination consists of a transimpedance preamplifier biased by a power supply of 1.8 V, a post amplifier (PA), and an output buffer (OB) with a 3.3-V power supply, aiming to lower the parasitic capacitance of the input stage and widen the output swing range, respectively. Meanwhile, the input-referred noise current is investigated to evaluate the detecting capability for the weak pulse current, and the crosstalk reduction schemes in circuit design and layout design are presented for the proposed AFE circuit. The proposed AFE circuit, which achieves a high gain of 100 dB ${\Omega }$ , a low gain of 60 dB ${\Omega }$ , a simulated transimpedance gain bandwidth of approximately 450 MHz, an equivalent input-referred noise current of 2.59 pA/Hz0.5, a signal-to-crosstalk ratio of 40.1 dB between adjacent channels, and a minimum detectable signal of $2.5~{\mu }\text{A}$ at SNR = 5, was fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS technology. The total area of AFE circuit, which includes the circuit core, bandgap and bias circuits, and I/O PAD, is approximately equal to ${4.80}\times {0.85}$ mm2. [ABSTRACT FROM AUTHOR]

This paper presents an integrated switched-capacitor-based low-power fully-differential analog front-end (AFE) for simultaneously detecting electrocardiogram (ECG) and respiration rate (RR). A current-driven passive mixer is used to up-convert the RR signal, and a preamplifier including a driven-ground common-mode feedback (CMFB) loop amplifies both the ECG and modulated RR signals. The modulated RR signal is then down-converted to baseband to be further amplified and detected. Switched capacitors (SCs) are widely used in the proposed AFE to provide large time constants that are also easily adjustable via the clock frequency. The chip is highly programmable, which enables complex automatic gain control (AGC) algorithms based on using a microcontroller within the loop. The AFE was fabricated in the OnSemi 0.5 μ m CMOS process. Both simulation and measurement results verify the functionality of the chip for measuring multiple biosignals, including ECG, RR, electromyography (EMG), and galvanic skin response (GSR). Performance metrics are competitive compared to the state of the art. [ABSTRACT FROM AUTHOR]

Abstract A 6-bit digital CMOS variable gain attenuator (VGAT) with 42 dB dynamic range (DR) and high linearity-in-dB was presented. CMOS transistors were used as the shunt devices and attenuation gains with different distribution rules of the shunt transistors (W / L)s were analyzed and simulated in detail. A geometric series with a length of 42 and a ratio of 1.122 was finally adopted for the (W / L)s to achieve the 42 dB DR and 1 dB attenuation step size. Fabricated in a 0.18-μm CMOS technology, the proposed VGAT had been integrated in a 4-channel ultrasonic imaging receiver chip and occupied an area of about 0.5 mm × 0.37 mm. The gain errors were limited in the range from −1 dB to −1.3 dB at 27 °C and the DR of the VGAT at different temperatures was retained above 40 dB. The –3 dB bandwidth was about 1.9 GHz at the maximum attenuation and the S11 was better than −11 dB with a 30 MHz input. [ABSTRACT FROM AUTHOR]