1. Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM
- Author
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Amitay Levi, Khai Tran, Jungsik Kim, Beery Dafna, Antonio Arreghini, Andrew J. Walker, Jin-Woo Han, Senthil Vadakupudhu Palayam, Arnaud Furnemont, K. Deniz Bozdag, Irwin Tain, Meyya Meyyappan, and Cuevas Peter
- Subjects
010302 applied physics ,Dynamic random-access memory ,Materials science ,Silicon ,business.industry ,Transistor ,chemistry.chemical_element ,Hardware_PERFORMANCEANDRELIABILITY ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,law.invention ,Hysteresis ,Soft error ,chemistry ,Memory cell ,law ,Logic gate ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Dram - Abstract
A new dynamic random access memory (DRAM) memory cell transistor is fabricated, and its soft-error immunity and rowhammer tolerance are studied. The vertical channel is formed by selective epitaxial growth of silicon pillar, and the surround gate forms a fully depleted (FD) channel, which can suppress floating-body effects, such as hysteresis. A TCAD simulation study compares this device and conventional bulk saddle FinFET in terms of soft error immunity and rowhammer tolerance. The confined channel limits soft error because of its thin channel volume for charge generation due to alpha and neutron particles. The surround gate device is inherently free from rowhammer attack as each silicon body of any memory cell transistor is fully isolated from neighboring word lines.
- Published
- 2021
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