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Dickson-type dc-dc converters have gained renewed interest in recent years due to their best-in-class volt-amp switch utilization. In addition, 'hybrid' switched-capacitor (HSC) structures increase passive component utilization while avoiding the slow-switching limit (SSL), and yet, most HSC work to date has done little to assess large signal voltage ripple behavior and subsequent passive utilization limits. This work contributes a comprehensive review of contemporary Dickson-type HSC converters before introducing eight fundamental reduced HSC Dickson structures, including three that are proposed here. Analysis allowing characterization of large signal operating points, capacitor sizing regimes, switching schemes, and maximum allowable power throughput is introduced. The analysis for 'split-phase' switching is also presented in detail, without making small ripple approximations. Furthermore, an expression for large ripple flying capacitor energy density utilization is derived, assisting with optimal topology selection and revealing that split-phase operation may be preferable for conversion ratios greater than 6:1. All analysis is verified in simulation, with an additional discrete hardware prototype further validating a complex case of resonant split-phase timing. The analytical results of 17 distinct Dickson variations are recorded, assisting with topology selection and design.

In this work, the online offering of a sophomore electrical and computer engineering hands-on course at UC Davis during COVID-19 pandemic is discussed. In response to California's social distancing guidelines, the course was abruptly moved from in-person to remote instruction. To overcome the challenges inherent in remote instruction, we employed novel policies, "Boost Points" (BP) and "Student Assistants" (SA), to incentivize early action on lab assignments and interaction between students. We present survey and participation data that show students favor these techniques. Finally, we outline future directions for SA/BP in lab-based circuits courses.

This paper describes a resonant Dickson-based topology that achieves complete soft-charging with two-phase operation and a convenient 50% duty cycle at all odd conversion ratios. A brief analysis is presented that shows how the resonant switching frequency can be calculated as a function of inductor and capacitor values. One solution sets all capacitors and both inductors equal, and results in switching devices experiencing a constant blocking voltage that is largely independent of load and fly capacitor voltage ripple. The requirement for capacitor matching and subsequent low capacitance density C0G dielectrics is compensated by a weakly bounded voltage swing: no switching devices are present on intermediary nodes connecting L and C elements allowing for very large voltage ripple and highly effective utilization of each fly capacitor's energy density. A discrete 1:5 prototype validates the proposed topology with measured waveforms illustrating 50% two-phase operation and a load-independent maximum blocking voltage across switching devices. An output power of 129 W with a 94% peak efficiency was measured for an input voltage of 20 V. Measuring 11.45 mm × 12.95 mm × 2.8 mm, this prototype achieves a very high power density of 311 kW/liter (5, 096 W/inch3) despite the use of diodes for simplicity and 66% of the converter's volume being comprised of PCB and free space.

By applying resonant charge redistribution (RCR) to the parasitic capacitances of a switched-capacitor converter, COSS-related dynamic switching losses can be significantly reduced. The proposed technique demonstrates adiabatic mitigation of all primary loss mechanisms in a transformer-less resonant Cockcroft-Walton (CW) converter's forward power path, with only the gate drivers exhibiting conventional hard-charged CV2f losses. Two inductors are used: a large primary inductance directly in the forward power path to mitigate transient inrush currents, and a second small inductance to perform Coss charge redistribution prior to initialization of subsequent phases. The second inductor can be small while still exhibiting high Q-factor as it only interacts with switch parasitics. A discrete 1:5 prototype using GaN-FETs and diodes achieves a power density of 181.8 kW/liter (2.98 kW/inch3) and a peak efficiency of 96.2% with RCR contributing a measured 61% reduction in total losses at light load for a 0.74% increase in solution volume.

Here we describe a gate-driver with resonant action that minimizes gating loss at high switching frequencies (10-20 MHz) while facilitating variable voltage gain that can exceed the supply rails. The gate voltage swing can be controlled with minimal duty cycle constraints, making this driver capable of meeting the diverse drive requirements of different switch technologies and converter topologies. A prototype uses two small N-channel gallium nitride (GaN) transistors within the drive structure, significantly decreasing parasitics. To do so, a capacitive decoupling technique is used to allow the high-side N- channel device's 'flying' driver to receive power; a distinct challenge for flying drivers commuting between two variable voltages. The prototype was applied to several high frequency switching devices. Up to a 72% reduction in gating-loss is observed as compared to a conventional hard-charged gate-driver while maintaining rise and fall times

Recent demonstrations of merged inductor-capacitor (LC) switching converters have resulted in record power densities being achieved at high voltage conversion ratios. To do so, sophisticated switch control schemes may be required. This work demonstrates N-phase and Split-phase switching techniques applied to a resonant Cockcroft-Walton converter. For the same hardware, the lower resonant switching frequency of the N-phase scheme significantly improves light-load efficiency relative to the Split-phase scheme. However, the N-phase approach suffers reverse body diode turn-on at large voltage ripple contributing to the Split-phase scheme obtaining the highest power density. Converter performance combining both switching techniques is analyzed using a discrete 1:5 Cockcroft-Walton converter implemented using gallium nitride FETs, multi-layer ceramic chip (MLCC) capacitors, and a 68 nH inductor. The resulting converter achieves a peak efficiency of 94.9% and 94% for the N-phase and Split-phase schemes respectively with the N-phase scheme seeing a 30% reduction in losses at light-load. The converter achieves a maximum output power of 190W, resulting in a record power density of 483.3 kW/liter (7,920 W/inch3) and specific power of 243 kW/kg.

Hybrid LC switched-capacitor converter architectures have demonstrated high power density while retaining efficiency at high conversion ratios. This work presents a resonant Cockcroft-Walton (CW) converter that achieves full zero-current switching (ZCS) on all switches using a single inductor and requiring only one current sensor. To do so, an N-phase clocking scheme is employed, eliminating the parallel paths that typically introduce transient shorting losses in a conventional 2-phase CW converter. The reduced voltage stress on the CW's fly capacitors results in a dramatic reduction in volume when using common MLCC capacitors. A discrete 1:5 CW prototype using silicon FETs and a spiral trace inductor was assembled on two commonly available PCB processes: 0.8 mm FR4 with 2 oz. Cu, and 0.127 mm polyimide film with 0.75 oz. Cu. The latter achieved a peak efficiency of 95% and a maximum power density of 0.686 W/mm3 (11.2 kW/inch3) in a volume of 44.5 mm3 (0.00271 inch3), excluding level-shifting and clock generation circuits.

A new wake-up receiver (WuRx) designed in 0.13 μm CMOS process is hybrid-integrated with a micro-electromechanical system (MEMS) RF resonator. While only consuming 166 nW of power (18.8 nW for the comparator and 147 nW for periphery), the WuRx is capable of detecting RF signals as weak as -60 dBm. In order to achieve this sensitivity, a passive voltage-boosting network comprised of a high quality factor (high-Q) piezoelectric MEMS resonator is utilized, in place of an inductor, to amplify the received voltages applied to a CMOS rectifier. The output of the rectifier is then applied to a low-power comparator used to set a logical bit that indicates when an RF signal has been detected. The trade-offs in designing the voltage boosting network are explained and an equation for the optimum number of rectifier stages is derived.

An in-line color and total phenolic sensor is described to track the color and total phenol evolution during red wine fermentations. The sensor uses multiple light-emitting diodes (LEDs) spanning the ultraviolet and visible spectrum, in particular 280 and 525 nm. The performance of phenolic sensor was evaluated by analyzing fermentation samples collected from multiple red wine fermentations performed during the 2012 season. The study confirmed that the LED phenolic sensor measurements strongly correlate with measurements performed with a reference UV-vis spectrophotometer and that in-line measurements can be made in a practical manner after removal of yeast and pulp with a 2.0 µm filter. The use of a 100 µm path-length flow cell avoids the need for dilution, making in-line measurements possible. The sensor provides in-line measurement on the evolution of the total phenolic content and color extraction patterns during red wine fermentations.

We consider the problem of adapting embedded software to heterogeneous devices where it is impractical to obtain a system-level power model for each target platform and operating environment. Our solution leverages the emerging capability of measuring power consumption at run-time using a built-in battery monitoring unit (BMU). We use a statistically rigorous design of experiments (DoE) methodology to efficiently characterize the power consumption configuration space of software online instead of constructing a system-level power model offline. This approach is simple, low-cost, and permits software to dynamically select suitable parameters at run-time to satisfy energy or performance constraints. We illustrate this approach using a camera trap application as a case study deployed on a Nokia N80 smartphone. © 2014 IEEE.

Purpose: Waste management for end-of-life (EoL) smartphones is a growing problem due to their high turnover rate and concentration of toxic chemicals. The versatility of modern smartphones presents an interesting alternative waste management strategy: repurposing. This paper investigates the environmental impact of smartphone repurposing as compared to traditional refurbishing using Life Cycle Assessment (LCA). Methods: A case study of repurposing was conducted by creating a smartphone "app" that replicates the functionality of an in-car parking meter. The environmental impacts of this prototype were quantified using waste management LCA methodology. Studied systems included three waste management options: traditional refurbishment, repurposing using battery power, and repurposing using a portable solar charger. The functional unit was defined as the EoL management of a used smartphone. Consequential system expansion was employed to account for secondary functions provided; avoided impacts from displaced primary products were included. Impacts were calculated in five impact categories. Break-even displacement rates were calculated and sensitivity to standby power consumption were assessed. Results and discussion: LCA results showed that refurbishing creates the highest environmental impacts of the three reuse routes in every impact category except ODP. High break-even displacement rates suggest that this finding is robust within a reasonable range of primary cell phone displacement. The repurposed smartphone in-car parking meter had lower impacts than the primary production parking meter. Impacts for battery-powered devices were dominated by use-phase charging electricity, whereas solar-power impacts were concentrated in manufacturing. Repurposed phones using battery power had lower impacts than those using solar power, however, standby power sensitivity analysis revealed that solar power is preferred if the battery charger is left plugged-in more than 20 % of the use period. Conclusions: Our analysis concludes that repurposing represents an environmentally preferable EoL option to refurbishing for used smartphones. The results suggest two generalizable findings. First, primary product displacement is a major factor affecting whether any EoL strategy is environmentally beneficial. The benefit depends not only on what is displaced, but also on how much displacement occurs; in general, repurposing allows freedom to target reuse opportunities with high "displacement potential." Second, the notion that solar power is preferable to batteries is not always correct; here, the rank-order is sensitive to assumptions about user behavior. © 2014 Springer-Verlag.

With recent advances in silicon nanophotonics, optical crossbars based on CMOS-compatible microring resonators have emerged as viable on-chip optical interconnection networks to deliver high-bandwidth communication at low power dissipation with a small footprint. This paper describes the design, fabrication and evaluation of an arbitration-free passive crossbar based on a microring resonator matrix that can be used to route wavelength division multiplexing (WDM) signals across the chip. The salient feature of the proposed design is the ability to support multicasting and many-to-one communication efficiently (without arbitration), which makes it suitable for implementing cache coherency protocols and on-chip interconnect in future many-core processors.

A separable electromagnetic coupler was designed, simulated, fabricated, and tested as part of a prototype eight-module multidrop memory bus. The coupler consists of broadside coupled traces, one on a rigid motherboard and the other on a flex circuit soldered to a daughter card. The zig-zag geometry of the traces reduces variation in the coupling coefficient due to horizontal and vertical misalignment of the coupler halves. Simulation and testing indicates that a target capacitive coupling coefficient of 0.34, which has been selected to balance signal-transmission-level requirements against motherboard impedance discontinuity effects, can be achieved with little variation over + / -12-mil alignment tolerance. In addition, custom interface circuitry was designed in conjunction with the coupler to enable 1.6-Gb/s data rate per differential pair. The prototype system was tested for an extended period executing read and write memory transactions for an estimated bit error rate less than 2.0e-17. Index Terms--Bus transfers, connector, coupled transmission lines, high-speed integrated circuits.