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This paper reports the design and implementation of an Armstrong power oscillator for wireless power transfer (WPT) using GaN HEMT (high electron mobility transistor) at 4.6 GHz and GaN FET at 40 kHz. In the first design, a low power depletion-type device is used, simulated and integrated with a magnetically coupled resonant (MRC) WPT system using PCBs. The second design is based on a higher power enhancement-type transistor, where it is simulated and compared with the first design. High quality AC output waveforms with low distortion are obtained, which leads to low electromagnetic interference (EMI) levels that are required for sensitive applications such as biomedical technologies.

This paper presents a design of a 3.5 GHz GaN Low Noise Amplifier (LNA) using Microstrip interconnect technology on a gold plated PCB and using packaged commercial GaN-on-SiC HEMTs. Cascode configuration with inter-stage matching and independent biasing networks was used. The whole design was fully implemented using Microstrip except for the capacitors and was optimized to reduce the noise figure (NF) and improve the gain and stability. The LNA provided a gain of 13.5 dB with a noise figure (NF) less than 3dB from 2.9 to 3.7 GHz with power consumption 2.92W.

This paper reports a design of a Cascode GaN Low Noise Amplifier (LNA) with independent biasing and inter-stage matching. The HEMTs are in a cascode configuration and they are independently biased with an inter-stage matching network. The CS stage is biased for a minimum noise figure (NF) and the CG stage is biased for a maximum linearity. The inter-stage matching is then maximizing the power transfer between the two stages. The LNA provided a gain of 13.5 dB with a NF less than 3dB from 2.9 to 3.7 GHz. The OIP3 is only 25 dBm with a power consumption of 2.92W.

This paper presents a design for 1–6 GHz low noise amplifier (LNA) based on cascade GaN HEMTs with LC ladder input matching and stabilizing output impedance. The designed LNA is simulated using Advanced Design Software (ADS) based on a commercial packaged transistor from Cree Inc. The LNA shows a maximum noise figure of 2.95 dB in the 1–6 GHz range with a gain of 14 dB. It also has a maximum S 11 of −2.4 dB, an input IP3 of 29.4dBm and is unconditionally stable over the whole bandwidth while drawing 13 Watts of DC power. The designed LNA also shows high linearity with more than 60 dBc carrier-to-intermediation distortion.