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A 7-nm leakage-current-supply (LCS) circuit monitors leakage across process and temperature variations and controls PFET block-head switches (BHSs) to supply the slow-changing leakage current while a high-bandwidth analog low-dropout (LDO) voltage regulator supplies the fast-changing dynamic current. By decreasing the LDO maximum current demand ( $I_{\mathrm{ MAX}}$ ), LCS test-chip measurements demonstrate a 70 mV (44%) reduction in the minimum dropout voltage ( $V_{\mathrm{ DO,MIN}}$ ), resulting in a wider voltage range of LDO usage for power savings of 14%–22%.

Conventional processors regulate the supply voltage (V DD ) and clock frequency (F CLK ) in two separate and independent control loops. A buck converter, switched-capacitor, or low-dropout (LDO) voltage regulator are example control loops for regulating V DD based on a reference voltage (V REF ). Processors commonly integrate a phase-locked loop (PLL) to separately regulate F CLK based on a reference clock frequency (F REF ), where the F CLK control loop is unaware of the impact of dynamic parameter variations such as V DD droops or temperature changes on the path-timing margin because the PLL voltage-controlled oscillator (VCO) operates on a separate analog voltage. For this reason, conventional processors require either V DD or F CLK guardbands or adaptive and resilient circuits to ensure correct functionality while in the presence of worstcase dynamic parameter variations [1].

We report on a 28nm product prototype test vehicle assembled back-to-face with a 4Gb 3× nm Wide I/O DRAM chip using Through Si Stacking (TSS) technology. The high bandwidth interface of the digital chip to the wide I/O memory chip is enabled by ∼1200 μ-bump joints with pitch as small as 40μm allowing for wide memory bandwidth. With appropriate chip floor-planning, we demonstrate the mitigation of any impact to digital circuit performance and yield from TSS and the possibility to re-use 2D circuit IP in a 3D product with minimal die size growth. Our 3DIC assembly process allows for a compact form-factor package with

In this work we have demonstrated, for the first time, a 0.605µm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the standby leakage, and lower Vccmin. The PU Vt and dual core oxide boundary were optimized to achieve robust Vccmin, process margin and reliability. The 45LPG thin core transistors and the DCO 8T SRAM are able to achieve 1.5GHz speed with ∼500mW at 0.9V and a low Vccmin of 0.6V.