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A class of single operational amplifier (OA) circuits is modified so that gain can be adjusted by varying two resistors. The theory is demonstrated by first order and second order circuits. The OA can be replaced by other devices such as FTFN, CCII, CFA. [ABSTRACT FROM AUTHOR]

This paper presents a new structure of an Orthogonal Signal Generator for a Phase Locked Loop (OSG-PLL), utilizing an Adaptive Notch Filter (ANF) in bandwidth as the foundation. The ANF employed to generate the orthogonal system within the Phase Locked Loop (PLL), is implemented from the parallel configuration of several Bandpass Filters (BPF), starting from a lattice-structured AllPass Filter (APF). This approach offers benefits such as simplicity and reduced sensitivity to coefficient rounding in fixed-point Digital Signal Processor (DSP) implementations. The bandwidth changes adaptively by adjusting and achieving the optimization of the filter coefficients. Two adaptation algorithms are proposed, studied, and analyzed, one utilizing Gradient Descent (GD) and another based on Proportional Control of Maximum Error (ME). A series of comparative simulations are conducted using MATLAB software to validate the most effective method among the two described algorithms. The simulation results from MATLAB and the experimental results from a fixedpoint digital signal processor (DSP), specifically the TMS320F812, are showcased and examined to assess the effectiveness of the algorithm of proportional control of the ME, which has been selected as the superior alternative, thereby supporting its theoretical development. [ABSTRACT FROM AUTHOR]

This paper proposes a systematic control design for a single-phase LCfiltered inverter considering uncertain system parameters. One major difficulty in controlling single-phase power converters is the lack of a direct conversion method for transforming single-phase signals into dq-frame signals. By employing an all-pass filter in this proposed approach, it is possible to control the output voltage in terms of DC quantity or the dqrotating frame. Furthermore, voltage stability and harmonic distortion (THD) minimization of the uninterruptible power supply (UPS) are major concerns in inverter design. Therefore, this controller uses integral action to get rid of steady-state errors and stabilize the closed-loop system by the state feedback control. In order to enlarge and guarantee the stability range in the presence of potential parameter fluctuations, an uncertainty model is being considered. In this context, the uncertainty models refer to the potential model with variations in the filter's inductance and capacitance caused by operating temperature, aging, and various external factors. The efficacy of the control approach is assessed through simulations and experiments, with the objective of comparing its results with those of the PI control using a control board featuring a TMS320F28335 digital signal processor. Consequently, the proposed approach offers lower THD at every load step with lesser afford in performance tuning in comparison to the PI method. [ABSTRACT FROM AUTHOR]

This article dealt the application of three-phase all-pass filter integrated with phase-locked loop (3Ø-APF-PLL) control approach in islanded electrical supply system for enhanced power quality (PQ). It also covers the effectiveness of proposed control under various operating conditions such as intermittent wind speed, variable solar irradiance, and unbalanced nonlinear load. An islanded electrical supply system includes wind energy generation, solar photovoltaic (SPV), and battery energy storage (BES). The proposed control technique provides a coordinated and balanced operation under a dynamical load. A 3Ø-APL-PLL-based control approach is proposed to extract the maximum value of fundamental component of load current and phase angle. The proposed control approach is utilized to operate voltage source converter (VSC) that performs multi-functions, such as reducing source current harmonics, power compensation (real & reactive), balancing of loads, and improving the overall power quality of the islanded SPV-wind-BES electrical supply system. The SPV system is developed using an incremental conductance (IC)-based maximum power point tracking (MPPT) technique to extract maximum power during the intermittent conditions of solar irradiance. A bidirectional controller (BDC) is designed to operate the charging/discharging modes of a BES. Generally, an islanded electrical supply system suffers from poor voltage & frequency regulation due to the intermittency of power generation sources, which can be solved by utilizing a BES with BDC control to manage the power leveling between the power generation sources and the unbalanced load. A 3Ø-APF-PLL control approach is compared to existing controllers like a least mean square (LMS) (Singh et al. in IET Power Electron 13:2767–2774, 2020) and second-order generalized integrator-based frequency locked loop (SOGI-FLL) (Golestan et al. in IEEE Trans Power Electron 34:213–224, 2018). Numerous parameters, such as the evaluation of the maximum value of the fundamental component, stability, steady-state error, and harmonic compensation capabilities, are taken into account when comparing 3Ø-APF-PLL to the control approaches described above. The dynamic parameters of the islanded electrical supply system are justified under the IEEE-519 standard. [ABSTRACT FROM AUTHOR]

A new universal active filter configuration is presented in this paper which is capable of realizing all three first-order filter responses namely all pass (AP), low pass (LP) and high pass (HP) using a single second generation voltage conveyor (VCII+), a virtually grounded capacitor and two resistors. The proposed circuit offers tunability of the cut-off frequency, gain (for HP filter) and simultaneous availability of two filter outputs, one at a low impedance node (HP/AP), the other output, namely the LPF will require a voltage buffer to avoid loading. The nonideal analysis of filter responses based on the nonideal model of VCII+ is carried out by considering all the parasitic immittances and nonideal gains and found that they have no significant effect on the performance of the proposed filter structure. Sensitivity analysis with respect to active and passive components has also been carried out. The functionality of the presented circuit has been validated through simulations and experimental results, where the VCII+ was implemented using the macro model of the commercially available CFOA IC AD844. Additionally, the proposed circuit has been tested using a CMOS VCII+ implemented with 0.18 μ m TSMC technology parameters. The tests include advanced evaluations based on Monte Carlo simulations. [ABSTRACT FROM AUTHOR]

It is shown that two other types of filters, viz., band-pass and band-reject, can be derived from a given all-pass filter. For illustration, we consider RC active all-pass filters, and show how starting from such a given circuit, one can obain band-pass or band-reject filters, simply by subtraction from, or addition to, unity, to the all-pass one. The corresponding circuit diagrams for implementations are also shown, and simulation plots have been drawn to illustrate the validity of the above facts. [ABSTRACT FROM AUTHOR]

Unbalanced loads are extremely prevalent in real systems, and they create power quality issues for the UPS system. To address this problem, this work provides an optimal voltage control scheme for a three-phase inverter using the linear matrix inequality method. In addition, the purpose of this controller is to provide a well-balanced three-phase sinusoidal voltage regardless of the imbalance of the loads. This symmetrical component-based controller features two paralleled voltage controls: a positive sequence to regulate output signals and a negative sequence to eliminate unbalanced voltages. Along with that, the optimization problem is formulated such that the convergence rate is maximized to obtain the output voltage as swiftly as possible. PSIM is used to carry out the simulation, and MATLAB is utilized to assist in determining the optimal control gain for the state feedback and integral control of each sequence. The control algorithm is then deployed utilizing an in-house designed control board together with a TMS320F28335 digital signal processor. To determine the efficacy of the proposed control, simulation, and experiment results are compared to those of an optimal controller without a negative sequence. [ABSTRACT FROM AUTHOR]

This research paper presents a symmetrical current-tunable active-RC all-pass filter that uses an active BJT coupled with R and C. The circuit's symmetrical structure ensures that the differential signals are treated equally, resulting in improved performance. Furthermore, the filter's ability to adjust the frequency by bias current makes it suitable for a wide range of applications, such as improving phase properties and creating other types of filters. The simulation results obtained through the Pspice program show that the value of the operating frequency can be adjusted by bias current, which is the highlight of this research. The transfer function of the circuit shows a response of about 0 dB and -90° respectively, indicating that the circuit can change the phase of the input signal without changing its magnitude. This feature is particularly useful in signal processing applications where phase changes are required. In addition, the paper discusses how the operating frequency can be increased by decreasing the capacitor. The transfer function of the circuit analyzed shows that the operating frequency (f0) is inversely proportional to the product of the capacitors. Therefore, decreasing the value of C increases the operating frequency of the circuit. Monte Carlo analysis results are also presented for resistors, capacitors, and transistors with error values. This analysis helps determine the effect of errors on the output signal of the circuit. The results show that the output signal is sensitive to changes in the resistor values, which can affect the accuracy of the filter. Therefore, it is important to select high-quality resistors to ensure that the filter operates accurately. [ABSTRACT FROM AUTHOR]

With the continuous enhancement of weak grid characteristics, the negative effects of grid voltage feedforward (GVF) and PLL on grid-connected inverters become more and more serious and are coupled. Therefore, it is difficult to effectively solve the system stability problem by only improving the PLL structure. Firstly, based on an improved phase-locked loop structure (CCF-PLL) with complex coefficient filter and considering the influence of GVF, the output admittance model of a grid-connected inverter is established. Through stability analysis, it is found that conventional GVF leads the total output admittance phase of the inverter, thus reducing the system stability margin under the weak grid. Then, an improved admittance remodeling strategy of the grid-connected inverter is proposed. An all-pass filter is introduced into the GVF loop to correct the phase of the total output admittance of the inverter, and the phase margin is used as the constraint to design the control parameters, which effectively improves the stability of the system under the weak grid. Finally, the simulation results show that, compared with traditional GVF, the proposed strategy can obviously improve the distortion of grid-connected current waveforms and improve system stability. [ABSTRACT FROM AUTHOR]

This article presents an overview of high-speed and high-performance continuous-time (CT) ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the CT ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth, and power efficiency.

A true‐time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non‐idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor‐less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non‐idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S11 and S22 parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW. [ABSTRACT FROM AUTHOR]

In this paper, two novel and compact structures of voltage-mode first-order all-pass filter are proposed. The first proposed structure is designed to provide non-inverting all-pass response only. It consists of only four MOS transistors and minimal number of passive elements i.e. one capacitor and one resistor. The proposed filter also offers the feature of high input impedance and is free from passive component matching constraints. Additionally, by including an inverting stage at the output, the first proposed design is extended to deliver both non-inverting and inverting all-pass responses simultaneously. Moreover, the proposed idea is further enriched with very essential feature of tunability by replacing the passive resistor with its active equivalent NMOS transistor. The theoretical analysis of the proposed design is verified with PSPICE simulation using TSMC 0.18 µm level-7 CMOS process parameters at supply voltage of ±0.9 V. Post layout verification is also explored to validate real time performance of proposed idea.

The optical all-pass filter (APF), which exhibits a constant amplitude response and a variable phase response, is a key to manipulating the optical phase without inducing signal amplitude distortion. High-order APFs are significantly demanded because they can afford large time delays and phase shifts. However, to date, only first-order APFs based on lossy waveguides have been reported. Although high-order APFs can be simply obtained by cascading multiple first-order APFs, the complexity and size are increased. To solve this problem, we propose and demonstrate a second-order APF using Mach–Zehnder interferometer-assisted microring resonators. The device is fabricated based on a silicon-on-insulator platform. Based on the second-order APF, an adjustable time delay between 553 and 948 ps is obtained, and the corresponding amplitude variation is less than 1.7 dB. Meanwhile, a microwave photonic phase shifter is also obtained based on the APF. The microwave phase shift can be adjusted from 0 to 3.27π, with an RF power variation within 2.4 dB. Additionally, the second-order APF can be reconfigured to a first-order APF, which significantly enhances its flexibility. The reconfigured first-order APF can realize an adjustable time delay between 257 and 429 ps, and the amplitude variation is less than 0.9 dB. The proposed high-order APF provides a novel approach to manipulating optical signals.

Guaranteeing privacy in released data is an important goal for data-producing agencies. There has been extensive research on developing suitable privacy mechanisms in recent years. Particularly notable is the idea of noise addition with the guarantee of differential privacy. There are, however, concerns about compromising data utility when very stringent privacy mechanisms are applied. Such compromises can be quite stark in correlated data, such as time series data. Adding white noise to a stochastic process may significantly change the correlation structure, a facet of the process that is essential to optimal prediction. We propose the use of all-pass filtering as a privacy mechanism for regularly sampled time series data, showing that this procedure preserves certain types of utility while also providing sufficient privacy guarantees to entity-level time series. Numerical studies explore the practical performance of the new method, and an empirical application to labor force data show the method's favorable utility properties in comparison to other competing privacy mechanisms. [ABSTRACT FROM AUTHOR]

In this paper, new Gm-C all-pass and amplitude-equalizer biquads are shown to be realized from a generalized Gm-C biquad filter structure by using Gm-simulated negative resistor in series with integrating capacitor in the lossless integrator. The non-ideality analysis of the all-pass/ amplitude-equalizer biquad using finite output conductance and parasitic output capacitance of Gm-cells is presented. The proposed Gm-C all-pass and amplitude-equalizer biquads are simulated for 0.18 μm CMOS technology with ± 0.9 V power supply in Cadence environment to validate the frequency response characteristics. For the Gm-C AP biquad filter designed for 1 MHz cut-off frequency and pole quality factor of 2, the power consumption is 82.37 µW, the input-referred noise is 137.6 μ V / H z and the dynamic range is 62.84 dB. The biquad has the figure of merit (FoM) of 0.2969 × 10−13 J. [ABSTRACT FROM AUTHOR]

In this paper, a novel complementary metal-oxide semiconductor (CMOS) transistors based first-order voltage-mode all-pass filter is proposed. The filter circuit employs six metal-oxide semiconductor (MOS) transistors and minimal number of passive components, i.e., a resistor and a capacitor. The core of the proposed filter is a CMOS inverting amplifier with unity gain. The proposed circuit exhibits some attractive features such as compact design, high input impedance and ability to provide non-inverting and inverting all-pass responses simultaneously. Additionally, it does not require any kind of passive element matching constraints. Furthermore, by replacing the passive resistor with an active negative channel metal-oxide semiconductor (NMOS) transistor, the proposed filter is enriched with the much-desired feature of tunability. The theoretical behavior is tested and demonstrated by carrying SPICE simulations using TSMC 0.18 μ m level-7 CMOS process parameters. [ABSTRACT FROM AUTHOR]

Unbalanced loads are extremely prevalent in real systems, and they create power quality issues for the UPS system. To address this problem, this work provides an optimal voltage control scheme for a three-phase inverter using the linear matrix inequality method. In addition, the purpose of this controller is to provide a well-balanced three-phase sinusoidal voltage regardless of the imbalance of the loads. This symmetrical component-based controller features two paralleled voltage controls: a positive sequence to regulate output signals and a negative sequence to eliminate unbalanced voltages. Along with that, the optimization problem is formulated such that the convergence rate is maximized to obtain the output voltage as swiftly as possible. PSIM is used to carry out the simulation, and MATLAB is utilized to assist in determining the optimal control gain for the state feedback and integral control of each sequence. The control algorithm is then deployed utilizing an in-house designed control board together with a TMS320F28335 digital signal processor. To determine the efficacy of the proposed control, simulation, and experiment results are compared to those of an optimal controller without a negative sequence.

In this paper, a lattice network-based second-order all-pass filter (APF) design is presented. Unlike previously published works, floating active inductors (FAIs) are used in the lattice topology. Inductance (L) and quality factor (Q) tunability of Q-enhanced FAIs are employed to ensure the designed APF is robust to process-voltage-temperature (PVT) variations and to make the filter’s group delay responses are constant for a wide frequency range. The operation of the proposed APF is verified by post-layout simulations using Cadence Design Suite in TSMC 65-nm CMOS technology. The operating frequency of the designed filter reaches 5 GHz with a delay range of 24.5-50 ps. The designed filter has a gain of -0.15 dB, which varies up to 1.47 dB in the operating frequency range. The group delay error is 114 fs, which is a 0.294% variation in the nominal case. The input-referred 1 dB compression point (P1dB) and the third-order interception point (IIP3) values are attained as -5.21 dBm and +9.19 dBm, respectively. At the nominal condition, the noise figure is achieved as 16.7 dB. The circuit occupies only 0.0189 μm2 while drawing 29 mA from a 1.5 V supply.

In this paper, two new first-order voltage-mode all-pass filters (APFs) are proposed. Each of the proposed APFs comprises a single modified DDCC-, and has high input impedance. The first and second APFs can provide first-order noninverting and inverting APF responses, respectively. As passive elements, the first APF comprises two grounded capacitors, and a floating resistor while the second one uses a grounded resistor, a floating resistor and a grounded capacitor. However, both of the APFs suffer from a matching problem. Two quadrature oscillators (QOs) obtained from the APFs are presented. Simulations of the APF and QO circuits are fulfilled via the SPICE program. Besides, diverse experiments for the APFs are made to verify the performances. [ABSTRACT FROM AUTHOR]

It is well known that fully differential signal processing is more advantageous than single-ended signal processing in a noisy environment, and is widely used in audio, video and other signal processing applications. This paper introduces a new fully differential configuration that contains a first-order low-pass (LP) filter, high-pass (HP) filter, and all-pass (AP) filter, all present within the same circuit design. The proposed fully differential configuration is simple and employs only one multiple-output current differencing transconductance amplifier and one grounded capacitor. The circuit has a wide operating frequency range (up to 73 MHz). The additional features offered by the proposed circuit include use of the lowest number of active and passive components, suitability of the integrated circuit chip, support of cascadability, electronic tunability, no passive component-matching restrictions, availability of all first-order responses, i.e., LP, HP, and AP, and low-level operating supply voltages. Non-ideal and parasitic analyses are investigated for the proposed circuit, and PSPICE simulation results are presented to verify the proposed theory. Additionally, the proposed fully differential LP filter circuit is experimentally verified using off-the-shelf ICs. Moreover, the cascading feasibility is demonstrated by realizing a fully differential nth-order LP filter. [ABSTRACT FROM AUTHOR]

First-order all-pass filter circuits, both non-inverting and inverting, could be the focus of this article, which could include the design and implementation of first-order all-pass filter circuits. Using a standard integrated circuit (IC): AD830, as well as a single resistor and a single capacitor, the proposed first-order all-pass filters could well be built. The AD830 is an integrated circuit (IC) manufactured by Analog Devices Corporation that is available for purchase. The pole frequency and phase response of the proposed all-pass filters could well be directly modified by attuning the resistor in the circuit. Aside from that, the output voltage has a low impedance, making it appropriate for use in voltage-mode circuits. In addition, the proposed first-order all-pass filter is used to design the multiphase sinusoidal oscillator, which serves as an example of an application wherein the oscillation condition can be adjusted without impacting the frequency. The gain and phase responses of the proposed all-pass filters, as well as their phase response adjustment, time-domain response, and total harmonic distortion of signals, are all shown via computer simulation using the PSPICE software, as well as their experimental results. For the proposed circuits, a statistical analysis is coupled with a Monte Carlo simulation to estimate the performance of the circuits. In accordance with the results of this study, a theoretical design suitable for developing a worksheet for teaching and learning in electrical and electronic engineering laboratories has already been developed. [ABSTRACT FROM AUTHOR]

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This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) $0.18~\mu \text{m}$ 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

This paper presents a steady-state comparison of two methods that generate an orthogonal voltage system for a single-phase Phase-Locked Loop (PLL) structure: a widely accepted one based on a Second Order Generalized Integrator (SOGI) and a new one based on a All-Pass Filter (APF) with Lattice structure. Both methods are very attractive because of their simple digital implementation, low computational load and good performance under harmonically distorted grid conditions and variable frequency, so they are a good alternative to other known methods. The paper derives and analyzes the full state space models of the two methods.It is shown that these two methods are equivalent in the most common operation conditions of distributed energy resources, although the APF structure is clearly better than the SOGI one because it maintains its orthogonal generation ability for any higher notch frequencies and any lower sampling frequencies. The comparative analysis were validated by simulation with MATLAB/Simulink and experimental results using a fixed-point DSP.

A current-mode first-order filter configuration simultaneously providing noninverting and inverting low-pass (LP) and high-pass (HP) responses depending on passive element choice is proposed. In addition, all-pass filter (APF) responses can be easily obtained with interconnection of LP and HP output currents. The proposed filter employs only two differential voltage current conveyors, a grounded resistor and a grounded capacitor, so it is suitable for integrated circuit realization. It provides the feature of high output impedance. It does not need any passive element matching constraints. A voltage-mode oscillator based on the inverting APF is presented as a typical application. The performance of the proposed configuration is verified through many SPICE simulation and experimental test results. [ABSTRACT FROM AUTHOR]

This paper proposes the starting method for position sensorless controlled interior permanent magnet synchronous motors (IPMSMs) by using all-pass filters. The starting of IPMSM position sensorless control is well known to be extremely difficult due to the lack of electromotive information. Therefore, IPMSM is often started and accelerated with the high-frequency signal injection in general, and then, the control algorithm is switched to position sensorless control without high-frequency injection in middle speed region. However, the acoustic noise due to high-frequency signal injection would occur, and the switching of control methods would cause some bumps. For this reason, IPMSM is desirable to be driven from the start to the steady state without high-frequency signal injection. This paper realizes to start the position sensorless controlled IPMSM without high-frequency signal injection by allpass filter with the assistance of the appropriate initial vector setting of each controller, under the assumption that the high-frequency signal injection is used only at standstill. Finally, this paper experimentally demonstrates the feasibility and the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Single-Phase Phase-Locked Loops (PLL) have become a crucial component of grid-tied power converters. PLL accuracy and fast response are important for control and protection purposes, especially in the presence of voltage harmonics and frequency variations. In this paper, a new PLL structure based on an Adaptive Notch Filter (ANF) is presented. This ANF, which generates the orthogonal system of the PLL, is implemented with an All-Pass Filter (APF) having inherent advantages, such as low sensitivity to coefficient rounding when implemented in fixed-point microprocessors and easy implementation in a Digital Signal Processing (DSP). Both simulation with MATLAB/Simulink, and experimental results on a fixed-point DSP, are presented and analyzed to evaluate the performance of the introduced PLL and to support the theoretical development. A set of comparative simulations between the proposed PLL and a some single-phase PLL described in the literature are conducted to validate the method.

In this paper, an inverter-based true time delay (TTD) cell for timed array receivers is proposed. The proposed TTD cell is designed in TSMC 0.18 µm CMOS technology for multi-GHz operations. The delay cell is made from an all-pass filter by Padé approximation. The first-order all-pass filter is built by combining a constant gain stage and a low pass stage based on the approximation. The constant gain stage consists of two NMOS transistors. The low pass stage is created with an inverter cell, cascaded with a PMOS transistor. Active true time delay cells are used in delay lines (commonly in cascaded topology) to develop a timed array system. Because of that, size of the TTD cell is critical and is an important design factor. So in this paper, an inductorless inverter-based wideband TTD cell is proposed. The wideband input impedance matching is achieved without bulky inductors using the resistive feedback technique in the inverter cell. More than wideband input impedance matching, flat gain, and flat delay response for the TTD cell are obtained with this technique. With the inverter-based input and complementary output structure, the TTD cell is a self-biased circuit. So, additional bias circuit is not needed. The proposed TTD cell consumes 8.7 mW from a 1.8 V supply. The achieved wideband delay is 10.6pS. Only 3% delay deviation over the 1–5 GHz band is observed, and this shows the excellent quality of the provided delay. The insertion loss is − 3.9 dB and is tolerable for a TTD cell. The input and output wideband impedance matching is ensured, and the S11 and S22 parameters are lower than -14.7 dB and − 10.9 dB, respectively. At last, the proposed TTD cell shows good linear performance, and IIP3 is around + 11.7 dBm. [ABSTRACT FROM AUTHOR]

Two novel resistorless structures of a first-order voltage-mode all-pass filter are presented in the paper. Both the structures employ a fully differential second-generation current conveyor (FDCCII) as the primary active element, in addition to an active resistor. A grounded capacitor is the only passive component used in both the structures. In both the structures, CMOS realization of FDCCII is utilized; hence, these structures are CMOS compatible. Some of the other highly demanded features possessed by the presented all-pass structures are: a simple circuit topology, electronic tunability, high input impedance, constraint-free operation in terms of passive component matching, and low sensitivity figures. The theoretical performances under ideal and non-ideal scenarios are presented in detail. Furthermore, the proposed idea is extended to an Nth-order voltage-mode all-pass filter and a quadrature oscillator to explore some of the possible applications. PSPICE simulation results verify the theoretical claims of the presented all-pass filters. [ABSTRACT FROM AUTHOR]

In this paper, a voltage mode all-pass filter design employing floating current sources (FCS) is proposed. The presented all-pass filter circuit contains two floating current sources, one grounded resistor and one floating capacitor. Furthermore, the PMOS transistors of the FCSs are replaced with dynamic threshold-voltage MOSFET (DTMOS) transistors. Due to the use of DTMOS transistors, power consumption and supply voltages of the filter circuit are reduced considerably, compared to the classical circuit. The gain and phase responses, input and output waves, the total harmonic distortion (THD) results, temperature performance, output noise voltage and Monte Carlo (MC) analyses of the all-pass filter are simulated. The simulation results of the proposed DTMOS based circuit are performed with the LTSPICE program using 0.18 μm TSMC CMOS process parameters. [ABSTRACT FROM AUTHOR]

A new filter operating in voltage mode and realizing all-pass function is proposed. The circuit requires a single current conveyor with an extra voltage input buffer stage and a floating capacitor, enjoys electronic tuning, needs input interface for easy connection and benefits by low output impedance, hence is load-insensitive and operable at twice the frequency range in comparison to other related circuits. In-depth theoretical and simulation studies are presented in support of the newly designed circuit. [ABSTRACT FROM AUTHOR]

The problem of active vibration control of weakly damped mechanical structures is potentially unstable modes of vibrations due to the positive feedback for some vibration modes. The paper will discuss the change of positive feedback on the negative one using all-pass discrete-time filters. These filters can be arranged in a cascade to stabilize many potentially unstable modes. The piezoelectric actuator as a source of force is used to damp vibration.

A true-time-delay line distorts wideband pulses and introduces errors if it has a nonlinear phase or a non-constant magnitude. In this brief, the energy of the error due to phase and magnitude deviations is analyzed. It is shown that the error energy is proportional to integral of the sum of squares of phase and magnitude deviations. This metric is used to draw design insights for equalizing the ac response non-idealities and to evaluate the efficacy of some of the active all-pass filter based true-time-delay lines reported in the literature. The proposed metric is shown to be a more reliable predictor of wideband pulse distortion than other measures that have been used in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a steady-state comparison of two methods that generate an orthogonal voltage system for a single-phase Phase-Locked Loop (PLL) structure: a widely accepted one based on a Second Order Generalized Integrator (SOGI) and a new one based on a All-Pass Filter (APF) with Lattice structure. Both methods are very attractive because of their simple digital implementation, low computational load and good performance under harmonically distorted grid conditions and variable frequency, so they are a good alternative to other known methods. The paper derives and analyzes the full state space models of the two methods. It is shown that these two methods are equivalent in the most common operation conditions of distributed energy resources, although the APF structure is clearly better than the SOGI one because it maintains its orthogonal generation ability for any higher notch frequencies and any lower sampling frequencies. The comparative analysis were validated by simulation using MATLAB=Simulink and experimental results using a fixed-point DSP. [ABSTRACT FROM AUTHOR]

Inverter‐side current feedback control (ICFC) has been extensively adopted in distributed generation systems because of its simple implementation and better consistency with actual operating conditions. At the same time, when there are a large number of background harmonics in the grid, capacitor voltage feedforward (CVF) is usually added to the system for its suppression. This method could make the system keep the first‐order characteristics under the analogue control. However, under digital control, due to the digital control delay, a reverse resonance peak will be generated in the loop gain, which makes the system unstable in the weak grid. In order to solve the aforementioned problems, this study proposes a feedforward phase compensation method of LCL grid‐connected inverter based on the all‐pass filter (AF). By introducing AF into the CVF channel, the phase lag in the range of reverse resonance peak frequency is compensated, so as to enhance the robustness of the system in the weak grid. At the same time, this study gives the detailed design process of the proposed method. Experimental results on a 3‐kW prototype are provided, and the effectiveness of the proposed control method is verified.. [ABSTRACT FROM AUTHOR]

Ionospheric dispersion causes severe distortions and ranging performance degradations of wideband global navigation satellite system (GNSS) signals. To compensate the non-linear and asymmetrical group delay of the dispersive ionosphere, an all-pass filter in the form of cascaded biquad sections was proposed in our previous study. On this basis, this paper develops an optimal delay-equalization all-pass filter by using the trust-region algorithm to construct the desired group delay and improve the fitting accuracy. The simulation results of the AltBOC(15,10) signal performance demonstrate that the proposed design is more accurate for distortion compensation and thus more effective for ranging bias mitigation than the previous approach. [ABSTRACT FROM AUTHOR]

This paper introduces four new resistorless circuits of first-order current-mode all-pass filter (CMAPF) based on dual-X current conveyor transconductance amplifier (DXCCTA). All the four circuits use a single DXCCTA and a capacitor for their realization. The main features of the proposed CMAPFs are: use of minimum active and passive components, resistorless realization, electronically adjustable pole frequency, easily cascadable, good sensitivity performance with respect to active and passive elements, low total harmonic distortion of output current (0.74%) and good operating frequency range (39.2 MHz). The non-ideal analysis of the proposed circuits has also been explored. Moreover, two applications of the proposed first-order CMAPF in terms of second order CMAPF and current-mode quadrature oscillator are also presented. HSPICE simulations have been carried out with 0.18 µm CMOS process parameters to validate the proposed circuits.

Single-Phase Phase-Locked Loops (PLL) have become a crucial component of grid-tied power converters. PLL accuracy and fast response are important for control and protection purposes, especially in the presence of voltage harmonics and frequency variations. In this paper, a new PLL structure based on an Adaptive Notch Filter (ANF) is presented. This ANF, which generates the orthogonal system of the PLL, is implemented with an All-Pass Filter (APF) having inherent advantages, such as low sensitivity to coefficient rounding when implemented in fixed-point microprocessors and easy implementation in a Digital Signal Processing (DSP). Both simulation with MATLAB/Simulink, and experimental results on a fixedpoint DSP, are presented and analyzed to evaluate the performance of the introduced PLL and to support the theoretical development. A set of comparative simulations between the proposed PLL and a some singlephase PLL described in the literature are conducted to validate the method. [ABSTRACT FROM AUTHOR]

Summary: This article describes the design of integrated linear group delay filters for analog signal processing (ASP) applications and their implementation through constant‐resistance lattice and bridged‐T networks. Unlike previously published works, our design method uses a recursive procedure as the basis for the synthesis of a suitable transfer function. Thanks to this method, filters with a more linear group delay characteristic and flat magnitude response can be obtained. Two filters are designed in a 0.13‐μm BiCMOS technology to demonstrate the method: a balanced lattice with a negative slope and an unbalanced bridged‐T of positive slope. [ABSTRACT FROM AUTHOR]