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In this paper, a family of nonlinear congruential generators (NLCGs) based on the digitized Renyi map is considered for the definition of hardware-efficient pseudorandom number generators (PRNGs), and a theoretical framework for their study is presented. The authors investigate how the nonlinear structure of these systems eliminates some of the statistical regularities spoiling the randomness of sequences generated with linear techniques. In detail, in this paper, a necessary condition that the considered NLCGs must satisfy to have maximum period length is given, and a list of such maximum period PRNGs for period lengths up to [2.sup.31] - 1 is provided. Referring to the NIST800-22 statistical test suite, two PRNG examples are presented and compared to well-known PRNGs based on linear recurrencies requiring a similar amount of resources for their implementation. Index Terms--Digital circuits, nonlinear systems, random number generators (RNGs), sequences.

In this brief, a family of discretized one-dimensional chaotic maps derived from the Sawtooth map is analyzed to evaluate its suitability for the integrated implementation of low-complexity digital pseudorandom bit generators (PRBGs). The proposed PRBGs, classifiable as nonlinear congruential generators, are investigated in terms of period length, statistical properties of the generated sequences, hardware complexity, and are compared with traditional PRBGs. Index Terms--Digital integrated circuits, discretized chaotic maps, pseudorandom bit generators (PRBGs).

In this paper, positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits. Positive feedback allows for significantiy reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints. The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction. PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters. Spectre simulations by using a 0.35-[micro]m CMOS process confirm that the proposed models are sufficiently accurate in practical cases. PFSCL, gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4. The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified. As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation. Index Terms--High speed, logic style, model, MOS current-mode logic (MCML), power efficient, source coupled logic.

In this brief, a novel strategy to design carry-skip adders is proposed. It allows to distribute bits into groups to achieve minimum delay, and consists of two steps. The first is a preliminary analytical sizing based on timing considerations, the second is a successive refinement to achieve the desired number of bits. The strategy is simple, systematic and general, thus, it is helpful to design in a pencil-and-paper approach, as well as providing an in-depth understanding of the optimum group sizing. Moreover, it allows to analytically estimate the minimum delay achievable before carrying out the design. The strategy proposed has been validated by applying it to the design of more than 50 adders, varying delay of logic gates used and number of bits. Analysis confirms that the strategy provides minimum delay in practical cases. Index Terms--Adders, carry skip, digital arithmetic, very large-scale integration (VLSI).

In this brief, a strategy to design high-fan-in multiplexers with minimum delay is proposed. The work extends the optimization proposed in Lin, 2000, to the case of switches with driving capability, that exhibit better performance in terms of noise immunity as well as being suitable for voltage scaling, which are becoming increasingly important properties in today's CMOS technologies. Moreover, the design strategy explicitly accounts for wiring parasitics in design equations. The criteria found are simple and useful right from the early design phases, as well as being independent of the technology used. In addition, an approximate expression of delay is given to predict the speed performance achievable for a given process before actually carrying out the optimized design. As a design example, a 256-input multiplexer was designed and simulated after extracting the parasitics from layout using a 0.35-[micro]m CMOS process. The predicted delay agrees well with simulation data. Index Terms--Address decoder, CMOS digital integrated circuits, column decoder, multiplexer, multiplexing.

In this paper a model to accurately evaluate even in a pencil-and-paper manner the oscillation frequency of a ring oscillator made up by a CML or ESCL differential gate is proposed. The model allows us to simply estimate the oscillation frequency changes due both to the bias current change and to process tolerances. The model was validated by Spice simulations on both 6- and 20-GHz technologies for the CML ring oscillator, and on 0.8-[micro]m CMOS process for the ESCL ring oscillator. The estimated oscillation frequency agrees with the simulated one. Indeed, average errors lower than 10% were found. Index Terms--Bipolar transistor circuits, circuit modeling, CMOS integrated circuits, current mode logic, emitter coupled logic, frequency estimation, high-speed integrated circuits, oscillators.

This paper deals with current mode logic (CML) and, in particular, models and optimized design strategies for MUX, XOR, and D flip-flop are presented. Both simple and accurate models for propagation delay are proposed. The models represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need only a few SPICE simulations to properly evaluate model parameters. The simple models show errors which are always lower than 20%, while accurate models have typical errors of 2%. Design optimization is in terms of bias currents giving minimum propagation delay, and it has been demonstrated that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 and 20 GHz, respectively. Index Terms--Bipolar logic device, bipolar transistor circuits, current-mode logic, digital integrated circuits, emitter-coupled logic, high-speed integrated circuits, MUX, switching circuits.