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Accurate alignment between the cavities in cavity-SOI (c-SOI) wafers and lithography on the wafer surface is essential to advanced MEMS production. Existing alignment methods are well defined, but often require specialized equipment or costly software packages available only in professional manufacturing environments. It would be beneficial for the microfabrication world to be able to utilize standard alignment techniques and tools that are easily available also in smaller MEMS fabrication units and especially the majority of research facilities. Therefore, we demonstrate a feasible method for c-SOI wafer alignment using an ASML PAS5500/100 wafer stepper with standard software configuration by relocating ASML alignment markers towards wafer's edges and utilizing a terracing process to reveal them for alignment. Moreover, we characterize the magnitude and behavior of image offset errors that are introduced using this method. The offset error is found to be inversely proportional to the value of the coordinate in each axis, resulting in images being shifted towards the center of the wafer. The measured offset errors are <160 nm, and are suitable for most applications. To further minimize these errors we propose a simple model or database of the offsets. We conclude that this alternative alignment method is feasible for a number of MEMS applications, and could promote increased integration of c-SOI technology into advanced MEMS production., Electronic Components, Technology and Materials

Accurate alignment between the cavities in cavity-SOI (c-SOI) wafers and lithography on the wafer surface is essential to advanced MEMS production. Existing alignment methods are well defined, but often require specialized equipment or costly software packages available only in professional manufacturing environments. It would be beneficial for the microfabrication world to be able to utilize standard alignment techniques and tools that are easily available also in smaller MEMS fabrication units and especially the majority of research facilities. Therefore, we demonstrate a feasible method for c-SOI wafer alignment using an ASML PAS5500/100 wafer stepper with standard software configuration by relocating ASML alignment markers towards wafer's edges and utilizing a terracing process to reveal them for alignment. Moreover, we characterize the magnitude and behavior of image offset errors that are introduced using this method. The offset error is found to be inversely proportional to the value of the coordinate in each axis, resulting in images being shifted towards the center of the wafer. The measured offset errors are <160 nm, and are suitable for most applications. To further minimize these errors we propose a simple model or database of the offsets. We conclude that this alternative alignment method is feasible for a number of MEMS applications, and could promote increased integration of c-SOI technology into advanced MEMS production.