Chui, Yew Leong, Ramli, Abdul Rahman, Perumal, Thinagaran, Sulaiman, Mohd Yusof, Ali, Mohd Liakot, Chui, Yew Leong, Ramli, Abdul Rahman, Perumal, Thinagaran, Sulaiman, Mohd Yusof, and Ali, Mohd Liakot
Digital Matrix System (DMS) is well known as sound management system that is specifically designed to provide an intelligent solution to meet the high expectation and distinctive demands of latest Public Addressing (PA) System. On the other hand, Digital CCTV System (DCS) is installed separately to expand the capability of moving object visualization. However, the operation of DCS is mutually exclusive to the management range of DMS. So, the development of Multimedia Digital Matrix System (M-DMS) is worth to provide an integrated solution with both DCS and DMS functionality. As a result, a new framework of Multimedia Public Addressing (M-PA) System is proposed. The essential of multimedia support in M-DMS is high-speed digital interfacing technique. In this case, back plane communication technique has been changed from parallel architecture to serial. So, switch fabric would be a good choice for serial back plane design. The communication backbone of M-DMS is designed to be in star topology. Optical fiber is used as physical communication media to provide better performance in transmission speed, bandwidth, electro-magnetic effect, and noise tolerance. Due to the issues of signal integrity in high-speed digital design, a new adaptive channel synchronization algorithm has been developed. The algorithm, named as hybrid-reset algorithm utilizes the nature of asynchronous reset to compensate the drawback of synchronous counter for phase detection. The hybrid-reset algorithm is successfully solved the most well known problem of channel synchronization in data oversampling method. The problem is about the incapability of embedded clock extraction from serial data stream with unpredictable center of data eye. Besides, the algorithm enables an accurate prediction to the center of data eye with an even number of oversampling clock to data rate ratio. This feature is valuable to simplify the process of frequency synthesis. The algorithm is implemented in programmable logic pl