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Despite of the fact that thousands of CD-SEM (critical dimension scanning electron microscope) images are acquired in a daily basis in a fab, limited metrology is performed. Usually these images will not serve other purposes after they are collected and measured, but as they are stored, post-process analysis can be applied. Initially, most of these images are used to perform CD metrology, even though many other types of metrics could be extracted from the same images, especially when using contour metrology. In this paper two use cases will be explored, where contour-based image processing is performed on typical inline metrology targets. In both cases, initial intended metric was CD but thanks to contour based image computing, complementary information can be extracted. In the first use case, CD and overlay metrics can be extracted, while in the second CD, etch slanting and asymmetry analysis is performed across the wafer. Contour-based metrology offers new capabilities to dissociate several layers (e.g. via and line) or elements (e.g. top and bottom) in the image so that interlayer and intralayer metrics, other than width dimensions, can be computed. Besides, a solution not integrated in the tool provides excellent versatility to re-process images, thus allowing the obtention of new metrics, which can be very helpful also for retro-analysis.

Galileo Galilei once quoted: “Measure what is measurable, and make measurable what is not so”. In silicon manufacturing R&D phase, it often happens that engineers would like to access some parameter values that are not easy, even impossible to measure. When looking at a CDSEM image, the parameters of interest seem easy to extract but in practice getting access to them in a robust and reliable way is not always simple. Developing a contour-based metrology tool coupling robust contour extraction with a comprehensive contour metrology environment could help to bridge this gap. In previous works, it has been shown that SEM images contain significant amounts of information that can be extracted and analyzed using efficient contour extraction and analysis toolboxes [1, 2]. Also, the concept of implementing remote contour-based metrology has been introduced. The present work continues to unveil what can be achieved with such solutions. For that, the example of implant layers’ process assumption will be explored. During this process step, counter doping problems can occur for example when the distance between layers deviates from nominal. Therefore, it is crucial for design rule control to measure some critical dimensions such as minimum distance between layers, corner rounding, slope, etc. However, given the characteristics of the different structures in the images, which may come from different layers and/or processes steps, the measurements are not straightforward to extract with standard CDSEM metrology algorithms. Moreover, recipes are complex to setup, measurements by themselves are not very stable, and usually an indirect determination of the key figure is performed. In this paper, we will show that multilayer contour-based metrology, mixing image contour and GDS layout, allows to overcome the previously mentioned difficulties, as well as to generate measurements that are not possible to be performed by using standard algorithms.

There has been a significant increase of optical applications in the last decade, either embedded into complex multifunction devices such as smartphones, or for imaging purpose as cameras. Core of such optical systems are microlens arrays, used for light gathering or light emitting. The most commonly used manufacturing method by the industry is the thermal reflow of photoresist polymer. The method consists in melting previously patterned photoresist dots in order to form the lenses. But the resist shaping into a microlens is not as straight forward, since the final microlens needs to match shaping criteria to maximize the device optical efficiency. The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps. This would help designers and lithographer to evaluate beforehand the final shape of a certain design at the end of the process flow. It would then offer the possibility to identify from the start the correct design to embed onto the photomask guaranteeing the fabrication of the desired microlens. A 3D compatible and computation efficient reflow simulation software is proposed in this paper, in line with a Design Process Technology Co-optimization (DTCO) approach. It allows the fast 3D reflow simulations of hundreds of different resist patterns, taking as input a CAD design and returning the corresponding 3D microlens that will be formed. The purpose of this paper is to present the developed reflow modeling software solution and its calibration methodology. The use of the proposed alternative simulation flow for microlens optimization in a Resolution Enhancement Technics (RET) environment will also be described.

In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted. This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox. Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

From the first digital cameras which appeared during the 70s to cameras of current smartphones, image sensors have undergone significant technological development in the last decades. The development of CMOS image sensor technologies in the 90s has been the main driver of the recent progresses. The main component of an image sensor is the pixel. A pixel contains a photodiode connected to transistors but only the photodiode area is light sensitive. This results in a significant loss of efficiency. To solve this issue, microlenses are used to focus the incident light on the photodiode. A microlens array is made out of a transparent material and has a spherical cap shape. To obtain this spherical shape, a lithography process is performed to generate resist blocks which are then annealed above their glass transition temperature (reflow). Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product. The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.

For C040 technology and below, photolithographic depth of focus control and dispersion improvement is essential to secure product functionality. Critical 193nm immersion layers present initial focus process windows close to machine control capability. For previous technologies, the standard scanner sensor (Level sensor - LS) was used to map wafer topology and expose the wafer at the right Focus. Such optical embedded metrology, based on light reflection, suffers from reading issues that cannot be neglected anymore. Metrology errors are correlated to inspected product area for which material types and densities change, and so optical properties are not constant. Various optical phenomena occur across the product field during wafer inspection and have an effect on the quality and position of the reflected light. This can result in incorrect heights being recorded and exposures possibly being done out of focus. Focus inaccuracy associated to aggressive process windows on critical layers will directly impact product realization and therefore functionality and yield. ASML has introduced an air gauge sensor to complement the optical level sensor and lead to optimal topology metrology. The use of this new sensor is managed by the AGILE (Air Gauge Improved process LEveling) application. This measurement with no optical dependency will correct for optical inaccuracy of level sensor, and so improve best focus dispersion across the product. Due to the fact that stack complexity is more and more important through process steps flow, optical perturbation of standard Level sensor metrology is increasing and is becoming maximum for metallization layers. For these reasons AGILE feature implementation was first considered for contact and all metal layers. Another key point is that standard metrology will be sensitive to layer and reticle/product density. The gain of Agile will be enhanced for multiple product contribution mask and for complex System on Chip. Into ST context (High mix logic Fab) in term of product and technology portfolio AGILE corrects for up to 120nm of product topography error on process layer with less than 50nm depth of focus Based on tool functionalities delivered by ASML and on high volume manufacturing requirement, AGILE integration is a real challenge. Regarding ST requirements “Automatic AGILE” functionality developed by ASML was not a turnkey solution and a dedicated functionality was needed. A “ST homemade AGILE integration” has been fully developed and implemented within ASML and ST constraints. This paper describes this integration in our Advanced Process Control platform (APC).

Critical dimension and overlay measurements have become a key challenge in microelectronics process control, and the weight of metrology in the success of a patterning technique is increasing. For the 14 nm node, the limit of scanner resolution can be overcome by double patterning, which requires a maximum overlay variability of 3 nm between the two reticles of the first metal level. In the double patterning case of metal layers, critical dimension of line spaces and overlay are no longer independent. In this paper, the possibility of a common measurement after the second lithography is studied. Scatterometry has been used to fit successfully the critical dimension of the two sublevels. As sensitivity to overlay is too low in device-like target, a strategy has been implemented from diffraction-based overlay measurement. So it becomes possible to provide information on the lithography step quality before the second etch process to enable rework if necessary. Finally a scatterometry target has been designed to fit simultaneously the two critical dimensions and overlay. This target, which is designed to maximize overlay sensitivity, has been placed in the next 14 nm CMOS product and is expected to make this scatterometry method even more attractive.

Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.

Directed self-assembly (DSA) of block copolymers has shown interesting results for contact hole application, as a vertical interconnection access for CMOS sub-10 nm technology. The control of critical dimension uniformity (CDU), defectivity, and placement error (PE) is challenging and depends on multiple processes and material parameters. This paper reports the work done using the 300-mm pilot line available in materials to integrate the DSA process on contact and via level patterning. In the first part, a reliable methodology for PE measurement is defined. By tuning intrinsic edge detection parameters on standard reference images, the working window is determined. The methodology is then implemented to analyze the experimental data. The impact of the planarization process on PE and the importance of PE as a complement of CDU and hole open yield for process window determination are discussed.

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.

Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to reduce CD dispersion. After a global CD budget evaluation at SPIE08 [1], we have been focusing on Intrafield CD corrections using Dose Mapper™[2]. The story continues and since then we have pursued our intrafield characterisation and focus on ways to get Dose Mapper™ dose recipe created be fore the first silicon is coming. In fact 40nm technology is already more demanding and we must be ready with integrated solutions for 32/28nm node. Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We won’t talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers regarding intrafield CD compensation are available in the litte rature but they do not necesserally fit logic manufacturing needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we correct upfront an Etch chambe r CD profile combined with a mask and scanner CD signature? How can we get intrafield map from random logic devices? This is what we will develop in this paper. Keywords: Photolithography, Immersion, Optical CD, Mask, Intrafield, Dose Mapper

Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (

A new interferometric method for trench depth monitoring in micromachining applications is presented. As compared to other interferometric techniques, this new method uses a Wollaston prism to generate two linearly polarized beams, which are recombined after reflection on the sample. This differential method, by taking advantage of the polarization properties of the light allows an accurate monitoring of the trench depth. New insights on interferometry are given, in particular it is shown that an optical model taking into account the effect of the mask evolution and its etching during the process leads to an improvement of the precision of the measurements. The application of this new interferometric method to two different processes is presented. This will show that real time Twin-Spot interferometry appears as a powerful technique for deep trench monitoring in micromachining applications.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.