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One of the many constraints of high numerical aperture extreme ultraviolet lithography is related to resist thickness. A critical consequence of moving from the current 0.33 to 0.55 NA (high NA) is depth of focus reduction. The question we seek to answer in the present study is how the resist thickness reduction, required to compensate for the drop in NA, impacts the e-beam metrology needed to characterize the process. The impact of film thickness on e-beam metrology was first investigated by critical dimension scanning electron microscopy (CD SEM) using our current best-known methods (BKMs). Optimized settings minimizing such an impact were then studied using CD SEM as well as low-voltage SEM. Atomic force microscopy was used to accurately characterize the sample thickness. Our results indicate that alternative operating conditions and BKMs are sometimes needed to meet the metrology requirements. However, even in the case of materials showing a large sensitivity to resist thinning, we were able to identify e-beam imaging conditions capable of meeting metrology specifications.

ispartof: JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3 vol:21 issue:2 status: published

The feasibility of using EUV lithography in high volume manufacturing makes the technology a very strong candidate for sub 20nm patterning[1,2]. However defect control remains a major challenge even today. The aim of this paper is to understand propagation of the programmed defects present on the EUV mask to wafer to get an understanding of how stochastic defects may evolve through processes and how we can mitigate it. The propagation of programmed defects from mask to post lithography to post etch at wafer level on wafers exposed on a NXE:3400 EUV lithography module with a simple stack coated with a Chemically Amplified Resist (CAR) with an in-house defectivity mask was studied (Figure 2: stack post etch- see full abstract). We focused on 32nm line/space pitch size, with mask bias of 14.5/17.5(17.5nm absorber lines on mask). We focused on 5 different types of programmed defects with varying dimensions. The programmed defects are organized as a matrix of line bridges(bumps) in a 15x10 array distribution. The biggest line bridge has a size of 20x40nm decreasing down with a fixed step size for each defect type. The smallest line bridge has a size of 6x6nm (Figure 1- see full abstract). The evolution of the defects from mask to wafer post lithography and post etch has been studied both theoretically by calculating change in defect area from a modelled script as well as experimentally with e-beam inspection and other metrology techniques. The end goal is to study the propagation of these programmed defects from post lithography to post etch on wafer through parameters like defect area, defect sizes and stack height information. References [1] EUV Mask and Wafer Defectivity: Strategy and Evaluation for Full Die Defect Inspection; Ravi Bonam, Hung-Yu Tien2, Acer Chou2, et al. [2] The analysis of EUV mask defects using a wafer defect inspection system; Kyoung-Yong Cho, Joo-On Park, Changmin Park, Young-Mi Lee, In-Yong Kang, Jeong-Ho Yeo et al.

High Numerical Aperture (NA) EUV lithography will require very thin resist films. This reduction in thickness will challenge most metrology techniques, except for Atomic Force Microscopy (AFM). Indeed, thinner resist films allow AFM to reach a better depth accuracy and a higher throughput. In this work, we demonstrate the capabilities of AFM metrology on 16-nm half-pitch resist lines obtained with 5 resist film thicknesses ranging from 10 to 30 nm. As we show, AFM provides relevant information about the pattern dimensions (resist height, line top roughness) as a function of exposure dose, and even about the bottom trench roughness on films with thickness < 10 nm.

Nanosheet Field-Effect Transistors (FETs) are candidates to replace today’s finFETs as they offer both an enhanced electrostatic control and a reduced footprint. The processing of these devices involves the selective lateral etching, also called cavity etch, of the SiGe layers of a vertical Si/SiGe superlattice, to isolate the future vertically stacked Si channels. In this work, we evaluate the capabilities of various conventional Critical Dimension (CD) and alternative spectroscopic techniques for this challenging measurement of a buried CD. We conclude that Raman and energy-dispersive X-ray spectroscopies are very promising techniques for fast inline cavity depth measurements.

Beyond the 5nm technology node, interconnect scaling has an impact on metal material selection: usage of copper may hit a limit with respect to resistance and reliability performance [1]. Thickness of barrier and liner (required for copper) cannot be reduced further, meaning that trench width reduction will have a negative effect on the relative copper volume. Grain boundary scattering increases as well, which in turn further increases resistivity and resistance. One of the best alternatives is Ruthenium (Ru), but dual-damascene processing is difficult with Ru (requires improvements in Ru filling of narrow high aspect ratio trenches and in Ru CMP selectivity and defects). So, a Back End of Line (BEOL) material change may require a move to a semi-damascene integration with direct Ruthenium metal etch [2]. This shift from a well-known dual-damascene flow, based on metal CMP, to a semi-damascene flow, based on metal etch integration, will require a new set of metrology capabilities, which are studied in this paper. In the current study, Scatterometry is widely used in all semi-damascene process steps to monitor both dimensional and material properties. Important measured parameters include thickness, full profile details, grain size, and roughness of metal lines—all parameters that are required for feedback and in-line process control. We will describe how these parameters can be monitored using a single Scatterometry metrology system. The semi-damascene process development described in this paper exploits EUV lithography at a critical dimension (CD) of 16 nm and 32 nm pitch and includes the optimization of the following process steps: 1. Metal deposition techniques: ALD and PVD, with a wide range of metal thickness. 2. Anneal , affecting grain size. 3. Etch process , for optimal metal line profile and roughness. The Scatterometry results were evaluated and verified by reference techniques such as CDSEM, and HAADF-STEM. The goal of the process optimization was Ru resistivity and resistance. In-line Scatterometry was shown to accurately predict the resistance of the Ru lines — parameter that is measured at the end of the processing, and is affected by all processes, including deposition, annealing, and etch. Prediction was carried out by a machine learning algorithm, based on an E-test, combining the contribution of all three process steps into a single output, at the post-etch measurement phase.

Atomic Force Microscopy (AFM) is a proven technique applied in research environments, most commonly in materials science and biological research. More recently, requirements in semiconductor manufacturing advocate that probe microscopy has potential to assist with the new metrology techniques associated with device scaling and the corresponding increase in 3D structures. In this paper a novel form of AFM called the Rapid Probe Microscope (RPM) will be demonstrated operating at high data acquisition rates; with images collected in seconds, combined with the ability to characterise individual 3D structures with sub nanometre accuracy. The capability of the RPM will be illustrated by measuring a suite of 2D EUV posts of 26nm dimension in staggered topology with 40nm minimum pitch. These structures were developed as part of IMEC’s EUV lithography patterning development program. The high throughput of the RPM enables the collection of multiple site and multiple pitch data, from a focused exposure matrix. Automated batch processing tools have been developed to enable the effective analysis of the high volume of data produced. The data can then be extensively interrogated to fully understand how the structure of the posts is related to the lithography process. In addition to a statistical analysis of the entire pillar population, the analysis tools can isolate and measure each individual pillar, providing the ability to compare the height and shape on an isolated pillar by pillar bases.

The vapor-phase deposition of 11-azidoundecyltrimethoxysilanes at reduced pressure and elevated temperature allows the introduction of azido (N3) functionalized silicon wafer substrates. This process can be optimized by controlling the amount of surface adsorbed water and results in uniform and reproducible self-assembled monolayers (SAMs). The N3-SAM density as investigated via TOF-SIMS is comparable on thermal oxide and Si3N4substrates. Furthermore, it is demonstrated that biomolecules can be successfully conjugated on both substrates using azide-alkyne ‘click’ reactions.

The process characteristics, the surface chemistry, and the resulting film properties of Ru deposited by atomic layer deposition from (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0) (EBECHRu) and O2 are discussed. The surface chemistry was characterized by both combustion reactions as well as EBECHRu surface reactions by ligand release. The process behavior on TiN starting surfaces at 325 °C was strongly influenced by Ti(O,N)x segregation on the growing Ru surface with consequences for both the growth per cycle as well as the film properties. For optimized process conditions, the films showed high purity with low C and O concentrations of the order of 1020 at./cm3. Higher deposition temperature led to strong (001) fiber texture of the films on SiO2 starting surfaces. Annealing in forming gas improved the crystallinity and led to resistivity values as low as 11 μΩcm for Ru films with a thickness of 10 nm.

With the Area Selective Deposition (ASD) technique, the material is deposited on desired areas of the sample surface. The control of such process implies accurate characterization of the deposited material on both growth and non-growth surfaces. This requires, first a good measurement capability to quantify the geometry of the deposited layer, and second, a proper assessment of the process selectivity. In this work, we show how to combine two complementary measurement techniques to overcome their individual inherent limitations1 for ASD applications. Scatterometry, the first measurement technique, has been applied to the characterization of the deposited layer geometry properties because of its high sensitivity to dimensional features and material. To complement the ASD performance characterization with the local information, Atomic Force Microscopy (AFM) has been used to access the topography details of the analyzed surfaces. We have analyzed the AFM images with the power spectral density (PSD) approach to identify undesired material deposition in the non-growth area and thus to characterize process selectivity through the comparison to a reference sample. Experimental validation of the scatterometry and AFM techniques for ASD applications has been done on wafers having various selectivity levels. The scatterometry metrology measured accurately the thickness of the deposited layer on both growth and non-growth areas when the deposited layer became uniform. The lateral overgrowth was quantified as well with the same technique and showed some changes from process condition to another. In addition, the PSD analysis applied to the AFM images was able to probe minutely the nanoparticles nucleation on the non-growth area and as result has revealed the selectivity transition regimes. Later, we have built a hybrid model by the combination of the 2 metrologies results and validated its predictions on test wafers.

Power Spectral Density (PSD) is now a standard analysis for pattern roughness process control in advanced patterning. Due to PSD analysis sensitivity coupled with Scanning Electron Microscopy (SEM), line edge roughness (LER) and line width roughness (LWR) are more understood. However, this is applied on sides of the line, and has limited information about roughness on top of the pattern. On the other hand, Atomic force microscopy (AFM) measure accurately the topography of pattern and even if this metrology is probe size dependent, the top of the patterned lines is well revealed when trenches are too narrow to be measured. In this work, we have adapted and applied the PSD analysis on patterned lines measured by AFM. Specific algorithm has been developed to localize the analysis on top of the line. This allow us to report on the effect of processes, such EUV resist smoothening and Area Selective Deposition (ASD).

The epitaxial growth of Si layers on Si substrates in the presence of O atoms is generally considered a challenge, as O atoms degrade the epitaxial quality by generating defects. Here, we investigate the growth mechanisms for Si epitaxy on O atomic layers (ALs) with different O-contents and structures. O ALs are deposited by ozone (O3) or oxygen (O2) exposure on H-terminated Si at 50 °C and 300 °C respectively. Epitaxial Si is deposited by chemical vapor deposition using silane (SiH4) at 500 °C. After O3 exposure, the O atoms are uniformly distributed in Si-Si dimer/back bonds. This O layer still allows epitaxial seeding of Si. The epitaxial quality is enhanced by lowering the surface distortions due to O atoms and by decreasing the arrival rate of SiH4 reactants, allowing more time for surface diffusion. After O2 exposure, the O atoms are present in the form of SiOx clusters. Regions of hydrogen-terminated Si remain present between the SiOx clusters. The epitaxial seeding of Si in these structures is realized on H-Si regions, and an epitaxial layer grows by a lateral overgrowth mechanism. A breakdown in the epitaxial ordering occurs at a critical Si thickness, presumably by accumulation of surface roughness.

The solid state reaction of an ultra-thin Ni film (6nm) with Si:P epi layers (P: 0.7 to 4.0%), grown on 300-mm Si wafers, is studied as a function of different rapid thermal process (RTP) annealing temperatures (250-550?C) before and after applying a selective etch. The films are characterized using sheet resistance (Rs), mass, glancing incidence X-ray diffraction (GIXRD), X-ray reflectivity (XRR) atomic force, scanning electron and transmission electron microscopy (AFM, SEM and TEM) analyses to follow the onset of the Ni reaction, the evolution of the different phases formed within the Ni-Si system and to investigate the NiSi film properties. Results demonstrate that, though the Ni conversion to form an intermediate Ni-rich silicide phase is complete at 300?C, showing no dependency on the P content, the complete transformation (to form low resistive NiSi) shows a temperature dependence with P content (350?C vs 400?C for 0.7% P and 2.0-4.0% P). Despite the delay in silicidation completion, the NiSi films exhibit comparable layer properties, for all P contents. All films show a uniform conversion with a similar volume expansion (2.1), good interface properties, comparable resistivity (18-20µ??cm) and exhibit a smooth morphology with limited rms roughness increase (0.37 to 0.56nm). The thermal stability studies carried out on NiSi, post RTP anneals, shows a different Rs stability (650 and 575?C for 0.7% and 2.0-4.0% P), while the morphological and phase stability is found to be similar (?500?C) for all P contents. The contact resistance measured using Circular Transmission Line Model (CTLM) structures for the synthesized NiSi films is found to be 4.8×10-8 and 1.2×10-8??cm2 for 0.7% and 4.0% P respectively, the latter meeting the requirements for 10-nm CMOS technology node as predicted by International Technology Road Map for Semiconductors (ITRS). Display Omitted The reaction of ultrathin Ni film with Si:P epi layer (P: 0.7 to 4.0% P) is studied.The silicidation reaction onset and completion show a dependency with P content.Independent of P content, comparable surface/interface properties are observed for NiSiContact resistivity using 4% P meets the ITRS requirements for 10nm technology nodes.

© 2018 Society of Photo-Optical Instrumentation Engineers (SPIE). As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: line width roughness (LWR) specifications are expected to be 2 μm and the need to correct for scanning electron microscope (SEM) noise]. We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec roughness protocol - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such as LWR, everyone speaks the same language, which is not currently the case.

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Year after year, the semiconductor industry overcomes a tremendous amount of technical challenges to satisfy Moore’s law. Through innovative device architectures, smart design, new integration and patterning concepts, better tools and new materials, the industry has successfully reached the 7nm technology node. Both design and patterning options are identified and the high volume manufacturing readiness is expected end of 2018. Today, the industry is preparing for the 5nm technology node (N5) while research centers start identifying and exploring the different patterning options for the 3nm technology node. The former targets a Metal 2 Pitch (M2P) of 32nm and a Contacted Poly Pitch (CPP) of 42nm while the latter aims for a M2P of 24nm and a CPP of 32nm. At such tight metal pitches and in view of the continuous progress in EUV tool performance, a single print EUV lithography is considered as a potential patterning option for N5 to pattern critical Back-End-Of-Line (BEOL) layers such as block, via and unidirectional metal lines. However, without the emergence of improved EUV photoresist (PR) platform that meets requirements for resolution, line edge roughness and sensitivity, we can expect a very limited available PR budget for pattern transfer (between 12nm and 30nm), an increase of defects such as bridging or line interruptions and finally a degradation of the sidewall roughness. These will contribute to the total CD variation and consume an important part of the overall Edge Placement Error (EPE) budget. Hence, actual patterning methods used to smooth and transfer down the PR pattern must be significantly improved and new solutions must be explored to enable the emergence of advanced technologies. In this work, we explore different post-lithography methods to overcome challenges related to EUV-based patterning at tight pitches. Both chemically amplified PR and metal-based PR are considered and the performance of the different approaches are evaluated step-by-step using top down SEM imaging, cross-section SEM and 3D-AFM. Finally, we complete the study showing Power Spectral Density (PSD) analysis that help to understand how the roughness is distributed in the frequency domain for the different studied methods.

© 2015 Elsevier B.V. All rights reserved. The impact of different Ru precursors and/or deposition methods on the electrical characteristics of Ru/SrTiOx/Ru capacitors has been investigated. The observed increase of the leakage current density (Jg) and the equivalent oxide thickness (EOT) for ALD (atomic layer deposition) deposited Ru layers compared to PVD (physical vapor deposition) deposited ones was found to be caused by a SrRuTiOx layer formation at the SrTiOx/Ru interface aided by the presence of the oxygen co-reactant used during the ALD, regardless of the precursor used. publisher: Elsevier articletitle: Understanding the EOT–Jg degradation in Ru/SrTiOx/Ru metal–insulator–metal capacitors formed with Ru atomic layer deposition journaltitle: Microelectronic Engineering articlelink: http://dx.doi.org/10.1016/j.mee.2015.04.076 content_type: article copyright: Copyright © 2015 Elsevier B.V. All rights reserved. ispartof: Microelectronic Engineering vol:147 pages:108-112 ispartof: location:ITALY, Udine status: published

In this work, we discuss the characteristics of particular island-type features with an amorphous core that are developed during the low temperature epitaxial growth of Ge and GeSn layers by means of chemical vapor deposition with Ge2H6. Although further investigations are needed to unambiguously identify the origin of these features, we suggest that they are originated by the formation of clusters of H and/or contaminants atoms during growth. These would initially cause the formation of pits with crystalline rough facets over them, resulting in ring-shaped islands. Then, when an excess surface energy is overcome, an amorphous phase would nucleate inside the pits and fill them. Reducing the pressure and/or increasing the growth temperature can be effective ways to prevent the formation of these features, likely due to a reduction of the surface passivation from H and/or contaminant atoms.

The synthesis of nickel silicide thin films via a vapor–solid reaction has been studied by exposing thin (10 nm) Ni films to silane (SiH4). The crystalline phases, the Ni/Si stoichiometric ratios, as well as the surface and interface properties of the resulting silicide films were investigated as a function of the growth parameters such as the SiH4 partial pressure, the reaction temperature, and the exposure time. At low temperature (300 °C), SiH4 exposure led to the self-limiting deposition of Si on Ni by catalytic decomposition of SiH4 but not to silicate formation. Between 350 and 400 °C, phase pure orthorhombic NiSi films were obtained that were formed directly without any apparent intermediate Ni-rich silicide phases. A transformation to NiSi2 occurred at 450 °C and above, and at 500 °C phase pure NiSi2 was obtained. Here, the transient formation of NiSi was observed that transformed into NiSi2 for prolonged SiH4 exposure. The results indicate that the Si solubility governs the phase formation sequen...

In this work, we report on wet-chemical defect revealing in InP fin structures relevant for device manufacturing. Both HCl and HBr solutions were explored using bulk InP as a reference. A distinct difference in pit morphology was observed between the two acids, attributed to an anisotropy in step edge reactivity. The morphology of the etch pits in bulk InP suggests that the dislocations are oriented mainly perpendicular to the surface. By studying the influence of the acid concentration on the InP fin recess in nanoscale trenches, it was found that aqueous HCl solution was most suitable for revealing defects. Planar defects in InP fin structures grown by the aspect ratio trapping technique could be visualized as characteristic shallow grooves approximately one nanometer deep. It is challenging to reveal defects in wide-field InP fins. In these structures, dislocations also reach the surface next to stack faults or twinning planes. Due to the inclined nature, dislocation-related pits are only a few atomic layers deep. Extending the pits is limited by the high reactivity of the fin sides and the strong surface roughening during etching. The process window for revealing wet-chemical defects in InP fins is limited.

Within 3D stacked integrated circuits (3D-SIC), the fabrication of well-defined and solid microbumps is required. These bumps are typically being processed in presence of probing metal such as Al in order to stack functioning dies [1]. As a result of the variety of metals present and the continuous microbump downscaling towards 10 μm, more selective Cu seed etch chemistries are being screened. These Cu seed etch chemistries should be compatible with a variety of metals (Ni, Sn, Al, Co) and generate bumps without undercut and acceptable lateral etch (< 300 nm/side for 20 μm and < 150 nm/side for 10 μm). However the lateral etch specifications were just met for 20 μm [2] and will be more stringent for 10 μm, especially as the lateral etch specification are within the same range as the Cu seed layer thickness (150 nm). Additionally, the current seed etch process is yielding rough bumps (Rs >15 nm) whereas our target is set to be

Epitaxial growth requires a clean starting surface for the growth of a high-quality crystalline layer. For epitaxy on Si, an HF-last wet clean followed by an in-situ high-temperature hydrogen bake is the reference pre-epi clean sequence to obtain an oxygen-free surface [1, 2]. The temperature required to remove all residual oxygen also makes the surface atoms mobile, resulting in reflow. The high temperatures used during the H2-bake can also result in intolerable doping profile changes. A lower temperature pre-epi clean sequence is required to avoid this reflow, especially when moving away from Si. In addition the high temperatures needed during a H2-bake would result in the relaxation of high mobility channels, e.g. strained Si1-xGex or III-V materials [3]. Several low temperatures pre-epi cleaning solutions have been proposed in the past, e.g. GeH4-assisted H2-bake [4] or more recently, a GeH4-assisted HCl clean [5]. In this study we looked at the interaction between HF-last wet clean and the in-situ GeH4-assisted HCl clean prior to Si0.8Ge0.2-on-Si epitaxy.

Summary The early capture of process issues or drifts for all the operationsin a process module is important to avoid material scrapping. Investi-gating the quality of the incoming material (e.g. the FEOL module(s)in case of a via-middle TSV flow) as well as the outgoing material(for a typical 3D flow, numerous process steps follow in the thinningand stacking modules after the TSV module processing is completed,both of which can be severely impacted when, for instance, there is anon-uniformity in TSV depth present) is important for cost-effectiveprocessing. Aside from capturing issues that have occurred in a givenprocess step, it will be essential to have methods available for failureanalysis in order to find the root cause. 22 An overview of possiblemethods to investigate process results is given in Table I, including Table I. Overview of metrology. The list should not be interpreted as exhaustive. Technique / Reference Advantages / Remarks DisadvantagesFIB-SEM 20,24 ◦ Good resolution of defects → Capture‘voids’/defects in a metal matrix (e.g. platingdefects, post-anneal ‘void’)◦ Cross-sectioning by FIB time-consuming forTSV →Slow feedback and limited statistics◦ Destructive◦ Failure analysis: Cross-sectioning in awell-defined plane possibleX-ray transmission (XRT) 36,37 ◦ Non-destructive◦ Fast feedback◦ Many (statistics !) + specific structures in diecan be inspected◦ Some type of devices and layers (e.g. organic)may be sensitive to radiation◦ Resolution limited (e.g. plating defect in smallO TSV difficult to resolve)Mass measurement ◦ Fast feedback → Early capture of issues possible ◦ Only 1 data point per wafer◦ Sensitive for detecting full-wafer depositionand removal◦ No information on process step uniformity◦ In case of deviations, other metrology needed forfinding root causeOptical TSV depth measurement ◦ Non-destructive ◦ Small-diameter, high aspect ratio TSV structures◦ Many positions per wafer possible → Wafer-level difficult to accessuniformity of etch processScanning Acoustic Microscopy(SAM) 6,7,28,29◦ non-destructive ◦ Time consuming when inspecting many dies on a◦ Detection of plating ‘voids’ possible (depth scan) wafer (limited field of view)◦ Specific structures in die can be inspectedScanning Electron Microscopy (SEM) ◦ Measurement of CD-litho and CD-etch ◦ Time consuming when inspecting many dies on a◦ Specific structures in die can be inspected wafer (limited field of view)Atomic Force Microscopy (AFM) /Profilometry◦ non-destructive ◦ Indirect imaging of plating ‘voids’◦ Specific structures in die can be inspected

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

In this contribution, we discuss the crystalline properties of strained and strain-relaxed CVD-grown GeSn layers with Sn content in the range 6.4-12.6 at.%. A positive deviation from Vegard's law was observed and a new experimental bowing parameter was extracted for GeSn: bGeSn = 0.041 Å (in excellent agreement with recent theoretical predictions). The GeSn critical thickness for strain relaxation as a function of Sn concentration was determined, resulting in significantly higher values than those predicted by equilibrium models. A composition-dependent strain relaxation mechanism was also found, with the formation of an increasing density of GeSn pyramidal islands in addition to misfit dislocations at lower Sn concentration. © 2013 The Electrochemical Society. ispartof: ECS Journal of Solid State Science and Technology vol:2 issue:4 pages:P134-P137 status: published

Si(1 0 0) surface was physically eroded using 1 keV O 2 + ion beam and the resultant surface was studied by atomic force microscopy (AFM). The data were analyzed within the framework of dynamic scaling theory. Results indicate two growth regimes during the evolution of ripples on the surface. The first growth regime which is an unstable one continues for around 35 min and has an exponential growth exponent. The second growth regime on the other hand sets in after this time and exhibits a growth exponent of 0.38. However, for the entire bombarding period a single coarsening exponent (1/z = 0.44) extracted from the power spectral density peak widths of the acquired AFM images is observed. The ripple amplitudes however show an exponential increase over the time domain studied in agreement with the Bradley–Harper theory. Finally, roughness measurements clearly indicate transition regions of sputter yield variations and the onset of ripple formation.

The atomic layer deposition (ALD) of Ta2O5 and TaSiOx from TaCl5, SiCl4, and H2O is reported. Both processes are influenced by the concomitant etching of Ta2O5 and TaSiOx by TaCl5. The optimum deposition temperature is found to be 250 °C for both Ta2O5 and TaSiOx. For lower deposition temperatures, the large Cl contamination leads to poor dielectric properties of the films, whereas higher temperatures lead to poor within-wafer (WiW) thickness non-uniformity due to etching. Si incorporation is limited to Si/(Si + Ta) ∼ 0.65 because of the slow adsorption kinetics of SiCl4 on SiOH-terminated surfaces. Under optimum conditions, amorphous films with good dielectric quality are obtained.

In this work, the compatibility of InP and InGaAs in cleaning solutions commonly used in semiconductor manufacturing is investigated. Aqueous oxidizing cleans should be avoided as the substrates dissolve rapidly. Low pH solutions may impose some serious ES&H issues due to hydride evolution occurring upon acidic hydrolysis of the III-V material. However, acidic solutions are very efficient to remove the native oxide from the substrate. Complete oxide free surfaces are not achieved after wet cleaning due to the rapid oxidation of these materials in the atmosphere.

NiO thin films are deposited by atomic layer deposition (ALD) from the Ni(dmamb)2 (dmamb = 1-dimethylamino-2-methyl-2-butanolate) precursor using O3 as the oxidizer. The films are analyzed for wafer uniformity, structure, composition, morphology, microstructure, and homogeneity. The Ni(dmamb)2 half-cycle shows an initial rapid partial saturation followed by slower further adsorption. By contrast, the O3 half-cycle shows good saturation behavior. In the studied deposition temperature range for ALD, the films are polycrystalline with negligible amounts of carbon in the films. Furthermore, the films are homogeneous in thickness and composition, demonstrating that high-quality NiO films can be deposited by ALD from Ni(dmamb)2.

Growth of high (above 40%) Ge content SiGe by applying silane and dichlorosilane as Si precursors on (110) Si is investigated. In the case of silane based processes Ge concentration is ~ 20% higher, whereas for dichlorosilane based processes it is ~ 30% lower on (110) Si compared to (100) Si. The morphology of the grown layers is found to be dependent on Ge concentration, layer thickness and process temperature. Use of optimized deposition parameters and adequate thickness results in high quality strained SiGe layers. Integration of high Ge content SiGe layers in multiple gate filed-effect transistor structures shows the expected differences in Ge content on the different Si planes forming Si fin. These differences can be avoided by adjusting the fin orientation on the Si wafer resulting in equal planes on the fin's top and sidewalls. When the investigated SiGe layers are incorporated in the buried channel field effect transistor structures on (110) Si wafers a significant thickening at the active windows edge is observed. It is speculated that this effect is connected with elastic SiGe relaxation caused by a non optimized process temperature.

Three advanced architectures for ultimate progress in Ge p-Metal Oxide Semiconductor Field Effect Transistors are discussed in this paper. Different routes for stress implementations in Ge channels, either biaxial or uniaxial, are proposed by advanced selective Chemical Vapor Deposition techniques. Selective SiGe Strained Relaxed Buffer growth in Shallow Trench Isolation is first discussed to implement biaxial compressive strained Ge Quantum Wells on top of it. Next, innovative GeSn chemical vapor deposition technique is described in order to build either uniaxial strained Ge channel with GeSn Source/Drain stressors or compressively biaxial strained GeSn Quantum Well channels on Ge buffer layers.

Scaling air-gap interconnects to 70nm pitch is demonstrated for the first time by combining air-gap technology (SiO"2 etch-back and non-conformal CVD) and the double patterning approach. A capacitance reduction of 45% was measured on the air-gaps compared to the SiO"2 reference. The reliability performance of the air-gaps was then evaluated and it was found that the structures exceeded 10years lifetime at 2MV/cm, almost matching the performance of SiO"2 interconnects. Air-gaps could therefore make a promising low-RC solution for future technology nodes.

Downscaling of the metal-insulator-metal capacitor (MIMCAP) for Dynamic Random Access Memory (DRAM) requires the introduction of high permittivity dielectrics. MIMCAP structures formed with RuO"2/Ru as bottom electrode, rutile TiO"2 as dielectric and TiN as top electrode are described. Ozone (O"3) is needed as oxidant in the TiO"2 atomic layer deposition (ALD) process in order to obtain the rutile phase (permittivity>80), while anatase TiO"2 (permittivity ~40) is obtained with H"2O. As O"3 etches the ruthenium substrate, an ultra-thin interlayer of TiO"2 was first grown with H"2O, followed by the thick TiO"2 layer deposited with O"3. In order to minimize the content of anatase in the TiO"2 layer, responsible for a reduced dielectric constant, we investigate the effect of scaling down the thickness of the protective H"2O based inter-layer on the equivalent oxide thickness (EOT) and leakage current density (J"g). The four times reduction in thickness without affecting the integrity of the ruthenium substrate resulted in a significant decrease of both EOT and J"g.

The formation of nanostructures on SiGe surfaces by erosion using mixed beams of isobaric species (Cs/Xe) is shown to depend on the Cs/Xe ratio. The nanostructures exhibit different wavelengths (longer wavelengths for higher Cs concentrations) contrary to the present theoretical understanding. Moreover, experiments with pure Cs and Xe beams also demonstrate that such differences are enhanced at lower bombarding energies. Such effects are primarily due to the fact that the retentivity and mobility of cesium at the sample surface gets enhanced at lower bombarding energies. The phenomenon could be explained theoretically by including an additional diffusion term in the growth equation describing the mobility of the primary ions on the irradiated surface. Semi-empirical calculations done in this direction also confirm this phenomenon.

Thin LuxAl2−xO3 films were deposited by atomic-layer deposition using Lu(thd)3, and TMA in combination with O3 as oxidizer. High-quality dielectric films were obtained with good process con-trol. The full range of the Lu/(Lu+Al) composition was found to be accessible. The films showed bulk density and low roughness. As a result, this process enables the study of LuxAl2−xO3 as dielectric in advanced non-volatile memory devices.

The results of a wet alkaline seed deposition process directly on barrier layers or thin adhesion promoter films, such as CVD Co are presented. This solution has been successfully used for copper plating on blanket and patterned Though Silicon Via (TSVs) wafers covered with either silicon oxide/PVD Ta(N)/CVD Co or silicon oxide/PVD Ti/CVD Co stacks. Such direct plated films were used as seed layers for subsequent copper plating from a conventional sulfuric acid electroplating bath. The effect of the plated stack composition and thicknesses, processing waveform and applied current on the plating rate and morphology of the deposited copper has been investigated.

For future generations of non-volatile memory applications, the replacement of the interpoly dielectric by a suitable high-k material is required. Rare-earth aluminates are potential candidates because they are predicted to combine a high dielectric permittivity with a large band gap. We demonstrate the atomic layer deposition (ALD) of GdxAl2-xO3 layers using Gd( i PrCp)3, trimethyl-aluminum (TMA), and H2 Oo r O3. Process windows for both H2O and O3 as oxidants are explored. H2O is shown to lead to better GdxAl2-xO3 film properties than O3, although the accessible composition range is limited because of the hygroscopic nature of Gd2O3.

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 107 cm− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III–V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 °C, we measured an active dopant concentration of about 2.1 × 10 20 cm − 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1–4 × 10 13 cm − 2 ) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.