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We have demonstrated the execution of several programs stored in an instruction memory by a rapid single-flux-quantum bit-serial 8-bit microprocessor named CORE e2h. We employed a minimal instruction set architecture composed of 13 instructions based on the reduced instruction set computer. We integrated a 128-bit instruction memory and a 128-bit data memory with an arithmetic logic unit, two registers, a program counter, an instruction register, and a controller unit on a single chip. The bit-serial operation was performed by an on-chip clock generator, while the system clocks are provided from room-temperature electronics. The CORE e2h was made up of 11 000 Nb/AlOx/Nb Josephson junctions and fabricated with the Advanced Industrial Science and Technology 10-kA/cm2, 9-Nb-layer process. We obtained the correct results for all the executed programs, including the integer division, the two kinds of summation algorithms, the Euclidean algorithm, and finding the greatest divisor. These test programs contained a single or nested double loop, and the maximum number of executed instructions was 205. We confirmed the stable operation with the DC bias margins of around 10% at 50-GHz for different test programs. The measured electric power consumption was 2.5 mW at 4.2 K, and the estimated computing power was 500 × 106 instructions/s.

We adopt superconductor/ferromagnet/insulator/superconductor (SFIS) Josephson junctions (JJs) as both switching JJs and intrinsic π phase shifters in superconductor digital circuits. The critical current density (Jc) and characteristic voltage (Vc) of the SFIS junctions are about 22 A/cm2 and 22 μV, respectively. The intrinsic π phase shift is confirmed by measuring the suppressed nominal critical current Icn and half-period-shifted modulation pattern of a π–π–π superconducting quantum interference device (SQUID) that contains three π-JJs in a superconducting loop. A single-flux-quantum (SFQ) circuit composed of a DC/SFQ, Josephson transmission line (JTL), and SFQ/DC converter based on SFIS JJs alone is demonstrated at 4.2 K. The energy dissipation of the SFQ/DC converter decreases by 80% because some JJs are self-biased by the π phase shifter. The intrinsic circulating currents induced by the π phase shifters lead to a narrow bias margin (±5%) and even error function, which can be solved by parameters optimization or circuit initialization in the future. The half-modulation period (Φ0/2) of a half-flux-quantum (HFQ) SQUID (a partial HFQ JTL) exhibits propagation of HFQ between π–π–π SQUIDs, indicating that more complex HFQ circuits can be developed with π-JJs alone in the future.

A high-throughput 4 $\boldsymbol{\times }$ 4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm $\boldsymbol{^2}$ , Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134 $\boldsymbol{\mu }$ W, respectively. Although the switching speed of the Josephson junctions was reduced by 40 $\boldsymbol{\%}$ owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.

We propose a new cryogenic high-speed and low-power matrix memory required for achieving a high-performance superconductor computing system. The memory cell is based on the 0-π SQUID with conventional Josephson junctions (0-junctions) and a π-shifted ferromagnetic Josephson junction (π-junction). The memory state is stored in the form of two stable states in the 0-π SQUID. The π shift feature of the π-junction eliminates the need for any bias current or magnetic field for the formation of two states, i.e., the memory is non-volatile. In this memory, an impulse-shaped voltage signal generated in single-flux-quantum (SFQ) circuits is used for the write and read operations of the memory state. By using the pulses propagating in passive transmission lines, high-speed and low-power operation can be achieved because a recharging process determining the operation speed and the dominant energy consumption can be eliminated. We fabricated the 0-π SQUID-based pulse-driven memory cells with an SFQ driver. From the static characteristics, we confirmed that the current needed for rewriting can be sufficiently reduced. In addition, we successfully demonstrated the correct write operation in the memory cell by the SFQ pulse train transmitted from the SFQ driver via the passive transmission line.

We demonstrated interface circuits between a half-flux-quantum (HFQ) circuit and a rapid single-flux-quantum (RSFQ) circuit to obtain SFQ/HFQ and HFQ/SFQ converters. These converters were created by simply inserting a resistor between an RSFQ circuit and the adjacent HFQ circuit, where both circuits are based on pulse logic. These converters enable us to create combinatory circuits that make the best use of the features of the two circuits. Using a DC/SFQ, SFQ/HFQ, HFQ/SFQ, and SFQ/DC converter, we measure an HFQ Josephson transmission line (JTL) composed of eight 0-0-π superconducting quantum interference devices (SQUIDs), which are the essential elements of an HFQ circuit. The 0-0-π SQUIDs are composed of two conventional Josephson junctions and a π-shifted ferromagnetic junction. The HFQ JTL demonstrated in this study is driven by a bias current 11-fold lower than that of a similar RSFQ JTL. These experimental results indicate that the HFQ circuit requires power that is two or more orders of magnitude lower than that of an RSFQ circuit.

In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents ( $I_{\mathrm{c}}$ values) of the Josephson junctions (JJs), or the bias voltage ( $V_{\mathrm{b}}$ ). The shifts and spreads of timing parameter fluctuations when $I_{\mathrm{c}}$ and $V_{\mathrm{b}}$ were lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after $I_{\mathrm{c}}$ was lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered $V_{\mathrm{b}}$ values were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered $I_{\mathrm{c}}$ or $V_{\mathrm{b}}$ to 6.25% of their conventional values, and the energy reduction after lowering of $V_{\mathrm{b}}$ was 26% better than that after lowering of $I_{\mathrm{c}}$ . Moreover, if a small error rate (for example $10^{-6}$ ) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.

We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic logic unit and register files for high-throughput oriented SFQ microprocessors based on a gate-level-pipeline structure. Achieving high-speed operation in the bit-parallel datapath is difficult because of feedback paths. We used concurrent-flow clocking and counter-flow clocking in combination to solve the timing problem at the feedback path in the datapath, and we optimized the number of JJs and pipeline stages in the register file for solving the timing issue. We designed the datapath with the cell library for the AIST 10 kA/cm $^2$ Advanced Process. The total number of pipeline stages, Josephson junctions, and circuit area of the designed datapath were 52, 18448, and 3.81 mm × 4.05 mm, respectively. We obtained a relatively wide bias margin of the designed datapath at the target clock frequency of 50 GHz, and it operated up to 64 GHz in on-chip high-speed testing.

With the advances in superconductor detectors and single flux quantum (SFQ) logic circuits, megapixel imagers have become possible. Various detectors such as superconducting stripline detectors (SSLD), kinetic inductance detectors, nanowire single-photon detectors have quite matured in terms of speed and performance. However, scaling of the read-out electronics is still a challenge. We propose an SFQ based synchronous address encoder to read-out the response of an SSLD array. The encoder circuit provides two sets of outputs at each clock period: one is the time-division multiplexed, serial data output, and the other is the synchronized address output associated with the time-multiplexed data. Thus, the number of connections to the room temperature is substantially reduced. We experimentally demonstrate a 2-bit encoder. Then, we present the scalability of the circuit to larger arrays and show the simulation results of a 4-bit encoder, which is suitable to read-out a 16 x 16 detector array.

In the field of superconducting electronics, a π phase shifter based on a ferromagnetic Josephson junction is expected to provide various advantages to classical and quantum superconducting devices. Here we report niobium nitride (NbN)-based ferromagnetic π junctions on a silicon (Si) substrate with a titanium nitride (TiN) buffer layer, which have applications to flux-bias-free flux quantum bits (qubits) and classical digital logic elements. We fabricated and characterized NbN/aluminum nitride (AlN)/NbN Josephson junctions, NbN/copper nickel (CuNi)/NbN ferromagnetic Josephson junctions, and superconducting quantum interference devices (SQUIDs) consisting of these junctions on the Si substrate. The fabricated NbN/AlN/NbN junctions showed a high junction quality suitable for qubit applications. Furthermore, the magnetic field dependence of the SQUID’s critical current indicated that the NbN/CuNi/NbN junction worked as a π phase shifter on the Si substrate.

We directly observed π-leaps of superconducting phase differences in π-junction-based superconducting quantum interference devices (SQUIDs). The SQUIDs studied here are formed by introducing a π-junction to a conventional-junction (0-junction)-based direct current (DC)-SQUID, which is referred to as the 0-0-π SQUID. Either clockwise or counter-clockwise-circulating currents flow spontaneously in the 0-0-π SQUID because of a π-phase shift of the π-junction. In other words, the 0-0-π SQUID has a bistable state corresponding to the directions of circulating currents. π-leaps are generated by transiting between the two states of the bistable state. π-leaps are an ultra-fast phenomenon and are difficult to observe as they are. We prepared a half-flux quantum (HFQ)-SQUID that comprised two 0-0-π SQUIDs. π-leaps are reflected in a static characteristic, that is, a modulation pattern of the critical current in the HFQ-SQUID. We formed π-junctions with the PdNi layer on 0-junction-based circuits supplied by the National Institute of Advanced Industrial Science and Technology. The modulation pattern of the HFQ-SQUID had a period corresponding to π-leaps as expected, although some microstructures were observed. We demonstrated that the microstructures originated from the asymmetry inside each 0-0-π SQUID by analyzing the relationship between the phase change of 0-0-π SQUIDs and the modulation patterns.

We fabricated NbTiN Josephson junctions (JJs) with HfO x barriers on thermally oxidized Si substrates. Hf overlayers with different resistivities were used for the HfO x barrier formation. The Hf overlayer with low resistivity produced junctions with high quality parameters. The critical current density (J c ) was obtained in the range of 0.01-0.4 kA/cm 2 by changing the thermal oxidation conditions of the Hf layer. The critical current uniformity was estimated at a maximum-to-minimum spread of ±10.1% for 85 of the 100 JJs. We evaluated the specific capacitance, which was approximately 110 fF/μm 2 for the J c ranging from 0.1 to 0.4 kA/cm 2 . The quasiparticle tunnel characteristics were improved by using the NbN electrodes instead of the NbTiN electrodes.

We report demonstration of a readout circuit with high-throughput single flux quantum (SFQ) based encoders for a large-scale video imaging system with a conventional frame rate. The encoders are fully parallel and integrated on the same chip as linear arrays of serially connected superconductor stripline detectors (SSLDs), superconducting quantum interference device (SQUID) based comparators, and SFQ synchronizers. Mutual coupling of parallel SSLDs and SQUID-based comparators allows the use of only one dc bias line; it is possible to use thousands of SSLDs without increasing the bias current or number of bias ports. To achieve crosstalk-free readout, the serially connected SSLDs are separated by low-pass filters or large inductors. We experimentally demonstrated crosstalk-free readout including SFQ parallel encoders from 1-D or 2-D serially connected SSLD arrays.

Purpose The lack of reliable and scalable superconducting random access memory (RAM) cells is the main obstacle for full implementation of superconducting rapid single flux quantum(RSFQ) computers. This work points the methodology and the structures that shall be used in future implementation of RSFQ RAM. Design/methodology/approach A new design for RAM using two ferromagnetic strips in proximity to the superconductor in a RSFQ computer is presented (1). The concept of using a RAM RSFQ cell as a tuneable superconducting qubit is also explored. Findings Two basic architectures for superconducting RAM cells were developed with integration schemes in two dimensions. Research limitations/implications The proposed RAM cells as depicted in Figures 7 and 16 offer smaller size and greater 3 scalability in comparison to other suggested schemes (4), (3), (2), (5). Practical implications Currently, the main obstacle in implementation of RSQF computer is lack of reliable RAM cell. RSQF computer shall have potential to take a large fraction of classical supercomputers, as it consumes much less power. Social implications Computation power shall be cheaper when one uses RSQF computers for big data and computational centres. It is a matter of some time. Originality/value The publication presents the new design of superconducting RAM cell for use in RSQF computer. The numerical relaxation method is used to solve biharmonic Ginzburg–Landau equation. The analytic approach as a solution of a specified problem is given.