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Silicon Carbide (SiC) power MOSFETs are known to degrade and eventually fail under repetitive short circuit (SC) stress. In this paper, a new approach, named BaSIC(DMM), is demonstrated to prevent the degradation and failure of 1.2 kV SiC power MOSFETs under repetitive SC stress. The new concept utilizes a low-voltage, gate-source-shorted Si depletion mode MOSFET connected to the source of the SiC MOSFET. It was experimentally verified that no degradation or failure of the SiC power MOSFET occurs after over 3000 SC events with the BaSIC(DMM) topology while the SiC power MOSFETs degraded and failed after 200 SC events without it.

The BaSIC(EMM) topology has been previously demonstrated to improve the short-circuit (SC) capability of 1.2-kV SiC power MOSFET s from 3.5 to 7.4 μs while producing a 17% increase in the net on -state resistance. However, a SC time of 10 μs could not be achieved. In this article, a systematic procedure for selection of the Si power MOSFET used in the BaSIC(EMM) topology is described based on information published by manufacturers of Si power MOSFET s in their datasheets. A tradeoff curve between the Si EMM drain saturation current at 150 °C versus its on -resistance at 25 °C is proposed in this article for determination of the best Si EMM product. The proposed methodology allowed identification of a superior Si EMM device. It was experimentally validated that a SC with-stand time of 11 μs, under a gate bias of 20 V applied to the 1.2-kV SiC power MOSFET at a drain bias of 800 V, was achievable with an increase in on -resistance of only 3.6%. These experimental results demonstrate a greatly improved tradeoff curve between SC time and increase in on -resistance.

Advanced SiC planar-gate power MOSFET s have been successfully manufactured in a 6-inch commercial foundry with device structures optimized for operation with gate drive voltage of 10 V, compatible with gated drive voltage for Si superjunction products. The electrical characteristics of three advanced SiC MOSFET options are described in this article and compared with those of a state-of-the art Si superjunction MOSFET . The new advanced SiC power MOSFET s are demonstrated to exhibit superior on -state and switching losses with significantly better body-diode reverse recovery performance. Their short-circuit withstand time is also found to be significantly longer than typical commercially available planar-gate SiC power MOSFET s. These improved characteristics make the advanced SiC power MOSFET s suitable replacements for Si superjunction transistors to enhance high frequency circuit performance.

Silicon carbide (SiC) power MOSFETs have been commercialized to replace silicon insulated gate bipolar transistors (IGBTs) in power conversion applications. However, the short-circuit ruggedness of SiC power MOSFETs must be enhanced to match that of Si IGBTs for application in motor drives for electric vehicles. A new, user-configurable method with a series-connected, Si enhancement mode MOSFET (EMM) is demonstrated to improve the short-circuit withstand time of commercially available 1.2-kV SiC power MOSFETs by 86% with a 4.2% increase in on- resistance and a 13% increase in switching loss. In contrast, operating the 1.2-kV SiC power MOSFET with a reduced gate bias of 15 V produces an 80% improvement in short-circuit withstand time with 31% increase in on- resistance and a 31% increase in switching loss. It is demonstrated that the drain of the EMM can be used as a sensing node to monitor on- state current and to detect short-circuit events.

The BaSIC(DMM) topology has been experimentally demonstrated to improve the short-circuit time for a 1.2 kV SiC power MOSFET product from $4.8~\mu \text{s}$ to $7.9~\mu \text{s}$ with a 17% increase in on-state resistance by utilizing a commercially available 100 V rated Gate-Source-Shorted (GSS) Si Depletion-Mode power MOSFET (DMM). The optimization of the Si GSS-DMM is discussed in this paper to achieve even superior performance, namely larger short-circuit time with less increase in on-resistance. It is theoretically demonstrated for the first time that a highly desirable short-circuit time of $10~\mu \text{s}$ , similar to Si IGBTs, can be achieved for two SiC power MOSFET products with less than 3% increase in on-resistance. This was accomplished by reducing the breakdown voltage rating of the Si GSS-DMM from 100 V to 30 V, altering the cell design parameters, and utilizing the trench-gate design. The theoretical analysis provided in this paper provides valuable design guidelines for manufacturers of Si GSS-DMM devices to achieve optimum performance for use in the BaSIC(DMM) topology.

Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. The BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.

This paper compares the static and dynamic performance of 1.2 kV 4H-SiC ACCUFETs and INVFETs with identical channel length (0.5 μm) and gate oxide thickness (55 nm). It is demonstrated for the first time that ACCUFETs have lower total switching losses in comparison to the INVFETs. ACCUFETs are therefore superior devices for applications due to their lower specific on-resistance and overall switching losses. However, short circuit tests conducted on the devices show that ACCUFETs have a smaller short-circuit time (tSC) in comparison the INVFETs due to their higher short-circuit current.

The electrical characteristics of the 1.2-kV rated 4H-SiC accumulation-channel split-gate octagonal cell MOSFET (SG-OCTFET) are experimentally compared with linear, square, hexagonal, octagonal, and compact-octagonal cell topologies. The specific on-resistance of the SG-OCTFET is 52% larger than the conventional linear cell topology. However, the SG-OCTFET has: (i) high-frequency figure-of-merit HFFOM[Ron×Cgd] 9.4×, 6.1×, 2.6×, 2.0×, and 1.8× superior to the square, hex, linear, octagonal, and compact-octagonal cells; (ii) fastest switching performance among all cell topologies, with 26% smaller switching energy loss than the conventional linear cell topology; and (iii) short circuit capability 1.5× longer than the conventional linear cell topology. The SG-OCTFET device is therefore an optimum candidate for high frequency applications of SiC MOSFETs.

Short-circuit (SC) capability is a critical requirement for power switches in modern power electronics applications. A tradeoff between on-state voltage drop, switching loss, and SC capability of insulated gate bipolar transistors (IGBTs) is performed by manufacturers. In general, IGBTs optimized with low on-state voltage have poor SC capability compared with those with good SC capability. In this report, a novel method is described to improve the SC capability of IGBTs optimized with low on-state voltage drop by using a gate-source-shorted Si depletion-mode (DM) mosfet connected in series with the emitter. A seven-fold increase in the SC capability of commercially available 1.2-kV IGBTs was achieved at high dc bus voltages with minimal impact on on-state and switching loss performance. The proposed method also provides a sensing voltage signal at the drain of the Si DM- mosfet , which can be used to monitor the on-state current magnitude and to detect SC fault conditions.

Grid interface power conversion systems for commercial, industrial and residential solar power generation are becoming ubiquitous due to the competitive cost of solar energy. The AC/DC dual active bridge (DAB) converter is an upcoming topology in industrial PV energy and energy storage applications, providing bidirectional power transfer and galvanic isolation. In this paper, the properties of a DAB-type converter are leveraged to propose a design optimization process. It can optimize the high-frequency RMS current, size of magnetic elements and zero-voltage-switching (ZVS) region of the converter. The resulting design is compared against that derived from a conventional approach. In addition, an algorithm to compute the harmonic currents at the DC and line frequency AC ports of the system is proposed, and the respective filter designs are presented. The optimized design of the AC/DC DAB converter is implemented using the newly developed, 1200 V, $46 \mathrm{m}\Omega$, four quadrant, SiC-based monolithic bidirectional FETs (BiDFET). Experimental results from the 2.3 kW, $400\mathrm{V}/277\mathrm{V}_{{\mathrm {RMS}}}$ hardware prototype are finally presented to verify the design process.

The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.

SiC power MOSFETs have poor short-circuit (SC) withstand capability compared to Si IGBTs. A new method, called BaSIC, with a low voltage silicon MOSFET in series with the source of the SiC power MOSFET, has been recently demonstrated for improvement of the SC capability with minimal impact on normal circuit operation. In this paper, the two BaSIC implementations using either a depletion-mode MOSFET (DMM) or an enhancement-mode MOSFET (EMM) are compared for the first time. The user-configurable BaSIC(EMM) topology was found to result in a superior overall performance. A 1.86x improvement in SC capability was achieved with the BaSIC(EMM) topology with 4% increase in on-resistance and 13 % increase in switching loss versus the BaSIC(DMM) topology which achieved a 2.4x improvement in SC capability with a 19% increase in on-resistance and a 40% increase in switching loss. The BaSIC(DMM) topology offers simplicity of implementation, while the BaSIC(EMM) topology offers a unique user-programmable capability for power electronics engineers.

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.

Commercial IGBTs optimized with low on-state voltage drop (V CE,SAT ) have poor short circuit ruggedness (t SC ). This paper demonstrates a new concept to enhance t SC for commercially available 1.7 kV IGBTs designed with low V CE,SAT using a gate-source-shorted (GSS) Si depletion-mode (DM) MOSFET in series. A five-fold improvement in t SC to over 25 μs was achieved at a DC bus voltage of 1100 V with only 15% increase in V CE,SAT and no change in total switching loss. The new concept also provides a sense voltage to monitor collector current during normal circuit operation and to detect SC events.

Gallium Nitride FETs have poor short-circuit withstand capability at high DC bus voltages with on-state gate drive voltage. In this paper, the BaSIC(DMM) topology that employs a low voltage Si depletion-mode MOSFET (DMM) in series with source of the GaN FET is demonstrated to suppress the peak short-circuit current and extend the SC withstand time. Experimental results are provided for commercially available 600 V Cascode GaN FETs. The SC withstand time was increased from 0.33 $\mu$ s to 4.35 $\mu$ s at a drain bias of 400 V with gate bias of 8 V, an improvement by a factor of 13x. Under normal power circuit operating conditions, the BaSIC(DMM) topology produces a 29 % increase in on-resistance and almost no change in switching losses.

In this paper, the switching and short-circuit performance of 650 V (BV=850V) 4H-SiC planar-gate MOSFETs with a gate oxide thickness of 27 nm are reported for the first time. The switching and short-circuit withstand times (t SC ) of devices with gate oxide thickness of 55 nm and 27 nm have been compared at various gate voltages. The R on,sp for the 27 nm device at V gs = 15 V is 1.7x smaller than that for the conventional 55 nm device at V gs =20 V while their total switching energy loss (E total ) is the same. The t SC for the 27 nm device at V gs = 10 V is 1.5x better than the 55 nm device at V gs =20 V. It is demonstrated for the first time that a much better trade-off can be obtained between shortcircuit capability and the specific on-resistance (R on,sp ) by reducing the gate oxide thickness from 55 to 27 nm.

In this paper, we report successful fabrication of the first large area, monolithic, 1.2 kV 4H-SiC Bi-Directional FETs (BiDFETs) with integrated JBS diodes in a 6-inch commercial foundry for use in matrix converters. The fabricated BiDFETs support high voltage (>1.2 kV) in the first and third quadrants. They exhibit very low on-resistance of 50 mΩ in the on-state in both quadrants when the 20 V gate bias is applied to both gates, allowing conduction of 20 A with 1 V drop. Fully gate voltage controlled output characteristics are also confirmed in both quadrants.

A novel 1.2 kV/10A, 4H-SiC monolithic, bidirectional switch has been developed for use in cycloconverter applications to facilitate high-frequency direct AC-to-AC power conversion and enables new power converter topologies. A new packaging solution, utilizing a 100 μm flexible polyimide organic laminate substrate is developed to mitigate thermo-mechanical stress during power cycling and enable smaller form factor and lower cost. Multiphysics simulations and static tests were conducted to show performance characterization of the module and compare it against metallic substrates. A new organic laminate epoxy resin composite dielectric (ERCD) is also evaluated for superior thermal performance and shows 63% reduction in junction to case resistance compared to DBC substrates

In this paper, we report successful fabrication of 1200 V 4H-SiC planar-gate inversion-channel power MOSFETs with 27 nm gate oxide thickness in a 6 inch commercial foundry. The static electrical characteristics, switching performance and short-circuit failure times for the 27 nm devices are compared with those of conventional 55 nm gate oxide devices. The specific on-state resistance of the 27 nm gate oxide devices at a gate voltage of 15 V was found to be 1.5x lower than the conventional 55 nm gate oxide devices at a gate bias of 20 V. The total switching energy loss (E tot ) for the 27 nm device with V gs of 15 V and V gs of 10 is approximately equal and 1.4x larger than the 55 nm case with V gs of 20 V. The short-circuit failure time (t sc ) for the 27 nm device is 1.4× better than 55 nm device at V gs of 10 V but 1.4× worse for V gs of 15 V.

The impact of channel length on the static, dynamic, and short-circuit performance of 1.2 kV-rated 4H-SiC inversion-channel (Inv) power MOSFETs is reported for the first time. Devices were successfully fabricated with the various channel lengths (L CH =0.3 to 1.1 $\mu$ m) in a 6 inch commercial foundry and they were packaged in TO-247 cases for all the testing. The devices with 0.3 $\mu$ m channel length were found to have the lowest on-resistance, best High Frequency Figures-of-Merit (HF-FOMs), and fastest switching performance, but worst short-circuit (SC) capability. The SC capability improved with increasing channel length at the penalty of an increase in the on-resistance. The fabricated 1.2 kV SiC MOSFETs were compared with commercially available 1.2 kV Si IGBTs in terms of the power losses and short-circuit capability: the 1.2 kV SiC power MOSFETs with long channel length can outperform the Si IGBT with lower power losses and superior short-circuit capability.

Silicon Carbide power MOSFETs are being adopted to replace Si IGBTs in power conversion applications. However, when compared to Si IGBTs, commercial SiC power MOSFETs have inferior short-circuit (SC) capability, which is an impediment to motor drive applications. SC ruggedness for SiC power MOSFETs can be improved by using a series resistance to reduce SC currents, but this adversely affects on-state and switching performance. This paper presents a new method, using a series-connected, gate-source-shorted (GSS) Si depletion-mode (DM) MOSFET, to enhance the SC capability of SiC power MOSFETs. The impact of the new method on normal circuit operation is compared to that using a series resistance for the first time in this paper. The SC capability of a 1.2 kV SiC power MOSFET is shown to improve from 4.8μs to 7.9μs using the new concept with only 17% increase in on-resistance and 11% increase in switching loss, whereas using a series resistance produces a similar SC performance improvement with 62% increase in on-resistance and 42% increase in switching loss. The new method also provides a voltage sensing node at the drain of the GSS Si DM MOSFET, which can be used to monitor the on-state current level and to detect SC events.

Silicon carbide power MOSFETs are under development to replace silicon IGBTs for high-efficiency power conversion applications. Commercial SiC power MOSFETs have a short-circuit (SC) capability inferior to those of Si IGBTs, thus constraining their widespread use. Gate drive voltage levels for SiC power MOSFETs can be reduced to increase SC capability but this results in a large increase in on-resistance. This paper presents a new method, with a series-connected Gate-Source-Shorted (GSS) Si Depletion-Mode (DM) MOSFET, to enhance the short-circuit capability of SiC power MOSFETs and compares its performance with the gate drive level adjustment approach for the first time. The SC capability of a 1.2kV SiC power MOSFET operating at 800V with a gate bias of 20V is demonstrated to improve from $4.8\boldsymbol{\mu} \mathbf{s}$ to beyond $7.5\boldsymbol{\mu} \mathbf{s}$ with only 17% increase in on-resistance using the new approach, whereas the gate drive level adjustment method produces a similar improvement in SC capability with a 66% increase in on-resistance. Measured static and dynamic characteristics demonstrate less than 20% increase in switching power loss using the new method. The new method also provides a voltage sensing node at the drain of the GSS Si DM MOSFET for detection of SC events, which is not available in the case of the conventional single SiC MOSFET.

Silicon carbide power MOSFETs are an attractive option to replace Si IGBTs in power conversion applications to reduce switching losses. Commercially available SiC Power MOSFETs do not have short-circuit (SC) capability matching those of Si IGBTs, thus prohibiting their use in some applications. This paper proposes an innovative method to improve the short circuit capability of 1.2 kV SiC power MOSFETs by using a gate-source shorted Si power depletion-mode MOSFET in series with the source electrode. Extension of the short circuit time from 4.8 μs to beyond 7.5 μs for a 1.2 kV SiC power MOSFET operating at a drain bias of 800 V and gate bias of 20 V has been experimentally demonstrated. Static and dynamic characteristics were measured to demonstrate minimal impact on power losses.

Improved SiC-MOSFETs with high HF-FOMs are enabling unprecedented high frequency MHz-switching. However, other SiC-MOSFET parameters, such as input capacitance and total gate resistance dictate the "theoretical limit" on the maximum switching frequency, and are often not considered. These latter parameters directly influence the "real-time" dynamic on-resistance when the propagation-time of gate voltage approaches that of the switching time period. To properly characterize MHz-switching performance, minimum switching times are calculated using a modified "input RC time constant" analysis that incorporates a time-dependent active area. An empirical comparison is conducted for several SiC-MOSFETs. A novel, equivalent RC ladder and resistor switch network model is proposed to describe the propagation of gate voltage and dynamic activation of unit-cells composing the SiC-MOSFET channel. A time-dependent effective on-resistance, accounting for transition and steady state conduction on-times, is determined and verified in both simulation and experiment. New high-frequency performance metrics for SiC-MOSFETs are proposed to provide greater insight for design engineers, and provide maximum expected operating limits. This will also help guide semiconductor designers to better match device to application.

The short circuit (SC-SOA) capability of power devices is crucial for power systems. In this paper, 1.2 kV SiC MOSFETs and JBSFETs are characterized, and their SC-SOA behavior was tested and analyzed. Due to the lower saturated drain current, the JBSFETs were found to have superior SC-SOA compared with MOSFETs despite the integrated Schottky contact. A new short circuit failure mechanism related to melting of the top Al metallization is proposed based up on non-isothermal TCAD numerical simulations supported with SEM measurements of failed die using Energy Dispersive X-ray Spectroscopy (EDS) analysis.