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Electroencephalography (EEG) is one of the most signals used for studying and demonstrating the electrical activity of the brain due to the absence of side effects, its noninvasive nature and its well temporal resolution. Indeed, it provides real-time information, so it can be easily suitable for predicting drivers’ vigilance states. The classification of these states through this signal requires sophisticated approaches in order to achieve the best prediction performance. Furthermore, deep learning (DL) approaches have shown a good performance in learning the high-level features of the EEG signal and in resolving classification issues. In this paper, we will predict individuals’ states of vigilance based on the study of their brain activity by analyzing EEG signals using DL architectures. In fact, we propose two types of networks: (i) a 1D-UNet model, which is composed only of deep one-dimensional convolutional neural network (1D-CNN) layers and (ii) 1D-UNet-long short-term memory (1D-UNet-LSTM) that combines the proposed 1D-UNet architecture with the LSTM recurrent model. The experimental results reveal that the suggested models can stabilize the training model, well recognize the subject vigilance states and compete with the state of art on multiple performance metrics. The per-class average of precision and recall can be, respectively, up to 86% with 1D-UNet and 85% with 1D-UNet-LSTM, hence the effectiveness of the proposed methods. In order to complete our virtual prototyping and to get a real evaluation of our alert equipment, these proposed DL models are implemented also on a Raspberry Pi3 device allowing measuring the execution time necessary for predicting the state vigilance in real time.

International audience; Epilepsy is one of the most widespread neurological pathologies, which is characterized by localized or generalized brain dysfunction due to abnormal or excessive paroxysmal electrical discharges. These discharges lead to neuronal hyperactivities causing prolonged and involuntary muscle contractions or periods of loss or altered consciousness. A patient's quality of life could be greatly improved with an effective alarm system able to predict future crises. Our article presents a fully specified model for automated seizure prediction based on autoregressive multivariate modeling and stability state analysis from clinical and simulated electroencephalography (EEG) data. Our model allows the calculation of a stability index whose analysis in content makes it possible to predict crises. The approach is validated on 29 crises recorded for 8 patients from a database available in free access and 14 simulated subjects also called virtual patients generated by neuro-computer platform TVB (The Virtual Brain:www.thevirtualbrain.org) using Epileptor as mass neural model for gray matter and “john Doe” matrix as white matter. Our preliminary results exhibit a detection accuracy of 97.87 %, a sensitivity of 100 % and an average prediction time for the eight real patients of 237.21 s and a detection accuracy of 100 %, a sensitivity of 93 % and an average prediction time of 4.427 s for the simulated subjects.

Deep learning, the fastest growing segment of Artificial Neural Network (ANN), has led to the emergence of many machine learning applications and their implementation across multiple platforms such as CPUs, GPUs and reconfigurable hardware (Field-Programmable Gate Arrays or FPGAs). However, inspired by the structure and function of ANNs, large-scale deep learning topologies require a considerable amount of parallel processing, memory resources, high throughput and significant processing power. Consequently, in the context of real time hardware systems, it is crucial to find the right trade-off between performance, energy efficiency, fast development, and cost. Although limited in size and resources, several approaches have showed that FPGAs provide a good starting point for the development of future deep learning implementation architectures. Through this paper, we briefly review recent work related to the implementation of deep learning algorithms in FPGAs. We will analyze and compare the design requirements and features of existing topologies to finally propose development strategies and implementation architectures for better use of FPGA-based deep learning topologies. In this context, we will examine the frameworks used in these studies, which will allow testing a lot of topologies to finally arrive at the best implementation alternatives in terms of performance and energy efficiency.

In this article, we propose to design a new modular architecture for a self-organizing map (SOM) neural network. The proposed approach, called systolic-SOM (SSOM), is based on the use of a generic model inspired by a systolic movement. This model is formed by two levels of nested parallelism of neurons and connections. Thus, this solution provides a distributed set of independent computations between the processing units called neuroprocessors (NPs) which define the SSOM architecture. The NP modules have an innovative architecture compared to those proposed in the literature. Indeed, each NP performs three different tasks without requiring additional external modules. To validate our approach, we evaluate the performance of several SOM network architectures after their integration on an FPGA support. This architecture has achieved a performance almost twice as fast as that obtained in the recent literature.

X-ray Coronary angiograms are intended to specify the global state of the artery system and therefore to detect and locate the zones of narrowing. Accurate coronary artery segmentation is a fundamental step in computer aided diagnosis of many diseases. In this paper, deep neural network based on U-Net architecture is proposed in order to improve the segmentation task for coronary images. In this context, various enhancement methods, like the adaptive histogram equalization and the multiscale technique with a Frangi filter are tested not only in normal conditions but also in the presence of noise to improve the system performance and to ensure its robustness against real conditions. Promising result are obtained and discussed for different performance criteria. This work will serve as a reference and motivation for researchers interested in the field of blood vessel segmentation by deep learning neural networks.

The development of hardware platforms for artificial neural networks (ANN) has been hindered by the high consumption of power and hardware resources. In this paper, we present a methodology for ANN-optimized implementation, of a learning vector quantization (LVQ) type on a field-programmable gate array (FPGA) device. The aim was to provide an intelligent embedded system for real-time vigilance state classification of a subject from an analysis of the electroencephalogram signal. The present approach consists in applying the extension of the algorithm architecture adequacy (AAA) methodology with the arithmetic accuracy constraint, allowing the LVQ-optimized implementation on the FPGA. This extension improves the optimization phase of the AAA methodology by taking into account the operations wordlength required by applying and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. This LVQ implementation will allow a considerable gain of circuit resources, power and maximum frequency while respecting the time and accuracy constraints. To validate our approach, the LVQ implementation has been tried for several network topologies on two Virtex devices. The accuracy–success rate relation has been studied and reported.

The Multiple-Wordlength Operation Grouping (MWOG) is a recently used approach for an optimized implementation on a Field Programmable Gate Array (FPGA). By fixing the precision constraint, this approach allows minimizing the data wordlength. In this paper, the authors present the integration of the approach based on the MWOG in the Algorithm Architecture Adequation (AAA) methodology, designed to implement real-time applications onto reconfigurable circuits. This new AAA-MWOG methodology will improve the optimization phase of the AAA methodology by taking into account the data wordlength and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. The AAA-MWOG methodology will allow a considerable gain of circuit resources. This contribution is demonstrated by implementing the Learning Vector Quantization (LVQ) neural-networks model on the FPGA. The LVQ optimization is used to quantify vigilance states starting from processing the electroencephalographic signal. The precision-gain relation has been studied and reported.

In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [Formula: see text] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.

This paper presents an optimizing methodology for implementing a multi-layer perceptron (MLP) neural network in a Field Programmable Gate Array (FPGA) device. In order to obtain an efficient implementation, a compromise of time and area is needed. Starting from simulation in the learning phase with fixed point operators, we have developed a methodology which allows the automatic generation of a VHDL code within a multi-width encoding of an MLP. The proposed methodology should determine the optimal encoding of various blocks of our Artificial Neural Networks (ANN) to optimize accuracy and minimize the application area. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized MLP implementation has been tried on Virtex devices.