The application of group IV nanowires (NWs) has been increased during the recent years to biosensing, low power transistors and thermoelectric devices. Electron beam and side wall transfer lithography have been widely used to manufacture NWs [1,2]. Both these techniques are time consuming and costly process. In this study, large arrays of suspended and strain-free Si1-xGexnanowires (NWs) (x=0.27-0.57) with a size of (50 nm to 500 nm in width and 6µm in length) have been manufactured. At first, conventional I-line lithography has been applied to form wires with large size (1 µm in width and 6µm in length) and then the dimensions were decreased to nano-scale level by focused ion beam (FIB). In this way, there is also the possibility to suspend these wires for a better thermal and electrical isolation. The crystalline quality of NWs was examined by transmission electron microscopy (TEM) and electrical measurements. The SiGe layers were processed on SOI wafers through condensation method. The wafer processing was initiated by thinning the Si cap of SOI wafers to 30 nm by thermal oxidation. A 100 nm thick Si0.73Ge0.27 epitaxial layer was deposited consequently and then condensed by oxidation at 1050 C followed by 850 C. The Atomic force microscopy (AFM) has been used to determine the surface roughness of final sample which shows less than 1 nm roughness for 1×1 μm2 areas. The Ge content was adopted after the layer thickness and oxidation time. The final thickness of SiGe layer was 60 nm according to SEM analysis and the Ge content was determined by XRD and RBS techniques. Fig.1 shows the XRD rocking curves of the initial SiGe layer and after condensation for two process times. The formed SiGe on oxide (SGOI) were process to form wires (1 µm in width and 6 µm in length ) by using I-line lithography and dry etching. Each chip consisted of an array of 50 NWs, which had four metal (Ti/Pt) contacts in couple on both sides for electrical measurement. In order to reduce the contact resistance of these NWs a 15 nm thick Ni film was evaporated at the contact regions and Rapid thermal annealing (RTA) treated at 450 ºC for 30 seconds to form Ni-SiGe prior to metallization. The unreacted Ni was then removed by 96% H2SO4 in H2O. FIB technique was used at this stage to decrease the width of wires to (50 nm to 500 nm) as shown in Fig.2a and 2b. A 20nm SiO2was deposited prior to FIB-thinning to protect the SiGe wires from eventual damages from Ga-ions. The electrical properties of these wires was measured by a set-up measurement consisted of a Cascade 11000 shielded probe station equipped. The NWs can also suspended by FIB technique as well. This provides to a better electrical and thermal measurement of the NWs. The suspended nanowire is shown in Fig3. In summary, the presented material and device processing in this study can be applied to fabricate SiGe NWRs with a long range of Ge content and dimensions for nano-scaled sensors and devices. Acknowledgement The authors acknowledge financial support from Swedish Foundation for Strategic Research “SSF” for this research (EM-011-0002). References [1] J.Hållstedt, P.E.Hellström and H.Radamson,” Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs,” Thin Solid Films., vol. 517 , pp.117-120, 2008. [2] R.Juhasz ,N. Elfström and J. Linnros,” Controlled Fabrication of Silicon Nanowires by Electron Beam Lithography and Electrochemical Size Reduction,” Nano Lett., vol. 5 , pp.275-280, 2005. Figures caption Figure 1. XRD rocking curves of SiGe before and after condensation. Figure 2. SEM images of the sample at different steps of two-dimensional patterning: a) Top view of the nanowires which are fabricated by I-line lithography and b) Nanowires are thinned by FIB. Figure 3. 3D SEM image of the suspended nanowire after finalizing the fabrication with FIB. Thickness of the nanowire is 130nm (z direction) while the width is 200nm (y direction).