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The conventional address map often incurs traffic congestion in on-chip memory components and degrades memory utilization when the access pattern of an application is not matched with the address map. To reduce traffic congestion and improve the memory system performance, we propose an adaptive image size padding technique for a given address mapping and a hardware configuration. In the presented software approach, the system can adaptively determine the image pad size at the application-invoke time to enhance the load balancing across the on-chip memory hierarchy. Mainly targeting a high-bandwidth image processing application running in a device accelerator of an embedded system, we present the design, describe the algorithm, and conduct the performance experiment. As a result, the experiments indicate the presented design can improve load balancing up to 95% and performance up to 35%, with insignificant memory footprint overheads. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Given the distinctive characteristics of flash-based solid-state drives (SSDs), such as out-of-place update scheme, as compared to traditional block storage devices, a flash translation layer (FTL) has been introduced to hide these features. In the FTL, there is an address translation module that implements the conversion from logical addresses to physical addresses. However, existing address mapping algorithms currently fail to fully exploit the mapping information generated by large I/O requests. First, based on this observation, we propose a novel continuity compressed page-level flash address mapping method (CCFTL). This method effectively compresses the mapping relationship between consecutive logical addresses and physical addresses, enabling the storage of more mapping information within the same mapping cache size. Next, we introduce two-level LRU linked list to mitigate the issue of compressed mapping entry splitting that arises from handling write requests. Finally, our experiments show that CCFTL reduced average response times by 52.67%, 16.81%, and 12.71% compared to DFTL, TPFTL, and MFTL, respectively. As the mapping cache size decreases from 2 MB to 1 MB, then further decreases to 256 KB, 128 KB, and eventually down to 64 KB, CCFTL experiences an average decline ratio of less than 3% in average response time, while the other three algorithms show an average decline ratio of 9.51%. • Propose an address mapping method using continuous entry compression. • Introduce two-level LRU lists with an index to solve compressed node splitting. • Demonstrate a stronger stability of our algorithm during the cache decline process. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Beijing University of Technology is the property of Journal of Beijing University of Technology, Editorial Department and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.

A statistical method was proposed to extract multiple-cell upsets (MCUs) from single-event upsets (SEUs) without the physical-to-logical address mapping of the device under test (DUT). The method was first developed to extract the mapping relation between the least significant bits (LSBs) of the physical address and the logical address bits. Then, the mapping relation was utilized to extract MCUs from the SEUs. Using the proposed method, the proportion, size, and shape of the MCU can be obtained with high accuracy. To evaluate the proposed statistical method, the method was applied to SEU test data of a 0.18-μm static random-access memory (SRAM) irradiated by various heavy ions. The results demonstrated its effectiveness in MCU extraction. [ABSTRACT FROM AUTHOR]

Due to the ever-growing demands of larger capacity of flash storage devices, various new manufacturing techniques have been proposed to provide high-density and large-capacity NAND flash devices. Among these new techniques, 3-D NAND flash is regarded as one of the most promising candidates for the next-generation flash storage devices. 3-D NAND flash brings high bit density and significant cost saving via stacking memory cells vertically. However, the read/write and erase units of 3-D NAND flash also grow larger than those of traditional planner flash devices. This growing trend of read/write and erase units for 3-D NAND flash imposes significant management difficulties, such as the grown size of mapping information, decreased garbage collection efficiency, and worsened write amplification issue. To alleviate these negative impacts of the growing read/write and erase units, this paper proposes a multiregional space management design to achieve subpage-level management while adaptively adjusting mapping granularity by considering the user behaviors. The proposed design was evaluated by a series of experiments, and results show that the access performance can be improved by 64%. [ABSTRACT FROM AUTHOR]

Structure is used more extensively used in program such as scientific computing. But the non-continuity and the non-aligment of vectorization structure array have a dramatic influence on the efficiency of program's vectorizaton. To reduce the access to these addresses during the SIMD vectorization, a structure peeling model is proposed based on the structure which combines domain access affinity and domain data type. At the same time, to meet t the requirement of memory access continuity and alignment in the vectorization of structured array, an address conversion method is proposed which structure arrays are mapped one by one map to two-dimensional arrays, further reducing the failure rate of cache. By using the test suites of gcc_vec, spec2000 and spec2006, the experimental results on the compiler of automatic vector show that the performance of optimized method can be improved by more than 8%. [ABSTRACT FROM AUTHOR]

Address mapping for flash storage devices has been a challenging design issue for controllers because of rapidly growing device capacity. In contrast with existing mapping methods, this study proposes a capacity-independent address mapping method to decouple the required on-device RAM space from the capacity of a flash storage device. Especially, the required RAM size of the proposed method depends only on the user accessed data set, which is also referred to as the working set, while the page-level performance can be nearly achieved. In addition, a simple but practical wear-leveling design is proposed with the capability in lifetime estimation of flash storage devices. Experiments of the proposed scheme obtained encouraging results. [ABSTRACT FROM AUTHOR]

NAND Flash based Solid State Drive (SSD) has been utilized in enterprise servers and high performance computing environments due to its various advantages, such as fast access speed, low power consumption, high reliability, etc. Since SSD suffers from poor performance of random writes and limited lifespan, a workload adaptive page-level address mapping algorithm, named WAPFTL, is proposed, which can predict the characteristics of incoming requests and dynamically adapt the cache strategy of address mapping information. Experimental results show that WAPFTL can improve the cache hit ratio and reduce the number of expensive extra read/write operations by jointly exploiting the temporal and spatial localities of workloads efficiently. Besides, WAPFTL can also reduce the number of erase operations, thus improving the overall performance of SSD. [ABSTRACT FROM AUTHOR]

With the continuous development of Wireless Sensor Network (WSN) technology and its expanding range of applications, the limitations of data-centered WSN are exposed. Therefore, in order to meet the requirements of application and management, it is particularly important to uniquely identify the node on a global scale by assigning an identifier for the sensor node. Firstly, the paper proposes the integrated architecture of the WSN identifier resolution, based on the implementation of hardware gateway and the design of system software, completes the mapping between the identifier of sensor node and the communication address of the sensor node in WSN, and then achieves tracing and management of the sensor node's application. Finally, the system is validated to be effective with being applied in the smart home. [ABSTRACT FROM AUTHOR]

The huge numbers of computers, devices and networks that connected to the Internet in the networking industry, that require more address space, better Quality of Services support, greater security, and an increasing number of media types and Internet-capable devices have all contributed to drive the development of new IPv6 protocol. The major importance during the development of IPv6 has been how to do the transition away from IPv4 towards IPv6 and vice versa. The work on transition strategies, tools, and mechanisms has been part of the basic IPv6 design effort from the beginning. The transition process from the current IPv4 to the future IPv6 is probably one of the most important subjects during the next generation protocols. This paper reviews the basics of IPv4 and IPv6 headers, and the methods for managing the transformation between IPv4 and IPv6. The proposed algorithms deal with header processing transformation transition between IPv4/IPv6 and vice versa depending on the bi-directional identification and recognition processes of the two distinct headers. [ABSTRACT FROM AUTHOR]

Abstract: The flash memory solid-state disk (SSD) is emerging as a killer application for NAND flash memory due to its high performance and low power consumption. To attain high write performance, recent SSDs use an internal SDRAM write buffer and parallel architecture that uses interleaving techniques. In such architecture, coarse-grained address mapping called superblock mapping is inevitably used to exploit the parallel architecture. However, superblock mapping shows poor performance for random write requests. In this paper, we propose a novel victim block selection policy for the write buffer considering the parallel architecture of SSD. We also propose a multi-level address mapping scheme that supports small-sized write requests while utilizing the parallel architecture. Experimental results show that the proposed scheme improves the I/O performance of SSD by up to 64% compared to the existing technique. [Copyright &y& Elsevier]

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters. [ABSTRACT FROM AUTHOR]

An FTL (flash translation layer), which most flash storage devices are equipped with, needs to guarantee the consistency of modified metadata from a sudden power failure. This crash recovery scheme significantly affects the writing performance of a flash storage device during its normal operation, as well as its reliability and recovery performance; therefore, it is desirable to make the crash recovery scheme efficient. Despite the practical importance of a crash recovery scheme in an FTL, few works exist that deal with the crash recovery issue in FTL in a comprehensive manner. This study proposed a novel crash recovery scheme called FastCheck for a hybrid mapping FTL called Fully Associative Sector Translation (FAST). FastCheck can efficiently secure the newly generated address-mapping information using periodic checkpoints, and at the same time, leverages the characteristics of an FAST FTL, where the log blocks in a log area are used in a round-robin way. Thus, it provides two major advantages over the existing FTL recovery schemes: one is having a low logging overhead during normal operations in the FTL and the other to have a fast recovery time in an environment where the log provisioning rate is relatively high, e.g., over 20%, and the flash memory capacity is very large, e.g., 32 GB or 64 GB. [ABSTRACT FROM AUTHOR]