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3. Real-time full-wafer design-based inter-layer virtual metrology

22. Practical DTCO through design/patterning exploration

25. 14-nm photomask simulation sensitivity

30. Full-chip correction of implant layer accounting for underlying topography

38. Applicability of global source mask optimization to 22/20nm node and beyond

39. Demonstrating the benefits of source-mask optimization and enabling technologies through experiment and simulations

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