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12. Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2 and Gate Stack Configuration

Author

K. Das Satish, Baral Biswajit, M. Biswal Sudhansu, Adak Sarosij, and K. Swain Sanjit

Subjects
Materials science, business.industry, General Engineering, 02 engineering and technology, 010402 general chemistry, 021001 nanoscience & nanotechnology, 01 natural sciences, 0104 chemical sciences, Stack (abstract data type), Performance comparison, MOSFET, Optoelectronics, General Materials Science, 0210 nano-technology, business, AND gate
Abstract

Objective:: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material. Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology. Result:: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred that gate stack technology gave a better performance over SiO2 oxide layer. Conclusion:: These results have significant effects in analog, RF and linearity operations. In this work, computer aided design (TCAD) simulations by 2D ATLAS, Silvaco International have been used.

Published
2020
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28. Performance Study of GCGS DG-MOSFETs for Asymmetric Doping and High K Oxide Material Using NQS Method.

Author

SWAIN, SANJIT KUMAR, ADAK, SAROSIJ, PARIJA, SARADIYA, and SARKAR, CHANDAN KUMAR

Subjects
METAL oxide semiconductor field-effect transistors, DOPING agents (Chemistry), RADIO frequency, PARAMETER estimation, NUMBER theory
Abstract

This work reported the analog and radio frequency performance for the Graded channel Gate stack double gate MOSFET structure for change in different high K oxide materials in the gate stack region. A wide comparison is established by considering the 2D TCAD simulator for change in doping concentration along the channel. This novel structure consists of gate stack engineering i.e. placing high-K layer over low-K region and non-uniform doping concentration to mitigate the SCEs and enhancing the performance of the existing devices. This novel device has the ability to suppressing the leakage current due stack techniques, avoiding the bipolar parasitic effect due to graded channel and simultaneously achieving higher breakdown voltage and better analog and RF performances. Therefore this device needs to be studied thoroughly for non uniform doping and different high K oxide materials to be reliable for future applications. Different parameters related to analog performances, such as output resistance, intrinsic gain, early voltage and output are studied. Similarly different RF parameters are also found out considering nonquasistatic (NQS) effect by interchanging the doping concentration and high-K layer materials. The 2D Sentrausu TCAD software was considered for carrying out the simulations for the proposed device with accurate validation. The result reveals that there is significant improvement on the performance of the proposed device for considering stack and graded channel techniques. [ABSTRACT FROM AUTHOR]

Published
2018

29. Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2and Gate Stack Configuration

Author

Swain, Sanjit K., Biswal, Sudhansu M., Das, Satish K., Adak, Sarosij, and Baral, Biswajit

Abstract

Objective: In this proposed work, the Analog, RF and Linearity performances of a DGMOSFET have been analyzed by considering InAs as a channel material. Methods: For the very first time, gate stack techniques in this device have been incorporated and a comparative analysis is conducted with respect to SiO2 oxide layer. The variations in different patterns of oxide layer and their comparison have been thoroughly investigated to have a better understanding of various performance parameters. A thorough analysis of the key figure-of-merits such as trans-conductance factor, transconductance generation factor (TGF), gate capacitance, cutoff frequency (fT), maximum frequency of oscillation (fmax), GBW and various linearity parameters such as gm2, gm3,VIP2, VIP3, IIP3, has been studied with respect to SiO2 oxide material and gate stack technology. Result: The simulation results revealed that the performances of the device are sensitive to both the oxide materials and it was also inferred that gate stack technology gave a better performance over SiO2 oxide layer. Conclusion: These results have significant effects in analog, RF and linearity operations. In this work, computer aided design (TCAD) simulations by 2D ATLAS, Silvaco International have been used.

Published
2020
Full Text
View/download PDF

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