Search

Searchable Symmetric Encryption (SSE), which enables users to search over encrypted data without decryption, has gained increasing attention from both academic and industrial fields. However, existing SSE schemes either have low search efficiency or cannot support multi-keyword search, dynamic updates, and result verification simultaneously. To solve these problems, we propose a Verifiable and Dynamic Multi-keyword Search (VDMS) scheme over encrypted data by using the bitmap and RSA accumulator, which provides multi-keyword search over encrypted data in an efficient, verifiable and updated way. The bitmap is used as a data structure to build the indexes, which improves the search efficiency and reduces the storage space of the indexes. The RSA accumulator and bitmap are combined to verify the correctness of results. Formal security analysis proves that our VDMS is adaptively secure against Chosen-Keyword Attacks (CKA), and empirical experiments using a real-world dataset demonstrate that our VDMS is efficient and feasible in practical applications.

This paper presents a fully integrated energy-efficient memory-based direct digital frequency synthesizer (DDFS). To overcome the limitation of using an accumulator and a Read-Only Memory (ROM) Lookup Table (LUT) within a DDFS, the proposed design utilizes a 6-bit memory with a configured mode of operation to synchronize the digital output clock with the input sampling clock. The proposed DDFS is able to tune the output phase and frequency once a phase rotator is used in the input clock path. To realize the proposed DDFS, a 6-bit memory in front-end and some analog blocks in back-end are employed. The prototype DDFS achieves jitter below 12.7 psrms integrated over a 100 MHz bandwidth with 28.25 Hz resolution while consuming less than 3 mW at sampling clock 3.12 GHz. The proposed DDFS is fabricated in a 0.9 V TSMC 7 nm CMOS process and occupies a core area of only 0.014 mm.

This paper presents a ternary low-density parity-check (LDPC) error correction system for wireless electrocardiogram sensors to improve the accuracy of arrhythmia classification. The classification system is based on ternary Delta-modulated bitstreams and rotation linear kernel support vector machines, which identifies the supraventricular ectopic beat (SVEB) and the ventricular ectopic beat (VEB) over the normal heartbeats. We model errors using a ternary symmetric channel with probability parameter p and construct a variety of ternary LDPC codes with different coding rates by concatenating two-component sub-matrices to form a parity-check matrix with a quasi-cyclic structure that facilitates the hardware design. In particular, a hardware-friendly LDPC encoder circuit is proposed that leverages the highly structured parity-check matrix to perform serial generation of the parity symbols using an accumulator and a look-up table. The encoder circuits are implemented on FPGA and synthesized on ASIC using a 32 nm CMOS process. Simulation results show that the ternary LDPC codes can significantly improve classification accuracy in the presence of errors. For example, with an error probability of up to 21% in the sensor output bitstreams, the classification accuracy remains above 99% with the proposed error correction system.

Spiking Neural Networks (SNNs) have recently emerged as a new generation of low-power deep neural networks due to sparse, asynchronous, and binary event-driven processing. Most previous deep SNN optimization methods focus on static datasets (e.g., MNIST) from a conventional frame-based camera. On the other hand, optimization techniques for event data from Dynamic Vision Sensor (DVS) cameras are still at infancy. Most prior SNN techniques handling DVS data are limited to shallow networks and thus, show low performance. Generally, we observe that the integrate-and-fire behavior of spiking neurons diminishes spike activity in deeper layers. The sparse spike activity results in a sub-optimal solution during training (i.e., performance degradation). To address this limitation, we propose novel algorithmic and architectural advances to accelerate the training of very deep SNNs on DVS data. Specifically, we propose Spike Activation Lift Training (SALT) which increases spike activity across all layers by optimizing both weights and thresholds in convolutional layers. After applying SALT, we train the weights based on the cross-entropy loss. SALT helps the networks to convey ample information across all layers during training and therefore improves the performance. Furthermore, we propose a simple and effective architecture, called Switched-BN, which exploits Batch Normalization (BN). Previous methods show that the standard BN is incompatible with the temporal dynamics of SNNs. Therefore, in Switched-BN architecture, we apply BN to the last layer of an SNN after accumulating all the spikes from previous layer with a spike voltage accumulator (i.e., converting temporal spike information to float value). Even though we apply BN in just one layer of SNNs, our results demonstrate a considerable performance gain without any significant computational overhead. Through extensive experiments, we show the effectiveness of SALT and Switched-BN for training very deep SNNs from scratch on various benchmarks including, DVS-Cifar10, N-Caltech, DHP19, CIFAR10, and CIFAR100. To the best of our knowledge, this is the first work showing state-of-the-art performance with deep SNNs on DVS data.

Max & min architectures for stochastic computing (SC) are introduced. Their key characteristic is the utilization of an accumulator to store the signed difference between the two inputs, without randomizing sources. This property results in fast-converging and highly accurate computations using short sequence lengths, improving on the latency–accuracy tradeoff of existing SC max–min architectures. The operation of the proposed architectures is modeled using Markov Chains, resulting in in-depth analysis, the derivation of their statistical properties, and guidelines for selecting the register’s size to achieve overall design optimization. The computational accuracy and the hardware requirements of the proposed architectures are compared to those of existing ones in the SC literature, using MATLAB and Synopsys Tools. The efficacy of the proposed architectures is demonstrated by realizing a $3 \times 3$ median filter and using it in an image processing application.

In this article, a novel high-speed floating-point multiply-accumulator (FPMAC) is proposed. It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC). The multiplier is realized by a radix-4 Booth encoding based on sign-magnitude inputs. The FAAC contains a bidirectional shift alignment, a fast 3:1 compressor, and a three-operand leading-zero predictor (LZP). Due to the simplification of implementation steps, a short critical path, and a full-pipelined structure, our FPMAC achieves a high running speed while sustaining the good performance of delay and resource consumption. We have implemented and evaluated our FPMAC on two devices from Xilinx. Compared with two contrast FPMAC architectures, the results show that the maximum clock frequencies of our FPMAC increase by 33.4%–74.4% in single-precision floating-point (SFP) and 15.8%–86.1% in double-precision floating-point (DFP).

The perception, localization, and navigation of its environment are essential for autonomous mobile robots and vehicles. For that reason, a 2D Laser rangefinder sensor is used popularly in mobile robot applications to measure the origin of the robot to its surrounding objects. The measurement data generated by the sensor is transmitted to the controller, where the data is processed by one or multiple suitable algorithms in several steps to extract the desired information. Universal Hough Transform (UHT) is one of the appropriate and popular algorithms to extract the primitive geometry such as straight line, which later will be used in the further step of data processing. However, the UHT has high computational complexity and requires the so-called accumulator array, which is less suitable for real-time applications where a high speed and low complexity computation is highly demanded. In this study, an Accumulator-free Hough Transform (AfHT) is proposed to reduce the computational complexity and eliminate the need for the accumulator array. The proposed algorithm is validated using the measurement data from a 2D laser scanner and compared to the standard Hough Transform. As a result, the extracted value of AfHT shows a good agreement with that of UHT but with a significant reduction in the complexity of the computation and the need for computer memory.

Verifiable pattern matching enables users to obtain authenticated query results over outsourced data on an untrusted remote server. It is a fundamental problem in many security-critical big data applications, including big database search, human genome data search, text search, etc., especially when these applications are outsourced to third-party clouds. However, the state-of-the-art schemes do not yet support efficient data updates. In this work, we propose the first dynamic verifiable pattern matching scheme to support efficient data updates. The proposed scheme is built on two ideas: one is to embed unique randomness to decouple the character and its index in the outsourced data, enabling efficient data updates; the other is to reduce the verifiable pattern matching problem to a discrete set membership testing problem, which relies on the decoupling introduced in the first idea. Based on these two ideas, the proposed scheme first employs the suffix array index structure to search pattern matching queries. The scheme then authenticates the outsourced text using a newly designed authenticated data structure based on the RSA accumulator, which guarantees the verifiability of pattern matching query results. Data update is naturally supported using the RSA accumulator working on discrete sets. Based on the proposed design, we have prototyped a proof-of-concept for the proposed scheme and have conducted an extensive experimental evaluation. In addition to supporting efficient data update, our experimental results show that the proposed scheme incurs reduced verification cost in comparison with the baseline state-of-the-art scheme.

The rise of the Internet of Things (IoT) and the constant growth of portable electronics have leveraged the concern with energy consumption due to the use of batteries in these devices. The nonvolatile memory (NVM) emerged as a solution to mitigate the problem due to its ability to retain data on sleep mode without a power supply. Nonvolatile processors (NVPs), in turn, may further improve energy saving, by making use of nonvolatile flip-flops (NVFFs) that store system state in parallel, allowing the device to be turned off when idle and resume execution instantly after power-on. This work describes the initial steps to implement a nonvolatile version of Neander, a hypothetical processor created for educational purposes. First, we implemented Neander in Register Transfer Level (RTL), separating the combinational logic from the sequential elements. Then, the latter were replaced by transistor-level descriptions ofvolatile flip-flops. We then validated this implementation by employing a mixed-signal simulation over a set of benchmarks. Results shown the expected behavior for the whole instruction set. Then, we implemented MTJ-based non-volatile flip-flops in circuit-level, using an open-source MTJ model. These elements were exhaustive validated using electrical simulations. With these results, we intend to carry on the implementation and fully equip our processor with nonvolatile features such as instant wake up.

In hypercompetitive embedded system environment, to develop the unique characteristic of machine learning computation for more efficient MAC design for reduced both the area and power. In this paper, Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations use in pipelined structure is usually adopted to improve the performance by reducing the number of adder circuits. The proposed a pipelining method that eliminates some of the flip-flops in carry look adder in selectively. Here, introduce the applying the Feed forward-Cutset-Free (FCF) pipelining method in borrow save adder (BSA) to the accumulator by reducing the design, optimized the power dissipation and undesired data transition in (MFCF-PA). From the FPGA Xilinx simulation output result shows that, the MAC unit reached between 15% and 25% energy saving and area reduction of 15% over the existing carry look ahead adder (CLA) conformist pipelined MAC units.

A digital signal processing (DSP) architecture is presented to compute single bins of the discrete Fourier transform (DFT) with low complexity. This architecture consists of a cascade of simple accumulators working at the input sampling rate and a polyphase finite impulse response (FIR) filter with complex coefficients working at a lower rate. The advantage of this structure is that, for several cases, it is possible to have a system with only one accumulator operating in the high-rate section and a low-order FIR filter working in the low-rate section. However, this depends on the index of the frequency bin to be computed (k) and the number of DFT points (N). Advantages and limitations of this approach are presented, and the implementation scheme is elaborated.

The charging device usually uses a transformer and a diode bridge. Charging the battery is called direct charging. Because it does not have a safety for the battery it can cause heat to the battery. But over time, this is no longer effective, this work can be done digitally using a microcontroller.. However, this tool is still not perfect because at the time of testing it cannot be set, sooner or later, the charging is to cut time efficiency and there is no indicator that states that the charging is full or not. Therefore, based on the description above, the researcher aims to make a smart charging accumulator based on the Arduino Uno microcotroller that is smarter, more efficient and can be used easily, with the advantage of having a tap changer on the transformer that functions as a regulator of the output voltage. as desired and piezoelectric alarm as an indicator if a full charge or there is a problem with the equipment itself.

With the explosive growth in the number of IoT devices, ensuring the integrity of the massive data generated by these devices has become an important issue. Due to the limitation of hardware, most past data integrity verification schemes randomly select partial data blocks and then perform integrity validation on those blocks instead of examining the entire dataset. This will result in that unsampled data blocks cannot be detected even if they are tampered with. To solve this problem, we propose a new and effective integrity auditing mechanism of sensor data based on a bilinear map accumulator. Using the proposed approach will examine all the data blocks in the dataset, not just some of the data blocks, thus, eliminating the possibility of any cloud manipulation. Compared with other schemes, our proposed solution has been proved to be highly secure for all necessary security requirements, including tag forgery, data deletion, replacement, replay, and data leakage attacks. The solution reduces the computational and storage costs of cloud storage providers and verifiers, and also supports dynamic operations for data owners to insert, delete, and update data by using a tag index table (TIT). Compared with existing schemes based on RSA accumulator, our scheme has the advantages of fast verification and witness generation and no need to map data blocks to prime numbers. The new solution supports all the characteristics of a data integrity verification scheme.

Reduce is a fundamental computing pattern, which is widely involved in scientific and engineering applications. For example, accumulation, the most common example of reduce pattern, is the core of applications such as dot product, matrix multiplication, and finite impulse response (FIR) filter. However, there is a trade-off between performance and area in the hardware implementation of the reduce pattern. To solve this problem, we propose an optimized reduction method that can handle multiple arbitrary-length sets. The performance of the proposed method is evaluated for both a single data set and numerous data sets. Moreover, to quickly differentiate the data of different sets in the reduction circuit, individual modules are designed to manage the data. We implement the design on FPGAs and present the experimental results. The proposed design with high performance and low resource consumption can achieve at least 1.59 times improvement on area-time product compared with the reported methods.

The improvement of advanced driver assistance systems (ADAS) and their safety assessment rely on the understanding of scenario-dependent driving behaviours, such as steering to avoid collisions. This study compares driver models that predict when a driver starts steering away to overtake a cyclist on rural roads. The comparison is among four models: a threshold model, an accumulator model, and two models inspired by a proportional-integral and proportional-integral-derivative controller. These models were tested and cross-applied using two different datasets: one from a naturalistic driving (ND) study and one from a test-track (TT) experiment. Two perceptual variables, expansion rate (the horizontal angular expansion rate of the image of the lead road user on the driver’s retina) and inverse tau (the ratio between the image’s expansion rate and its horizontal optical size), were tested as input to the models. A linear cost function is proposed that can obtain the optimal parameters of the models by computationally efficient linear programming. The results show that the models based on inverse tau fitted the data better than the models that included expansion rate. In general, the models fitted the ND data reasonably well, but not as well the TT data. For the ND data, the models including an accumulative component outperformed the threshold model. For the TT data, due to the poorer fit of the models, more analysis is required to determine the merit of the models. The models fitted to TT data captured the overall pattern of steering onsets in the ND data rather well, but with a persistent bias, probably due to the drivers employing a more cautious strategy in TT. The models compared in this paper may support the virtual safety assessment of ADAS so that driver behaviour may be considered in the design and evaluation of new safety systems.

By introducing stochastic computing (SC), the hardware consumption of Deep Neural Network (DNN) can be reduced significantly. However, long SC sequence length is needed to maintain the accuracy, which results in extended computation time. To shorten the sequence length, we propose two high-accuracy SC computation units to improve the precision of SC-DNN, which are the rematching-based correlation-independent multiplier and the accumulator-based Rectified Linear Unit. Moreover, a length-adaptive method that uses variable lengths for different images is adopted to decrease the average sequence length. Software simulation shows that the SC design has just 0.01% accuracy loss with only the sequence length of 20 for MNIST dataset comparing to the binary system. The ASIC layout results demonstrate the area efficiency is improved by 16X comparing to the latest SC-DNN with similar accuracy loss.

The charging device usually uses a transformer and a diode bridge. Charging the battery is called direct charging. Because it does not have a safety for the battery it can cause heat to the battery. But over time, this is no longer effective, this work can be done digitally using a microcontroller.. However, this tool is still not perfect because at the time of testing it cannot be set, sooner or later, the charging is to cut time efficiency and there is no indicator that states that the charging is full or not. Therefore, based on the description above, the researcher aims to make a smart charging accumulator based on the Arduino Uno microcotroller that is smarter, more efficient and can be used easily, with the advantage of having a tap changer on the transformer that functions as a regulator of the output voltage. as desired and piezoelectric alarm as an indicator if a full charge or there is a problem with the equipment itself.

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

We define “reproducibility” as getting bitwise identical results from multiple runs of the same program, perhaps with different hardware resources or other changes that should not affect the answer. Many users depend on reproducibility for debugging or correctness. However, dynamic scheduling of parallel computing resources, combined with nonassociative floating point addition, makes reproducibility challenging even for summation, or operations like the BLAS. We describe a “reproducible accumulator” data structure (the “binned number”) and associated algorithms to reproducibly sum binary floating point numbers, independent of summation order. We use a subset of the IEEE Floating Point Standard 754-2008 and bitwise operations on the standard representations in memory. Our approach requires only one read-only pass over the data, and one reduction in parallel, using a 6-word reproducible accumulator (more words can be used for higher accuracy), enabling standard tiling optimization techniques. Summing n words with a 6-word reproducible accumulator requires approximately 9 n floating point operations (arithmetic, comparison, and absolute value) and approximately 3 n bitwise operations. The final error bound with a 6-word reproducible accumulator and our default settings can be up to 2 29 times smaller than the error bound for conventional (recursive) summation on ill-conditioned double-precision inputs.

The Internet of Things (IoT) is the core infrastructure of the smart city information system. With the explosive growth of IoT devices, how to securely maintain the important data generated by IoT devices has become an important issue. In the conventional IoT-cloud based infrastructure, the sensitive IoT data was stored in a third cloud service provider. However, in such a manner, the private IoT data may be disclosed by the cloud server since the cloud server knows all the data stored in it. This paper, for the first time, proposes a decentralized secure mechanism based on the blockchain technique to store the important data generated in the IoT system. This mechanism effectively solves the data reliability, security and privacy issues that may be encountered in the conventional IoT-cloud system. Considering the defects of simplified payment verification used by light nodes in blockchain networks, this paper proposes an Unspent Transaction Output (UTXO) verification mechanism based on the RSA accumulator, which makes the computational complexity of light nodes to generate and verify the UTXO proof to be constant. The proposed mechanism not only provides proof of inclusion but also supports efficient proof of exclusion for a lightweight node. Our experiment results indicate that the proposed scheme is practical and efficient.

Hough Transform (HT) algorithm is commonly used for linear detection but requires huge memory and computational complexity. In this paper, we design an adapted hardware architecture of HT for straight lane lines detection. Because the lane markings parallel in the 3D world cannot be horizontal or vertical in the image plane, we optimize the architecture and the computational complexity of HT. The proposed architecture uses (Y-intercept, θ) parameterization for the construction of HS and lane orientation, which also simplifies the inverse HT (IHT) operation and reduces the dimension of the accumulator. The efficiency of the proposed architecture is demonstrated by a software-hardware co-simulation on a Xilinx Virtex-5 ML505 platform. Compared to other reported hardware implementation, the proposed method can reduce the circuit resources. The processing speed is 1.47 m s and the detection rate is 92%.

The possibility of the inference of neural networks on minifloats has been studied. Calculations using a float16 accumulator for intermediate computing were performed. Performance was tested on the GoogleNet, ResNet-50, and MobileNet-v2 convolutional neural network and the DeepSpeechv01 recurrent network. The experiments showed that the performance of these neural networks with 11-bit minifloats is not inferior to the performance of networks with the float32 standard type without additional training. The results indicate that minifloats can be used to design efficient computers for the inference of neural networks.

In the process of development in the Semiconductor Industry, Intellectual Property (IP) piracy has become a threat to innovation. To reduce this, logic encryption is found to be an effective solution. It is achieved by employing the concept of keys for the circuits. In this paper, logic encryption is a concept is applied to the previously proposed Least Transistor Count (LTC) full adder. The concept of least gates is taken for its advantage for its low power and delay when compared to conventional adders. The proposed work is compared with the LTC full adder and with similar encrypted full adders and has observed 1000 times decrease in power. Delay is recorded as 25ns for sum and 4.32ps for carry signal. The proposed work has 56 per cent more power and 80 per cent more area than the LTC adder. But it has achieved a drop of 59 per cent in transistor count than previous works and a strong level of encryption than previous works. The proposed encrypted full adder is extended to a Multiplier and Accumulator (MAC) unit design. An encrypted MAC design is proposed by focusing on the key combinations and positions.

A novel image motion self-registration algorithm was proposed and realized to improve the effectiveness of Time-Delay-Integration image processing. First, to overcome the defects of the on-chip accumulator, a CMOS camera with off-chip digital accumulator was designed. Compared to the traditional on-chip Time-Delay-Integration, the new off-chip digital Time-Delay-Integration cost none silicon area and can integrate signal processing easily. The novel algorithm was developed to work with this new off-chip digital Time-Delay-Integration. To assess the proposed algorithm, simulations and experiments were carried out. With the new algorithm, the cross-correlation similarity of the Time-Delay-Integration images improved from 0.9257 to 0.9587, even when the image motion mismatch rate is 0.1. Further experiments proved the effectiveness of the proposed algorithm when the image motion mismatch is existing. This algorithm is suitable for applications in remote sensing systems with characters of low-illumination and high scanning speed.

Previous solutions on security and privacy in Industrial Internet of Things (IIoT) focus primarily on the data or the deployment and communication problems of devices. However, the management and authentication of IoT devices for IIoT systems has received less attention. To facilitate the research on this area, we take the IIoT control system as an example. It is crucial to authenticate the relationships among devices to ensure that data can only be accessed by authenticated parties. In this paper, we provide a feasible solution to address the aforementioned issue. Considering that a directed graph can be used to intuitively represent such relationships, we present a dynamically updatable privacy-preserving authentication scheme for general directed graphs. Specifically, our scheme is based on the cryptographic accumulator and an underlying standard digital signature scheme. We formalize its security notions and prove its security under the adaptive chosen-message attacks. The efficiency of our scheme is evaluated in order to illustrate its practically for real-world applications.

These days age development to be more prominent in biometric angle. Particularly CAD machine is essentially renowned for ordering and division. In this theory Kidney issue and the division systems are examined. The kidney inconvenience recognizable proof and the finding in logical region are well focused on kidney’s external layer. Accordingly, the inward inconvenience isn’t yet considered in each case. This is mulled over and another time is produced in this examination for division of Kidney using GBDT (Gradient Boosting Decision Tree) thought. The exploration managed with a novel proficient componentThis research was handled with novel efficient mechanism named as GBDT. A systematic technique termed GBDT was utilized to enhance the predictive model. In the process of renal cortex phase localization, a technique which integrates Generalized Hough Transform (GHT) with Active Appearance Models (AAM) was enforced for kidney localization to appraise the renal cortex thickness. The AAM method always matches a new data to the appearance model by minimizing the intensity of root mean square (RMS) between the new data as well as appearance model instance. And finally, from the result of the localization phase, the proposed method GBDT was employed to segregate the kidney into various components. Then an accumulator matrix indicating the possible position of an object was constructed pursuant to the R-table, where the training set data is normally used in this form of table. The results were evaluated to reveal the higher achievement of the proposed system.

Evidence accumulation models (EAMs) have become the dominant models of rapid decision-making. Several variants of these models have been proposed, ranging from the simple linear ballistic accumulator (LBA) to the more complex leaky-competing accumulator (LCA), and further extensions that include time-varying rates of evidence accumulation or decision thresholds. Although applications of the simpler variants have been widespread, applications of the more complex models have been fewer, largely due to their intractable likelihood function and the computational cost of mass simulation. Here, I present a framework for efficiently fitting complex EAMs, which uses a new, efficient method of simulating these models. I find that the majority of simulation time is taken up by random number generation (RNG) from the normal distribution, needed for the stochastic noise of the differential equation. To reduce this inefficiency, I propose using the well-known concept within computer science of “look-up tables” (LUTs) as an approximation to the inverse cumulative density function (iCDF) method of RNG, which I call “LUT-iCDF”. I show that when using an appropriately sized LUT, simulations using LUT-iCDF closely match those from the standard RNG method in R. My framework – which I provide a detailed tutorial on how to implement – includes C code for 12 different variants of EAMs using the LUT-iCDF method, and should make the implementation of complex EAMs easier and faster.

The paper presents an unsupervised method for anomaly detection named Adaptive Suppression (AS). The method relies on distance metrics between data points and receives hypothesis about percent of anomalies in dataset. Data points having initial accumulator value, “suppress” each other based on distance. Data points with high retained accumulator values considered as anomalous. We tested the method using anomaly video datasets (QMUL and UCSD). We extract scene dynamics using grid of short-time trackers (TrackGrid) and apply Adaptive Suppression to every TrackLoop (element of TrackGrid) separately, and then aggregate values using maximum. Using proposed method, we obtain competitive results: 0.746 AUC on QMUL, 0.7 on UCSD Ped1, 0.82 AUC on UCSD Ped2. Also, we apply Adaptive Suppression to CIFAR-10 dataset over space of reduced dimensionality (using UMAP) to provide an example of applicability of AS to image data. Possibly, AS has simple implementation and can be applied to any kind of data for which distance (or similarity metrics) exists, allowing to estimate anomaly/uniqueness of texts, images and other types of datasets using Deep Learning methods.

Public cloud storage is a fundamental cloud computing service. Currently, most owners of large data outsource their data to cloud storage services-even high-profile owners such as governments. However, public cloud storage services are not optimal for ensuring the possession and integrity of the outsourced data, a situation that has given rise to many proposed provable data possession check schemes (PDP). A PDP scheme allows data owners to efficiently, periodically, and securely verify that a cloud storage provider possesses the outsourced data. Most of the currently available provable data possession check schemes make selective (i.e., probabilistic) checks using random data blocks to verify data integrity rather than checking the entire dataset. Therefore, these schemes are considered inadequate by critical infrastructure sectors that involve highly sensitive data (critical data). In this paper, a new and efficient deterministic data integrity check scheme called cryptographic-accumulator provable data possession (CAPDP) is proposed. The CAPDP surpasses the common limitations exhibited by other currently proposed schemes. The underlying scheme of the CAPDP is based on a modified RSA-based cryptographic accumulator that has the following advantages: 1) it allows the data owner to perform an unlimited number of data integrity checks; 2) it supports data dynamics; 3) it is efficient in terms of communication, computation and storage costs for both the data owner and the cloud storage provider; 4) the verification operation in the proposed scheme is independent of the number of blocks being verified; 5) it minimizes the burden and cost of the verification process on the data owner's side, enabling verification to be performed even on low-power devices; and 6) it prevents tag forgery, data deletion, replacement, and data leakage attacks and detects replay attacks. Moreover, the prototype implementation and experimental results show that the scheme is applicable in real-life applications.

Recently, edge-device training has arisen an urgent necessity since it can enhance the model adaptability without causing high transmission cost and privacy issues. Due to the need for a wide data range and high data precision to improve accuracy, DNN training requires much wider floating-point (FP) data for convolution and complicated arithmetics for batch normalization. They lead to massive computation and memory access energy, which yields challenges for power-constrained edge-devices. This paper proposes a novel PE, called LPE, with three innovations to solve this issue. First, LPE stores the operands in the posit format, satisfying both precision and data range with lower bit-width. It reduces training latency and energy for memory access. Second, LPE transfers complicated arithmetics during training into the logarithm domain, including multiplication in convolution layer and division, square, square root in batch normalization layers. It reduces computation energy and improves throughput. Third, LPE contains a two-stage floating-point accumulation unit. It extends the computation range while using the low bit-width accumulator, enhancing precision and reducing power consumption. Evaluated with 28 nm CMOS process, our PE achieves 1.81× power and 1.35× area reduction compared with IEEE 754 float-point 16 (FP16) fused MAC while maintaining the same dynamic range. When performing training with the proposed PE unit, it can achieve 1.97× energy reduction and offer 1.68× speed up.

In this paper, a row-wise XNOR accumulator architecture for STT-MRAM arrays is proposed for parallel and efficient multiply-and-accumulate (MAC) operation. The proposed accumulator supports in-memory computing and binary neural network (BNN) applications. In the proposed architecture, inputs are fed from the complementary bitlines, whereas readout is performed through a time-based sense amplifier (TBS). The proposed architecture that does not require any ADC can exhibit an average error rate of 0.085 for XNOR vector size (i.e., accumulate capacity) of 128 bits, which translates into 98.45% classification accuracy of a multi-layer perceptron (MLP) on the MNIST dataset.

Due to the development of smart flight controller, powerful accumulator with LiPoly cells, global positioning/ navigation systems and light weight mechanical construction the UAV technology is applicable in nearly unlimited technical areas. The small construction and the mobile application is offering a wide area of opportunities in the area of antenna measurements and its characterization in their different function and localization. The paper will describe the special challenges of their interdisciplinary aspects during the design, development and operation phase.

Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. A 16 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx ISE 14.7 design suite. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. In addition to these blocks, designed RISC Processor consists of other blocks like Control unit and data path, Register Bank, Program Counter and Memory. The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that 44% savings in power in case of MAC and that of 12% in case of ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced by 45% in case of MAC and that of 35% in case of ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay by 34% and saves around 88% power compared to conventional processor. Hence the improvement in speed of operation, reduction in power utilization and less area utilization are the key features of designed RISC processor.

Sparse tensor contractions appear commonly in many applications. Efficiently computing a two sparse tensor product is challenging: It not only inherits the challenges from common sparse matrix-matrix multiplication (SpGEMM), i.e., indirect memory access and unknown output size before computation, but also raises new challenges because of high dimensionality of tensors, expensive multi-dimensional index search, and massive intermediate and output data. To address the above challenges, we introduce three optimization techniques by using multi-dimensional, efficient hashtable representation for the accumulator and larger input tensor, and all-stage parallelization. Evaluating with 15 datasets, we show that Sparta brings 28 -- 576× speedup over the traditional sparse tensor contraction with sparse accumulator. With our proposed algorithm- and memory heterogeneity-aware data management, Sparta brings extra performance improvement on the heterogeneous memory with DRAM and Intel Optane DC Persistent Memory Module (PMM) over a state-of-the-art software-based data management solution, a hardware-based data management solution, and PMM-only by 30.7% (up to 98.5%), 10.7% (up to 28.3%) and 17% (up to 65.1%) respectively.

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

The increasing complexity of the cyber-physical products used nowadays along with the ever-expanding firmware and electronics and the connectivity aspects of the industrial environment, require thinking beyond the traditional engineering structures and related design stages.The development and evolution of today’s virtual and physical prototypes to the digital twin approach requires high levels of accuracy of the simulation models, covering a wide range of multiphysical areas, as well as different levels of scale and reliability of the model - depending on life cycle applications. This high levels of accuracy in the use of engineering decision-making models can only be achieved in an integrated environment closely linked to the digital and physical worlds.The aim of this study is to define the Digital Twin concept based on Virtual Prototypes and create virtual prototypes for an existing uninterruptible power supply system with a kinetic battery accumulator.

The cost involved in training deep neural networks (DNNs) on von-Neumann architectures has motivated the development of novel solutions for efficient DNN training accelerators. We propose a hybrid in-memory computing (HIC) architecture for the training of DNNs on hardware accelerators that results in memory-efficient inference and outperforms baseline software accuracy in benchmark tasks. We introduce a weight representation technique that exploits both binary and multi-level phase-change memory (PCM) devices, and this leads to a memory-efficient inference accelerator. Unlike previous in-memory computing-based implementations, we use a low precision weight update accumulator that results in more memory savings. We trained the ResNet-32 network to classify CIFAR-10 images using HIC. For a comparable model size, HIC-based training outperforms baseline network, trained in floating-point 32-bit (FP32) precision, by leveraging appropriate network width multiplier. Furthermore, we observe that HIC-based training results in about 50% less inference model size to achieve baseline comparable accuracy. We also show that the temporal drift in PCM devices has a negligible effect on post-training inference accuracy for extended periods (year). Finally, our simulations indicate HIC-based training naturally ensures that the number of write-erase cycles seen by the devices is a small fraction of the endurance limit of PCM, demonstrating the feasibility of this architecture for achieving hardware platforms that can learn in the field., Comment: Accepted at ISCAS 2021 for publication

Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction of an 8-, 16-, 32-, 64-bit multiplier using the carry-save adder, the Kogge stone adder, and the HNFG adder with the high operating speed of the proposed HNFG gate adder. The architecture of the device and the logic gates which are reversible can be implemented using the Vedic multiplier. The output of the accumulator operation is dependent on the multiplier unit and the adder units. Here, the development of a multiplier and an adder can be built using reversible gates to achieve high operating speeds, and the use of a Vedic multiplier for greater efficiency. Also fewer area and partial elements are used. A comparative study is being conducted between the conventional [1] and the Kogge stone adder based on HNFG. Finally, it has been shown that the proposed HNFG gate with multiplier adder has a relatively high-speed over the conventional method. The whole process of simulation and synthesis is done using Xilinx 14.7 tool.

MAC Unit is the basic building block of any signal processing hardware. At present, every field, such as medicine, astronomy, geography, industry, embedded system, etc requires applications of digital image processing. These fields require real-time processing, and efficiency is necessary in the implementation of digital image processing. Multiplier –and Accumulator (MAC) Units perform the mathematical operation such as convolution. They are the fundamental digital block and are the most computationally and resource-demanding unit. A MAC unit with optimum performance and power consumption is always desired. The primary contribution of this paper is investigating the existing work and techniques used by several authors to minimize the power consumption in the design of MAC Unit. This review can provide aninsight to the beginners in the VLSI Arithmetic Circuit Design to gain more idea on Low power MAC Unit Design.

The Quantum Dot Cellular Automata (QCA) is a latest technology that has gained the curiosity of researchers due to its small size and low power consumption, so it is being researched as a suitable alternate to the CMOS technology. The QCA technology provides a new computational platform in designing digital circuits with the help of quantum-dots. Quantum dots have wide range of application like LED, medical imaging and quantum computing etc. The quantum-dots are Nano crystals that transfer information at Nano scale. This paper proposed an area efficient design and implementation of a 16-bit Multiply-Accumulate unit (MAC). It’s been designed by designing an area efficient novel 1-bit Full adder using QCA it is further used in a 16-bit Parallel binary adder and 8-bit multiplier modules. The design put forth for proposed 1-bit adder has brought down the cell count by 9.09% and area by 33.33%.The proposed design of multiplier has decreased the cell count by 18.7% and area by 9.92% in contrast to other previous designs. The proposed design of MAC has 27110 cells and its area is 77.89 μm2. The simulation results have been verified using the QCADesigner Simulation tool.

We propose a new fast fully unsupervised method to discover semantic patterns. Our algorithm is able to hierarchically find visual categories and produce a segmentation mask where previous methods fail. Through the modeling of what is a visual pattern in an image, we introduce the notion of "semantic levels" and devise a conceptual framework along with measures and a dedicated benchmark dataset for future comparisons. Our algorithm is composed by two phases. A filtering phase, which selects semantical hotsposts by means of an accumulator space, then a clustering phase which propagates the semantic properties of the hotspots on a superpixels basis. We provide both qualitative and quantitative experimental validation, achieving optimal results in terms of robustness to noise and semantic consistency. We also made code and dataset publicly available.

Spectral clustering is a Machine Learning technique intensively used in Big Data applications. It makes extensive use of linear algebra. This article introduces the concept of MapReduce Accelerator (MRA) as the reconfigurable part of a heterogeneous computing system. Although the accelerator we propose is a general purpose one, it has some specific features related to the targeted application. This is possible due to the pseudo-reconfigurable environment which deploys in FPGA a parameterizable programmable accelerator. The main specific characteristics of the accelerator are proposed as a result of the analysis performed on the spectral clustering algorithms. The architecture is described and the spectral clustering algorithms are evaluated. The proposed solution is compared, in terms of computing performance and energy consumption, with other solutions published in the literature. The increase in computing performance is accompanied by a 3-5 times reduction in energy consumed. The accelerator is a linear array of cells controlled by a sequencer loop closed through a reduction network. Each cell is a simple, accumulator-based execution unit with a big two-port register file. The reduction network is a log-depth pipelined circuit performing few reduction functions such as add, min, max. The experimental system is a PYNQ-Z2 board equipped with Zinq 7020 SoC; it is used to implement and evaluate the acceleration provided by an 128-cell MRA.

Based on the moving average filter, a moving accumulative sign filter is proposed, its performance is analysed comprehensively, and it can be applied to the structure of pipeline voter, which can be used for the detection of a single digital signal, and can also be used for the majority voter of two signals. The two-stage voter has been implemented, only use gates and D flip-flop, which greatly reduces the area and power consumption of the voting circuit. The proposed structure has been used in a CDR circuit in a 40 nm SerDes chip.

This work explores the effects of nonassociativity of floating-point addition on Message Passing Interface (MPI) reduction operations. Previous work indicates floating-point summation error is comprised of two independent factors: error based on the summation algorithm and error based on the summands themselves. We find evidence to suggest, for MPI reductions, the error based on summands has a much greater effect than the error based on the summation algorithm. We begin by sampling from the state space of all possible summation orders for MPI reduction algorithms. Next, we show the effect of different random number distributions on summation error, taking a 1000-digit precision floating-point accumulator as ground truth. Our results show empirical error bounds that are much tighter than existing analytical bounds. Last, we simulate different allreduce algorithms on the high performance computing (HPC) proxy application Nekbone and find that the error is relatively stable across algorithms. Our approach provides HPC application developers with more realistic error bounds of MPI reduction operations. Quantifying the small-but nonzero-discrepancies between reduction algorithms can help developers ensure correctness and aid reproducibility across MPI implementations and cluster topologies.

Due to the high demands for computing, the available resources always lack. The approximate computing technique is the key to lowering hardware complexity and improving energy efficiency and performance. However, it is a challenge to properly design approximate multipliers since input data are unseen to users. This challenge can be overcome by Machine Learning (ML) classifiers. ML classifiers can predict the detailed feature of upcoming input data. Previous approximate multipliers are designed using simple adders based on ML classifiers but by using a simple adder-based approximate multiplier, the level of approximation cannot change at runtime. To overcome this drawback, using an accumulator and reconfigurable adders instead of simple adders are proposed in this paper. Also, the rounding technique is applied to approximate floating-point multipliers for further improvement. Our experimental results show that when the error tolerance of our target application is less than 5%, the proposed approximate multiplier can save area by 70.98%, and when the error tolerance is less than 3%, a rounding enhanced simple adders-based approximate multiplier can save area by 65.9% and a reconfigurable adder-based approximate multiplier with rounding can reduce the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.

Most of the computing circuits require multiply-accumulate (MAC) operation which involves the computation of product of the input data bits and subsequent addition or subtraction of that product to the accumulator. As it is seen that the multiplier is the most fundamental module of any MAC unit, it becomes necessary to design the multiplier such that it consumes less power and exhibits minimum delay. Initially, in our work, a 32 bit MAC unit is designed using xor gates and 16-bit Vedic multipliers. The design is then synthesized and implemented in Xilinx Vivado using Verilog HDL. Synopsys DC is also used to analyze parameters such as area and power. When compared to the existing methods, a reduction in power of around 3% is obtained with our proposed work.

Automatic understanding of sports is essential to improve viewer experience and for coaches and players to analyze, strategize and improve game performance. To achieve this it is essential to harness the ability to localize and recognize the actions in sports videos. In this paper we focus on the fast paced sport of badminton. The challenge is to extract relevant spatio-temporal features from several consecutive frames and to classify them as an action or a no-action in minimal time and with minimal computational power. We propose two novel Neural Accumulator (NAC) based frameworks, namely NAC-LSTM and NAC-Dense for aforementioned objective. Neural Accumulator is employed for spatial and temporal feature extraction respectively followed by classification. The actions of the players were annotated as react,lob, forehand, smash,backhand and serve. An Autoencoder-LSTM Network, Dilated Temporal Convolutional Networks (TCN) and Long Term Recurrent Convolutional Network (LRCN) have been designed for comparison. Multiclass recognition has been performed with 5-fold cross validation on several test-train data splits (from 10–50%) to verify the efficacy of the results. The proposed methods achieve a high classification accuracy in strikingly minimal CPU time.

Targeting the continuous demand for processing capabilities, field programmable gate arrays (FPGA) offer a facile platform for processor development. FPGAs answer the need for rapid processor prototyping and testing, while also providing hardware solutions for software engineers. In this context, this work proposes a novel high-speed processor architecture, developed around the traditional Harvard architecture with pipelining. The novelty of this work consists in having two block RAM (BRAM) modules implement the data memory, enabling to simultaneously read and write the instruction data and results respectively. Consequently, every pipeline microinstruction is executed in precisely one clock cycle. Besides the pipeline, a register in the accumulator and logical unit (ALU) allows the employment of execution results in successive instructions. These contributions operate towards high-speed operation of the processor, with an average of one instruction per clock cycle. The proposed processor architecture was implemented in VHDL, and the design was validated by simulation in Xilinx ISIM, as well as by practical tests carried out on an Artix7 35T and a Kintex Ultrascale+FPGA respectively.