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236 results on '"Acacio, Manuel E."'

1. Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing

Author

Muñoz-Martínez, Francisco, Garg, Raveesh, Abellán, José L., Pellauer, Michael, Acacio, Manuel E., and Krishna, Tushar

Subjects
Computer Science - Hardware Architecture
Abstract

Sparsity is a growing trend in modern DNN models. Existing Sparse-Sparse Matrix Multiplication (SpMSpM) accelerators are tailored to a particular SpMSpM dataflow (i.e., Inner Product, Outer Product or Gustavsons), that determines their overall efficiency. We demonstrate that this static decision inherently results in a suboptimal dynamic solution. This is because different SpMSpM kernels show varying features (i.e., dimensions, sparsity pattern, sparsity degree), which makes each dataflow better suited to different data sets. In this work we present Flexagon, the first SpMSpM reconfigurable accelerator that is capable of performing SpMSpM computation by using the particular dataflow that best matches each case. Flexagon accelerator is based on a novel Merger-Reduction Network (MRN) that unifies the concept of reducing and merging in the same substrate, increasing efficiency. Additionally, Flexagon also includes a 3-tier memory hierarchy, specifically tailored to the different access characteristics of the input and output compressed matrices. Using detailed cycle-level simulation of contemporary DNN models from a variety of application domains, we show that Flexagon achieves average performance benefits of 4.59x, 1.71x, and 1.35x with respect to the state-of-the-art SIGMA-like, Sparch-like and GAMMA-like accelerators (265% , 67% and 18%, respectively, in terms of average performance/area efficiency)., Comment: To appear on ASPLOS 2023

Published
2023

2. Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators

Author

Garg, Raveesh, Qin, Eric, Muñoz-Martínez, Francisco, Guirado, Robert, Jain, Akshay, Abadal, Sergi, Abellán, José L., Acacio, Manuel E., Alarcón, Eduard, Rajamanickam, Sivasankaran, and Krishna, Tushar

Subjects
Computer Science - Distributed, Parallel, and Cluster Computing, Computer Science - Hardware Architecture
Abstract

Graph Neural Networks (GNNs) have garnered a lot of recent interest because of their success in learning representations from graph-structured data across several critical applications in cloud and HPC. Owing to their unique compute and memory characteristics that come from an interplay between dense and sparse phases of computations, the emergence of reconfigurable dataflow (aka spatial) accelerators offers promise for acceleration by mapping optimized dataflows (i.e., computation order and parallelism) for both phases. The goal of this work is to characterize and understand the design-space of dataflow choices for running GNNs on spatial accelerators in order for mappers or design-space exploration tools to optimize the dataflow based on the workload. Specifically, we propose a taxonomy to describe all possible choices for mapping the dense and sparse phases of GNN inference, spatially and temporally over a spatial accelerator, capturing both the intra-phase dataflow and the inter-phase (pipelined) dataflow. Using this taxonomy, we do deep-dives into the cost and benefits of several dataflows and perform case studies on implications of hardware parameters for dataflows and value of flexibility to support pipelined execution., Comment: Accepted for publication at the 36th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2022)

Published
2021

3. STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators

Author

Muñoz-Martínez, Francisco, Abellán, José L., Acacio, Manuel E., and Krishna, Tushar

Subjects
Electrical Engineering and Systems Science - Signal Processing, Computer Science - Hardware Architecture, Computer Science - Machine Learning
Abstract

The design of specialized architectures for accelerating the inference procedure of Deep Neural Networks (DNNs) is a booming area of research nowadays. First-generation rigid proposals have been rapidly replaced by more advanced flexible accelerator architectures able to efficiently support a variety of layer types and dimensions. As the complexity of the designs grows, it is more and more appealing for researchers to have cycle-accurate simulation tools at their disposal to allow for fast and accurate design-space exploration, and rapid quantification of the efficacy of architectural enhancements during the early stages of a design. To this end, we present STONNE (Simulation TOol of Neural Network Engines), a cycle-accurate, highly-modular and highly-extensible simulation framework that enables end-to-end evaluation of flexible accelerator architectures running complete contemporary DNN models. We use STONNE to model the recently proposed MAERI architecture and show how it can closely approach the performance results of the publicly available BSV-coded MAERI implementation. Then, we conduct a comprehensive evaluation and demonstrate that the folding strategy implemented for MAERI results in very low compute unit utilization (25% on average across 5 DNN models) which in the end translates into poor performance.

Published
2020

6. CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators

Author

Muñoz-Martínez, Francisco, Abellán, José L., Acacio, Manuel E., Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Schwardmann, Ulrich, editor, Boehme, Christian, editor, B. Heras, Dora, editor, Cardellini, Valeria, editor, Jeannot, Emmanuel, editor, Salis, Antonio, editor, Schifanella, Claudio, editor, Manumachu, Ravi Reddy, editor, Schwamborn, Dieter, editor, Ricci, Laura, editor, Sangyoon, Oh, editor, Gruber, Thomas, editor, Antonelli, Laura, editor, and Scott, Stephen L., editor

Published
2020
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11. Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence

Author

Fernández-Pascual, Ricardo, Ros, Alberto, Acacio, Manuel E., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Hannig, Frank, editor, Cardoso, João M. P., editor, Pionteck, Thilo, editor, Fey, Dietmar, editor, Schröder-Preikschat, Wolfgang, editor, and Teich, Jürgen, editor

Published
2016
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15. Speculative inter-thread store-to-load forwarding in SMT architectures

Author

Feliu, Josue, Ros, Alberto, Acacio, Manuel E., Kaxiras, Stefanos, Feliu, Josue, Ros, Alberto, Acacio, Manuel E., and Kaxiras, Stefanos

Abstract

Applications running on out-of-order cores have benefited for decades of store-to-load forwarding which accelerates communication of store values to loads of the same thread. Despite threads running on a simultaneous multithreading (SMT) core could also access the load queues (LQ) and store queues (SQ) / store buffers (SB) of other threads to allow inter-thread store-to-load forwarding, we have skipped exploiting it because if we allow communication of different SMT threads via their LQs and SQs/SBs, write atomicity may be violated with respect to the outside world beyond the acceptable model of read -own-write-early multiple-copy atomicity (rMCA).In our prior work, we leveraged this idea to propose inter-thread store-to-load forwarding (ITSLF). ITLSF accelerates synchronization and communication of threads running in a simultaneous multi-threading processor by allowing stores in the store-queue of a thread to forward data to loads of another thread running in the same core without violating rMCA.In this work, we extend the original ITSLF mechanism to allow inter-thread forwarding from speculative stores (Spec-ITSLF). Spec-ITSLF allows forwarding store values to other threads earlier, which further accelerates synchronization. Spec-ITSLF outperforms a baseline SMT core by 15%, which is 2% better on average (and up to 5% for the TATP workload) than the original ITSLF mechanism. More importantly, Spec-ITSLF is on par with the original ITSLF mechanism regarding storage overhead but does not need to keep track of the speculative state of stores, which was an important source of overhead and complexity in the original mechanism. (c) 2022 The Author(s). Published by Elsevier Inc. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

Published
2023
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19. Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs

Author

Fernández-Pascual, Ricardo, Ros, Alberto, Acacio, Manuel E., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Lopes, Luís, editor, Žilinskas, Julius, editor, Costan, Alexandru, editor, Cascella, Roberto G., editor, Kecskemeti, Gabor, editor, Jeannot, Emmanuel, editor, Cannataro, Mario, editor, Ricci, Laura, editor, Benkner, Siegfried, editor, Petit, Salvador, editor, Scarano, Vittorio, editor, Gracia, José, editor, Hunold, Sascha, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, Lengauer, Christian, editor, Carretero, Jesús, editor, Breitbart, Jens, editor, and Alexander, Michael, editor

Published
2014
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20. Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support

Author

Lodde, Mario, Flich, José, Acacio, Manuel E., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Wolf, Felix, editor, Mohr, Bernd, editor, and an Mey, Dieter, editor

Published
2013
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21. Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory

Author

Gaona, Epifanio, Abellán, José L., Acacio, Manuel E., Fernández, Juan, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Kubátová, Hana, editor, Hochberger, Christian, editor, Daněk, Martin, editor, and Sick, Bernhard, editor

Published
2013
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22. Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols

Author

Lodde, Mario, Flich, Jose, Acacio, Manuel E., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Kaklamanis, Christos, editor, Papatheodorou, Theodore, editor, and Spirakis, Paul G., editor

Published
2012
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23. Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs

Author

Ros, Alberto, Acacio, Manuel E., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Guarracino, Mario R., editor, Vivien, Frédéric, editor, Träff, Jesper Larsson, editor, Cannatoro, Mario, editor, Danelutto, Marco, editor, Hast, Anders, editor, Perla, Francesca, editor, Knüpfer, Andreas, editor, Di Martino, Beniamino, editor, and Alexander, Michael, editor

Published
2011
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24. Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades

Author

Gaona, Epifanio, Fernández, Juan, Acacio, Manuel E., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Sips, Henk, editor, Epema, Dick, editor, and Lin, Hai-Xiang, editor

Published
2009
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25. Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs

Author

Ros, Alberto, Acacio, Manuel E., García, José M., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Dou, Yong, editor, Gruber, Ralf, editor, and Joller, Josef M., editor

Published
2009
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26. Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades

Author

Abellán, José L., Fernández, Juan, Acacio, Manuel E., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bubak, Marian, editor, van Albada, Geert Dick, editor, Dongarra, Jack, editor, and Sloot, Peter M. A., editor

Published
2008
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27. Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs

Author

Fernández-Pascual, Ricardo, García, José M., Acacio, Manuel E., Duato, José, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Sadayappan, Ponnuswamy, editor, Parashar, Manish, editor, Badrinath, Ramamurthy, editor, and Prasanna, Viktor K., editor

Published
2008
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28. Directory-Based Conflict Detection in Hardware Transactional Memory

Author

Titos, Rubén, Acacio, Manuel E., García, José M., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Sadayappan, Ponnuswamy, editor, Parashar, Manish, editor, Badrinath, Ramamurthy, editor, and Prasanna, Viktor K., editor

Published
2008
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29. Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors

Author

Ros, Alberto, Acacio, Manuel E., García, José M., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Aluru, Srinivas, editor, Parashar, Manish, editor, Badrinath, Ramamurthy, editor, and Prasanna, Viktor K., editor

Published
2007
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30. Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network

Author

Flores, Antonio, Aragón, Juan L., Acacio, Manuel E., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Aluru, Srinivas, editor, Parashar, Manish, editor, Badrinath, Ramamurthy, editor, and Prasanna, Viktor K., editor

Published
2007
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31. Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture

Author

Villa, Francisco J., Acacio, Manuel E., García, José M., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Yang, Laurence T., editor, Rana, Omer F., editor, Di Martino, Beniamino, editor, and Dongarra, Jack, editor

Published
2005
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32. A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors

Author

Ros, Alberto, Acacio, Manuel E., García, José M., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Cunha, José C., editor, and Medeiros, Pedro D., editor

Published
2005
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33. On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs

Author

Villa, Francisco J., Acacio, Manuel E., García, José M., Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Bubak, Marian, editor, van Albada, Geert Dick, editor, Sloot, Peter M. A., editor, and Dongarra, Jack, editor

Published
2004
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