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2,746 results on '"Abstraction layer"'

1. DeepRS: A Library of Recommendation Algorithms Based on Deep Learning

Author

Hongwei Tao, Xiaoxu Niu, Lianyou Fu, Shuze Yuan, Xiao Wang, Jiaxue Zhang, and Yinghui Hu

Subjects
Recommendation algorithm library, Deep learning, Tensorflow, Abstraction layer, Electronic computers. Computer science, QA75.5-76.95
Abstract

Abstract In recent years, recommendation systems have become more complex with increasing research on user preferences. Recommendation algorithm based on deep learning has attracted a lot of attention from researchers in academia and industry, and many new algorithm models are proposed every year. Researchers often need to implement the proposed model to compare the results, which is a great challenge. Even if some papers provide source code, there are a variety of programming languages or deep learning frameworks, and it is not easy to compare the results in the different frameworks. In view of the lack of easily extensible deep learning-based recommendation algorithm libraries, based on the common analysis of deep learning algorithms in attention factorization machine (AFM), neural factorization machine (NFM), deep factorization machine (DeepFM) and deep cross-network (DCN), a recommendation algorithm library based on deep learning (DeepRS for short) is designed and implemented. It consists of three levels: framework level, abstract level and algorithm level. The framework level adopts the Tensorflow open source framework, which provides interfaces, such as automatic differentiation, tensor computing, GPU computing, and numerical optimization algorithms. The abstraction level uses the interface of the framework level to realize the embedding layer (EL), the full connection layer (FCL), the multi-layer perceptron layer (MLPL), the prediction layer (PL), the factorization machine layer (FML), the attention network layer (ANL), the cross-layer (CL) and the cross-network layer (CNL). The algorithm level implements the deep learning-based recommendation algorithms, such as AFM, NFM, DeepFM and DCN, on the basis of the abstraction level and the framework level. Experiments show that the proposed algorithm library has good scalability, ease of use and correctness.

Published
2022
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2. Abstracting Data in Distributed Ledger Systems for Higher Level Analytics and Visualizations.

Author

Vinceslas, Leny, Dogan, Safak, Sundareshwar, Srikumar, and Kondoz, Ahmet M.

Subjects
BLOCKCHAINS, DATA analytics, VISUALIZATION, USER interfaces, SYSTEMS development, DATA visualization
Abstract

By design, distributed ledger technologies persist low-level data, which makes conducting complex business analysis of the recorded operations challenging. Existing blockchain visualization and analytics tools such as block explorers tend to rely on this low-level data and complex interfacing to provide an enriched level of analytics. The ability to derive richer analytics could be improved through the availability of a higher level abstraction of the data. This article proposes an abstraction layer architecture that enables the design of high-level analytics of distributed ledger systems and the decentralized applications that run on top. Based on the analysis of existing initiatives and identification of the relevant user requirements, this work aims to establish key insights and specifications to improve the auditability and intuitiveness of distributed ledger systems by leveraging the development of future user interfaces. To illustrate the benefits offered by the proposed abstraction layer architecture, a regulated sector use case is explored. [ABSTRACT FROM AUTHOR]

Published
2023
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5. Abstracting Data in Distributed Ledger Systems for Higher Level Analytics and Visualizations

Author

Leny Vinceslas, Safak Dogan, Srikumar Sundareshwar, and Ahmet M. Kondoz

Subjects
distributed ledger technology (DLT), blockchain, block explorer, hyperledger fabric, abstraction layer, information visualization, Information technology, T58.5-58.64
Abstract

By design, distributed ledger technologies persist low-level data, which makes conducting complex business analysis of the recorded operations challenging. Existing blockchain visualization and analytics tools such as block explorers tend to rely on this low-level data and complex interfacing to provide an enriched level of analytics. The ability to derive richer analytics could be improved through the availability of a higher level abstraction of the data. This article proposes an abstraction layer architecture that enables the design of high-level analytics of distributed ledger systems and the decentralized applications that run on top. Based on the analysis of existing initiatives and identification of the relevant user requirements, this work aims to establish key insights and specifications to improve the auditability and intuitiveness of distributed ledger systems by leveraging the development of future user interfaces. To illustrate the benefits offered by the proposed abstraction layer architecture, a regulated sector use case is explored.

Published
2023
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6. The Design and Implementation of OpenMP 4.5 and OpenACC Backends for the RAJA C++ Performance Portability Layer

Author

Killian, William, Scogland, Tom, Kunen, Adam, Cavazos, John, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Chandrasekaran, Sunita, editor, and Juckeland, Guido, editor

Published
2018
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8. Abstraction Layer For Standardizing APIs of Task-Based Engines.

Author

Alomairy, Rabab, Ltaief, Hatem, Abduljabbar, Mustafa, and Keyes, David

Subjects
*DYNAMICAL systems, *ENGINES, *APPLICATION program interfaces, *TASK analysis, *COMPILERS (Computer programs)
Abstract

We introduce AL4SAN, a lightweight library for abstracting the APIs of task-based runtime engines. AL4SAN unifies the expression of tasks and their data dependencies. It supports various dynamic runtime systems relying on compiler technology and user-defined APIs. It enables a single application to employ different runtimes and their respective scheduling components, while providing user-obliviousness to the underlying hardware configurations. AL4SAN exposes common front-end APIs and connects to different back-end runtimes. Experiments on performance and overhead assessments are reported on various shared- and distributed-memory systems, possibly equipped with hardware accelerators. A range of workloads, from compute-bound to memory-bound regimes, are employed as proxies for current scientific applications. The low overhead (less than 10 percent) achieved using a variety of workloads enables AL4SAN to be deployed for fast development of task-based numerical algorithms. More interestingly, AL4SAN enables runtime interoperability by switching runtimes at runtime. Blending runtime systems permits to achieve a twofold speedup on a task-based generalized symmetric eigenvalue solver, relative to state-of-the-art implementations. The ultimate goal of AL4SAN is not to create a new runtime, but to strengthen co-design of existing runtimes/applications, while facilitating user productivity and code portability. The code of AL4SAN is freely available at https://github.com/ecrc/al4san , with extensions in progress. [ABSTRACT FROM AUTHOR]

Published
2020
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9. Conclusions and Future Work

Author

Goossens, Sven, Chandrasekar, Karthik, Akesson, Benny, Goossens, Kees, Dutt, Nikil D., Series editor, Martin, Grant, Series editor, Marwedel, Peter, Series editor, Goossens, Sven, Chandrasekar, Karthik, Akesson, Benny, and Goossens, Kees

Published
2016
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10. Sound and Precise Cross-Layer Data Flow Tracking

Author

Lovat, Enrico, Ochoa, Martín, Pretschner, Alexander, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Caballero, Juan, editor, Bodden, Eric, editor, and Athanasopoulos, Elias, editor

Published
2016
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12. HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction

Author

Anuj Pathania, Lothar Thiele, Tulika Mitra, Zhaoying Li, Dhananiaya Wijerathne, and Parallel Computing Systems (IvI, FNWI)

Subjects
Computer science, Reconfigurability, Systolic array, Parallel computing, computer.software_genre, Computer Graphics and Computer-Aided Design, Abstraction layer, Kernel (linear algebra), Scalability, Hardware acceleration, Compiler, Electrical and Electronic Engineering, computer, Software, Abstraction (linguistics)
Abstract

Coarse-Grained Reconfigurable Array (CGRA) has emerged as a promising hardware accelerator due to the excellent balance among reconfigurability, performance, and energy efficiency. The CGRA performance strongly depends on a high-quality compiler to map the application kernels on the architecture. Unfortunately, the state-of-the-art compilers fall short in generating high quality mapping within an acceptable compilation time, especially with increasing CGRA size. We propose HiMap - a fast and scalable CGRA mapping approach - that is also adept at producing close-to-optimal solutions for multi-dimensional kernels prevalent in existing and emerging application domains. The key strategy behind HiMap's efficiency and scalability is to exploit the regularity in the loop iteration dependencies by employing a virtual systolic array as an intermediate abstraction layer in a hierarchical mapping. Experimental results confirm that HiMap can generate application mappings that hit the performance envelope of the CGRA. HiMap offers 17.3x and 5x improvement in performance and energy efficiency of the mappings compared to the state-of-the-art. The compilation time of HiMap for near-optimal mappings is less than 15 minutes for 64x64 CGRA while existing approaches take days to generate inferior mappings.

Published
2022
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14. The Open-Source LearnLib : A Framework for Active Automata Learning

Author

Isberner, Malte, Howar, Falk, Steffen, Bernhard, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Kroening, Daniel, editor, and Păsăreanu, Corina S., editor

Published
2015
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19. Fair and Comprehensive Benchmarking of Machine Learning Processing Chips

Author

Marian Verhelst, Geoffrey W. Burr, Boris Murmann, Rangharajan Venkatesan, and SukHwan Lim

Subjects
Class (computer programming), Artificial neural network, Computer science, business.industry, Best practice, Inference, Benchmarking, Machine learning, computer.software_genre, Abstraction layer, Hardware and Architecture, Artificial intelligence, Electrical and Electronic Engineering, Architecture, business, computer, Software, Abstraction (linguistics)
Abstract

With the rise of custom silicon chips for AI acceleration, fair and comprehensive benchmarking of hardware innovations has become increasingly important. While benchmarking at the application- and system-level provides the most complete picture of trade-offs across multiple design dimensions, this can hide the impact of innovations at lower levels. Moreover, system-level benchmarking is not always feasible, especially for academic and industrial research chips. Benchmarking machine learning chips at lower abstraction levels is therefore still useful and common practice, making use of architecture- or circuit-level metrics. Yet the selection of good metrics and benchmarking conditions is critical, as these strongly influence the correlation between the observed performance benefits and the final system-level benefits. This paper provides an overview of benchmarking strategies at different abstraction levels, and discusses best practices and pitfalls to-be-avoided. We then propose to combine this diligent benchmarking at the appropriate individual abstraction level, with careful extrapolation to the system-level to also gauge impact at that topmost level. While the paper focuses on neural network inference workloads, many guidelines discussed here are applicable to the broader class of machine learning chips.

Published
2022
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21. Data Protection in a Cloud-Enabled Smart Grid

Author

Fromm, Alexander, Kelbert, Florian, Pretschner, Alexander, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Cuellar, Jorge, editor

Published
2013
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25. Model Based Architecting and Construction of Embedded Systems (ACES-MB 2011)

Author

Van Baelen, Stefan, Gérard, Sébastien, Ober, Ileana, Weigert, Thomas, Espinoza, Huascar, Ober, Iulian, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, and Kienzle, Jörg, editor

Published
2012
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26. Outlook

Author

Broy, Manfred, Pohl, Klaus, editor, Hönninger, Harald, editor, Achatz, Reinhold, editor, and Broy, Manfred, editor

Published
2012
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27. Logical Viewpoint

Author

Eder, Sebastian, Mund, Jakob, Vogelsang, Andreas, Pohl, Klaus, editor, Hönninger, Harald, editor, Achatz, Reinhold, editor, and Broy, Manfred, editor

Published
2012
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29. QRev: migrating quantum code towards hybrid information systems

Author

Luis Jiménez-Navajas, Mario Piattini, and Ricardo Pérez-Castillo

Subjects
Reverse engineering, Computer science, business.industry, computer.software_genre, Abstraction layer, Quantum technology, Software, Scalability, Information system, Safety, Risk, Reliability and Quality, Software engineering, business, computer, Knowledge Discovery Metamodel, Quantum computer
Abstract

Quantum computing is now a reality, and its incomparable computational power has led companies to show a great interest in being able to work with quantum software in order to support part of their current and future business operations. However, the quantum computing paradigm differs significantly from its classical counterparts, which has brought about the need to revolutionise how the future software is designed, built, and operated in order to work with quantum computers. Since companies cannot discard all their current (and probably mission-critical) information systems, they must adapt their classical information systems to new specific quantum applications, thus evolving towards hybrid information systems. Unfortunately, there are no specific methods with which to deal with this challenge. We believe that reengineering, and more specifically, software modernisation using model-driven engineering principles, could be useful as regard migrating classical systems and existing quantum programs towards hybrid information systems. This paper, therefore, presents QRev, a reverse engineering tool that analyses quantum programs developed in Q# in order to identify its components and interrelationships, and then generates abstract models that can be used in software modernisation processes. The platform-independent models are generated according to the Knowledge Discovery Metamodel (KDM) standard. QRev is validated in a case study involving five quantum programs in order to demonstrate its effectiveness and scalability. The main implication of the study is that QRev can be used in order to attain KDM models, which can subsequently be employed to restructure or add new quantum functionality at a higher abstraction level, i.e. independently of the specific quantum technology.

Published
2021
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30. A learning experience toward the understanding of abstraction-level interactions in parallel applications

Author

Darío Suárez-Gracia, Alejandro Valero, Pablo Ibáñez, Emanuel A. Georgescu, Adolfo Muñoz, Rubén Gran-Tejero, Pedro Álvarez, Joaquín Ezpeleta, and Luis M. Ramos

Subjects
Atomicity, Computer Networks and Communications, Computer science, business.industry, Concurrency, 020206 networking & telecommunications, 02 engineering and technology, Theoretical Computer Science, Abstraction layer, Consistency (database systems), Artificial Intelligence, Hardware and Architecture, ComputingMilieux_COMPUTERSANDEDUCATION, 0202 electrical engineering, electronic engineering, information engineering, Parallelism (grammar), 020201 artificial intelligence & image processing, Isolation (database systems), Software engineering, business, Curriculum, Software, Abstraction (linguistics)
Abstract

In the curriculum of a Computer Engineering program, concepts like parallelism, concurrency, consistency, or atomicity are usually addressed in separate courses due to their thoroughness and extension. Isolating such concepts in courses helps students not only to focus on specific aspects, but also to experience the reality of working with modern computer systems, where those concepts are often detached in different abstraction levels. However, due to such an isolation, it exists a risk of inducing to the students an absence of interactions between these concepts, and, by extension, between the different abstraction levels of a system. This paper proposes a learning experience showcasing the interactions between abstraction levels addressed in laboratory sessions of different courses. The driving example is a parallel ray tracer. In the different courses, students implement and assemble components of this application from the algorithmic level of the tracer to the assembly instructions required to guarantee atomicity. Each lab focuses on a single abstraction level, but shows students the interactions with the rest of the levels. Technical results and student learning outcomes through the analysis of surveys validate the proposed experience and confirm the students learning improvement with a more integrated view of the system.

Published
2021
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32. The Science of Conceptual Modelling

Author

Thalheim, Bernhard, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Hameurlain, Abdelkader, editor, Liddle, Stephen W., editor, Schewe, Klaus-Dieter, editor, and Zhou, Xiaofang, editor

Published
2011
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34. Cloud Basics

Author

Baun, Christian, Kunze, Marcel, Nimis, Jens, Tai, Stefan, Baun, Christian, Kunze, Marcel, Nimis, Jens, and Tai, Stefan

Published
2011
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36. Modelling Probabilistic Inference Networks and Classification in Probabilistic Datalog

Author

Martinez-Alvarez, Miguel, Roelleke, Thomas, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Goebel, Randy, editor, Siekmann, Jörg, editor, Wahlster, Wolfgang, editor, Deshpande, Amol, editor, and Hunter, Anthony, editor

Published
2010
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37. SyLaGen – An Extendable Tool Environment for Generating Load

Author

Striewe, Michael, Balz, Moritz, Goedicke, Michael, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Müller-Clostermann, Bruno, editor, Echtle, Klaus, editor, and Rathgeb, Erwin P., editor

Published
2010
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38. A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems

Author

Bellasi, Patrick, Fornaciari, William, Siorpaes, David, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Müller-Schloer, Christian, editor, Karl, Wolfgang, editor, and Yehia, Sami, editor

Published
2010
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40. Working with Databases

Author

Tomlinson, Todd, VanDyk, John K., Tomlinson, Todd, VanDyk, John K., Lowman, Michelle, editor, Anglin, Steve, editor, Beckner, Mark, editor, Buckingham, Ewan, editor, Cornell, Gary, editor, Gennick, Jonathan, editor, Hassell, Jonathan, editor, Moodie, Matthew, editor, Parkes, Duncan, editor, Pepper, Jeffrey, editor, Pohlmann, Frank, editor, Pundick, Douglas, editor, Renow-Clarke, Ben, editor, Shakeshaft, Dominic, editor, Wade, Matt, editor, Welsh, Tom, editor, Castro, Anita, editor, and Fugate, Mary Ann, editor

Published
2010
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41. Toward Compositional Verification of Interruptible OS Kernels and Device Drivers.

Author

Chen, Hao, Wu, Xiongnan, Shao, Zhong, Lockerman, Joshua, and Gu, Ronghui

Abstract

An operating system (OS) kernel forms the lowest level of any system software stack. The correctness of the OS kernel is the basis for the correctness of the entire system. Recent efforts have demonstrated the feasibility of building formally verified general-purpose kernels, but it is unclear how to extend their work to verify the functional correctness of device drivers, due to the non-local effects of interrupts. In this paper, we present a novel compositional framework for building certified interruptible OS kernels with device drivers. We provide a general device model that can be instantiated with various hardware devices, and a realistic formal model of interrupts, which can be used to reason about interruptible code. We have realized this framework in the Coq proof assistant. To demonstrate the effectiveness of our new approach, we have successfully extended an existing verified non-interruptible kernel with our framework and turned it into an interruptible kernel with verified device drivers. To the best of our knowledge, this is the first verified interruptible operating system with device drivers. [ABSTRACT FROM AUTHOR]

Published
2018
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43. Provider-Independent Use of the Cloud

Author

Harmer, Terence, Wright, Peter, Cunningham, Christina, Perrott, Ron, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Sips, Henk, editor, Epema, Dick, editor, and Lin, Hai-Xiang, editor

Published
2009
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45. g-Eclipse – A Contextualised Framework for Grid Users, Grid Resource Providers and Grid Application Developers

Author

Kornmayer, Harald, Stümpert, Mathias, Gjermundrød, Harald, Wolniewicz, Paweł, Hutchison, editor, Kanade, editor, Kittler, editor, Kleinberg, editor, Mattern, editor, Mitchell, editor, Naor, editor, Nierstrasz, editor, Pandu Rangan, editor, Steffen, editor, Sudan, editor, Terzopoulos, editor, Tygar, editor, Vardi, editor, Weikum, editor, Bubak, Marian, editor, van Albada, Geert Dick, editor, Dongarra, Jack, editor, and Sloot, Peter M. A., editor

Published
2008
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46. A Mechanized Program Verifier

Author

Moore, J. Strother, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Meyer, Bertrand, editor, and Woodcock, Jim, editor

Published
2008
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50. Online and transparent self-adaptation of stream parallel patterns

Author

Luiz Gustavo Fernandes, Marco Danelutto, Dalvan Griebler, Adriano Vogel, and Gabriele Mencagli

Subjects
Flexibility (engineering), Numerical Analysis, Computer science, Distributed computing, Self adaptation, Computer Science Applications, Theoretical Computer Science, Abstraction layer, Stream processing, Computational Mathematics, Computational Theory and Mathematics, Parallelism (grammar), Computer communication networks, Software
Abstract

Several real-world parallel applications are becoming more dynamic and long-running, demanding online (at run-time) adaptations. Stream processing is a representative scenario that computes data items arriving in real-time and where parallel executions are necessary. However, it is challenging for humans to monitor and manually self-optimize complex and long-running parallel executions continuously. Moreover, although high-level and structured parallel programming aims to facilitate parallelism, several issues still need to be addressed for improving the existing abstractions. In this paper, we extend self-adaptiveness for supporting autonomous and online changes of the parallel pattern compositions. Online self-adaptation is achieved with an online profiler that characterizes the applications, which is combined with a new self-adaptive strategy and a model for smooth transitions on reconfigurations. The solution provides a new abstraction layer that enables application programmers to define non-functional requirements instead of hand-tuning complex configurations. Hence, we contribute with additional abstractions and flexible self-adaptation for responsiveness at run-time. The proposed solution is evaluated with applications having different processing characteristics, workloads, and configurations. The results show that it is possible to provide additional abstractions, flexibility, and responsiveness while achieving performance comparable to the best static configuration executions.

Published
2021
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