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The applications regarding the Internet of Things (IoT) demand lightweight and robust cryptographic solutions to ensure authenticated encryption with associated data (AEAD). Also, the lightweight cryptographic solutions that provide data confidentiality, integrity, and authenticity in a single algorithm are critical. In this regard, the CAESAR and NIST lightweight cryptography (LWC) competitions were concluded in 2019 and recently in 2023, respectively, with Ascon selected as the new LWC standard. Ascon has been evaluated (in the literature) for various characteristics, including some limited efforts on field-programmable gate array (FPGA) devices. A comprehensive evaluation of Ascon’s hardware implementation is still needed. Therefore, this work presents a unified hardware implementation of two variants of Ascon, i.e., Ascon-128 and Ascon-128a, to investigate the performance of the AEAD operation on 7-series FPGA devices up to the post-place and route level. For AEAD computations in our work, an iterative design-level approach with a finite-state machine (FSM)-based dedicated controller is employed. The benchmarking results show that Ascon utilizes 1632, 1497, 1904, and 1756 look-up tables on Virtex, Kintex, Spartan, and Artix 7-series FPGA devices, respectively. The operating frequencies on these devices are 335, 331, 309, and 317 MHz, with power consumptions of 239, 236, 219, and 222 mW. Consequently, our evaluation of Ascon demonstrates higher performance in operating frequency on Kintex-7 FPGA.

We propose a hardware-optimized design that implements a Montgomery Elliptic-curve point multiplication Algorithm over $GF(2^{233})$ using Lopez-Dahab projective coordinates. Moreover, we propose a digit-parallel modular multiplier, which reduces clock cycles and improves throughput. Also, we provided how to use our proposed digit-parallel multiplier for post-quantum cryptography algorithms. In addition, we use the proposed digit-parallel multiplier with the square circuit to implement the Itoh-Tsujii inversion algorithm for modular inversion computation; this permits hardware resource minimization. An efficient finite-state machine controller is implemented for control functionalities. A figure of merit in throughput/area is defined for reasonable comparison to state-of-the-art. We provide implementation results after post-place-and-route on field-programmable gate array devices. On the Virtex-7 device, our design utilizes 3386 slices and requires 7218 clock cycles; it achieves a maximum frequency of 365 MHz and computes one point multiplication in $19.77\mu s$ . The total power consumption of our design is 2027 mW. The calculated values for throughput and figure of merit are 50.58Kbps and 14.93, respectively. Consequently, the implementation results and comparisons reveal our design’s suitability for applications requiring area and throughput-optimized cryptographic implementations.

This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on a field-programmable-gate-array (FPGA) platform with a block and key lengths of 32 and 64 bits. The critical features of our architecture include parallelism, pipelining, and a dedicated controller. Parallelism splits the digits of the key and data blocks into smaller segments. Then, we use each segmented key and data block in parallel for encryption and decryption computations. Splitting key and data blocks helps reduce the required clock cycles. A two-stage pipelining is used to shorten the critical path and to improve the clock frequency. A dedicated controller is implemented to provide control functionalities. For the performance evaluation of our design, we report implementation results for two different cases on Xilinx 7-series FPGA devices. For our case one, the proposed architecture can operate on 382, 379, and 388 MHz frequencies for Kintex-7, Virtex-7, and Artix-7 devices. On the same Kintex-7, Virtex-7, and Artix-7 devices, the utilized Slices are 49, 51, and 50. For one encryption and decryption computation, our design takes 16 clock cycles. The minimum power consumption is 172 mW on the Kintex-7 device. For the second case, we targeted the same circuit frequency of 50 MHz for synthesis on Kintex-7, Virtex-7, and Artix-7 devices. With minimum hardware resource utilization (51 Slices), the least consumed power of 13.203 mW is obtained for the Kintex-7 device. For proof-of-concept, the proposed SIMECK design is validated on the NEXYS 4 FPGA with the Artix-7 device. Consequently, the implementation results reveal that the proposed architecture is suitable for many resource-constrained cryptographic applications.