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Unlike conventional analog-to-digital converter (ADC), phase-domain ADC (Ph-ADC) is more power efficient for the implementation of fully digital Gaussian frequency shift keying (GFSK) demodulator in bluetooth low energy (BLE). Besides, Ph-ADC based demodulator is flexible to pair with low-IF and zero-IF receiver, opposed to limiter based demodulator that work with low-IF receiver only. Yet, currently reported Ph-ADC based demodulator lack of preamble detection for BLE which will be used as symbol clock synchronization. In this work, a Ph-ADC based demodulator is proposed with the feature of preamble detection on BLE's packet. The detected preamble is used for symbol clock recovery and compensation of carrier frequency offset in a BLE packet. Besides, the proposed demodulator is flexible to demodulate IF or baseband signal by simply configuring a parameter value. Using MATLAB, minimum signal-to-noise Ratio (SNR) needed to demodulate BLE packet is estimated using Monte Carlo simulation with 99% confidence level. For hardware implementation, the proposed demodulator is implemented at RTL in Synopsys and its layout is generated using 0.18 μm CMOS technology. To understand the trade-off between power consumption, layout size and minimum SNR needed, the proposed Ph-ADC based demodulator is scaled to a different combination of 4-bit to 6-bit resolution and 2 MHz to 16 MHz sampling rate. Configuration with the best trade-off for the proposed Ph-ADC demodulator can achieve bit error rate (BER) of 0.1% at SNR of 12.5 dB and able to tolerate carrier frequency offset of ± 200 kHz while using only half the power needed by state of the art limiter based demodulator. [ABSTRACT FROM AUTHOR]

In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its exibility, faster development time and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Rooine model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches. [ABSTRACT FROM AUTHOR]