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Conventional convolutional neural networks (CNNs) present a high computational workload and memory access cost (CMC). Spectral domain CNNs (SpCNNs) offer a computationally efficient approach to compute CNN training and inference. This paper investigates CMC of SpCNNs and its contributing components analytically and then proposes a methodology to optimize CMC, under three strategies, to enhance inference performance. In this methodology, output feature map (OFM) size, OFM depth or both are progressively reduced under an accuracy constraint to compute performance-optimized CNN inference. Before conducting training or testing, it can provide designers guidelines and preliminary insights regarding techniques for optimum performance, least degradation in accuracy and a balanced performance-accuracy trade-off. This methodology was evaluated on MNIST and Fashion MNIST datasets using LeNet-5 and AlexNet architectures. When compared to state-of-the-art SpCNN models, LeNet-5 achieves up to 4.2× (batch inference) and 4.1× (single-image inference) higher throughputs and 10.5× (batch inference) and 4.2× (single-image inference) greater energy efficiency at a maximum loss of 3% in test accuracy. When compared to the baseline model used in this study, AlexNet delivers 11.6× (batch inference) and 5× (single-image inference) increased throughput and 25× (batch inference) and 8.8× (single-image inference) more energy-efficient inference with just 4.4% reduction in accuracy.

Nowadays, 5G is playing a significant role in the efficiency of network security and creating more and faster channels for communication. 5G is evolving industries such as healthcare, education, marketing, transportation, and V2X (Vehicle-to-everything). In addition, 5G considers a new radio access technology that is adding new applications like the Internet of Things (IoT), Augmented Reality, Virtual Reality, connected cars, connected people-to-people, smart city, connected homes that are considered using higher bandwidth and low latency. Mainly, this paper is focusing on security challenges faced by the Vehicular ad-hoc network (VANET). VANET faces threats in three different fields; security, safety, and infotainment, which further have numerous attacks. More precisely, this research conducted an in-depth study and proposed a VANET trust model. Therefore the proposed model deals specifically with the “location closeness” parameter. Moreover, the trust model integrated with 5G cloud to support greater coverage, effective network density with respect to network infrastructure and IoT as well. Therefore, in this article, an effort has been put forward to implement the model using case studies to validate the trust model based on the “location closeness” parameter. The results proved the valid implementation of the model by identifying the trusted communication between the vehicles.

Future many-core systems need to address the dark silicon problem, where some cores would be turned off to control the chip’s thermal and power density, which effectively limits the performance gain from having a large number of processing cores. Task migration technique has been previously proposed to improve many-core system performance by moving tasks between active and dark cores. As task migration imposes system performance overhead due to the large wake-up latency of the dark cores, this paper proposes a prediction-based early wake-up (PEW) to reduce the dark cores’ wake-up latency during task migration. A window-based online ridge regression (RR) is used as the prediction model. The prediction model uses the past window’s thermal, power, and core status (i.e., active or dark) to predict the future core temperatures at run-time. If task migration is predicted in the next control period, the proposed PEW puts the dark cores in a power state with low wake-up latency. Thus, the proposed PEW reduces the time for the dark cores to start executing the tasks. The comparison results show that our proposed PEW reduces the completion time by up to 7.9% and 4.1% compared to non-early wake-up (NoEW) and a fixed threshold wake-up (FEW), respectively. It also shows that the proposed PEW increases the MIPS/Watt by up to 5.5% and 2.3% over NoEW and FEW, respectively. These results show that the proposed PEW improves the many-core system’s overall performance in terms of reducing dark cores’ wake-up latency and increasing the number of executed instructions per Watt.

The Internet of things (IoT) and advancements of wireless technology have evolved intelligent transport systems to integrate billion of smart objects ready to connect to the Internet. The modern era of the Internet of things (IoT) has brought significant development in vehicular ad hoc networks (VANETs) which transformed the conventional VANET into the Internet of Vehicle (IoV) to improve road safety and diminished road congestion. However, security threats are increasing due to dependency on infrastructure, computing, dynamic nature, and control technologies of VANET. The security threats of VANETs could be addressed comprehensively by increasing trustworthiness on the message received and transmitting node. Conversely, the presence of dishonest vehicles, for instance, Man in the Middle (MiTM) attackers, in the network sharing malicious content could be posed as a severe threat to VANET. Thus, increasing trustworthiness among nodes can lead to increased authenticity, privacy, accuracy, security, and trusted information sharing in the VANET. In this paper, a lightweight trust model is proposed, presented model identifying dishonest nodes and revoking its credential in the MiTM attack scenario. Furthermore, addressing the privacy and security requirement, the pseudonym scheme is used. All nodes in the VANET established trust provided by initially RSU, which is a trusted source in the network. Extensive experiments are conducted based on a variety of network scenarios to evaluate the accuracy and performance of the presented lightweight trust model. In terms of recall, precision, and F-score, our presented model significantly outperformed compared to MARINE. The simulation results have validated that the proposed lightweight model realized a high trust level with 40% of MiTM attackers and in terms of F-score 95%, whereas the MARINE model has 90%, which leads to the model to attain high detection accuracy.

Tongue diagnosis is known as one of the effective and yet noninvasive techniques to evaluate patient’s health condition in traditional oriental medicine such as traditional Chinese medicine and traditional Korean medicine. However, due to ambiguity, practitioners may have different interpretation on the tongue colour, body shape and texture. Thus, research of automatic tongue diagnosis system is needed for aiding practitioners in recognizing the features for tongue diagnosis. In this paper, a tongue diagnosis system based on Convolution Neural Network (CNN) for classifying tongue colours is proposed. The system extracts all relevant information (i.e., features) from three-dimensional digital tongue image and classifies the image into one of the colours (i.e. red or pink). Several pre-processing and data augmentation methods have been carried out and evaluated, which include salt-and-pepper noises, rotations and flips. The proposed system achieves accuracy of up to 88.98% from 5-fold cross validation. Compared to the reported baseline Support Vector Machine (SVM) method, the proposed method using CNN results in roughly 30% improvement in recognition accuracy.

Recent researches have shown that spectral representation provides a significant speed-up in the massive computation workload of convolution operations in the inference (feed-forward) algorithm of Convolutional Neural Networks (CNNs). This approach results in reducing the computational complexity of the classification task, which makes spectral-based CNN suitable for implementation on embedded platform that typically has constrained resources. However, a major challenge in this approach is that the mathematical formulation of a nonlinear activation function in spectral (frequency) domain is currently not available; hence, computation of the activation functions in each layer has to be performed in the spatial domain. This results in several spatial-frequency domain switchings that are computationally very costly, and as such, it would be advantageous to strictly stay in the frequency domain. Hence, in this work, a novel Spectral Rectified Linear Unit (SReLU) for the activation function is proposed, that makes it possible for the computations to remain in the frequency domain, and therefore avoids the multiple compute-intensive domain transformations. To further optimize the classification speed of the network, an efficient spectral-based CNN model is presented that uses only the lower frequency components by way of fusing the convolutional and sub-sampling layers. Additionally, we provide and utilize a frequency domain equivalent of the conventional batch normalization layer that results in improving the accuracy of the network. Experimental results indicate that the proposed spectral-based CNN model achieves up to 17.02 × and 3.45 × faster classification speed (without considerable accuracy loss) on AT&T face recognition and MNIST digit/fashion classification datasets, respectively, as compared to the equivalent models in the spatial domain, hence outperforming conventional approaches significantly.

Conventional Convolutional Neural Networks (CNNs), which are realized in spatial domain, exhibit high computational complexity. This results in high resource utilization and memory usage and makes them unsuitable for implementation in resource and energy-constrained embedded systems. A promising approach for low-complexity and high-speed solution is to apply CNN modeled in the spectral domain. One of the main challenges in this approach is the design of activation functions. Some of the proposed solutions perform activation functions in spatial domain, necessitating multiple and computationally expensive spatial-spectral domain switching. On the other hand, recent work on spectral activation functions resulted in very computationally intensive solutions. This paper proposes a complex-valued activation function for spectral domain CNNs that only transmits input values that have positive-valued real or imaginary component. This activation function is computationally inexpensive in both forward and backward propagation and provides sufficient nonlinearity that ensures high classification accuracy. We apply this complex-valued activation function in a LeNet-5 architecture and achieve an accuracy gain of up to 7% for MNIST and 6% for Fashion MNIST dataset, while providing up to 79% and 85% faster inference times, respectively, over state-of-the-art activation functions for spectral domain.

This paper presents the design of Bluetooth low energy (BLE) link layer controller implemented on application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) and general purpose processor (GPP). CAL dataflow programming has been used that allows automatic RTL and C code generation from high-level specification. The generated RTL code is synthesized and implemented on ASIC Silterra 180 nm process technology and Xilinx Artix FPGA, while the generated C code is implemented on Intel i7 GPP. High-level design space exploration has been made by performing actor merging techniques to obtain seven different architectures, which are compared in terms of performance, area, power and energy. The results show that energy improvements for ASIC, FPGA and GPP are 44.71%, 10.22% and 28.31%, respectively, through the design space exploration methodology.

A vehicular ad hoc network (VANETs) is transforming public transport into a safer wireless network, increasing its safety and efficiency. The VANET consists of several nodes which include RSU (Roadside Units), vehicles, traffic signals, and other wireless communication devices that are communicating sensitive information in a network. Nevertheless, security threats are increasing day by day because of dependency on network infrastructure, dynamic nature, and control technologies used in VANET. The security threats could be addressed widely by using machine learning and artificial intelligence on the road transport nodes. In this paper, a comparison of trust and cryptography was presented based on applications and security requirements of VANET.

This paper proposes a highly parallel two-dimensional (2D) HEVC transform hardware architecture, implemented in 32-nm VLSI technology. The design allows very high-resolution and frame-rate video coding by way of a very fast HEVC transform operations. It is based on a split architecture, where the individual transform type and size is separated into its own core, therefore enables pixel-level parallelism in the 2D parallel and folded structures. This work also implements the full specification of the HEVC transform for both the DCT and DST transforms, with performance, power, and area analyses for the two structures. Results show very significant speed up over existing unified architectures, with only a relatively modest increase in total gate count. The design is suitable for applications that require very high video resolution and frame rate.

Future many-core systems need to handle high power density and chip temperature effectively. Some cores in many-core systems need to be turned off or &lsquo, dark&rsquo, to manage chip power and thermal density. This phenomenon is also known as the dark silicon problem. This problem prevents many-core systems from utilizing and gaining improved performance from a large number of processing cores. This paper presents a dynamic thermal-aware performance optimization of dark silicon many-core systems (DTaPO) technique for optimizing dark silicon a many-core system performance under temperature constraint. The proposed technique utilizes both task migration and dynamic voltage frequency scaling (DVFS) for optimizing the performance of a many-core system while keeping system temperature in a safe operating limit. Task migration puts hot cores in low-power states and moves tasks to cooler dark cores to aggressively reduce chip temperature while maintaining high overall system performance. To reduce task migration overhead due to cold start, the source core (i.e., active core) keeps its L2 cache content during the initial migration phase. The destination core (i.e., dark core) can access it to reduce the impact of cold start misses. Moreover, the proposed technique limits tasks migration among cores that share the last level cache (LLC). In the case of major thermal violation and no cooler cores being available, DVFS is used to reduce the hot cores temperature gradually by reducing their frequency. Experimental results for different threshold temperatures show that DTaPO can keep the average system temperature below the thermal limit. Affirmatively, the execution time penalty is reduced by up to 18% compared with using only DVFS for all thermal thresholds. Moreover, the average peak temperature is reduced by up to 10.8∘C. In addition, the experimental results show that DTaPO improves the system&rsquo, s performance by up to 80% compared to optimal sprinting patterns (OSP) and reduces the temperature by up to 13.6∘C.

This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.

In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

Air traffic control nowadays mainly relies on radar based surveillance system and with the growth of air traffic, the problems of air transportation system is approaching its limit. The increase in the task of scheduling flights results in higher overall operation cost and pose higher rate of flight safety hazards. Thus, an upgrade from conventional air traffic management systems to the Next Generation Air Transportation (NextGen) System is required. The Automatic Dependent Surveillance Broadcast (ADS-B) modem is the key component of NextGen, which uses Global Navigation Satellite System (GNSS) to provide better accuracy of aircraft position. ADS-B continuously broadcasts information on altitude, position, identity, velocity, and other aircraft information to generate best picture for air traffic management. In this paper, the ADS-B modulator and demodulator have been developed using high-level RVC-CAL dataflow actor language, and automatically synthesized to C and Verilog/VHDL codes for hardware and software implementations. Results show that the performance of the proposed designs at high-level exceeds the minimum throughput requirement specified in the ADS-B standard by a factor of more than three.

Most of the cores in future many-core system-on-chip (MCSoC) will be off or ‘dark’ to manage the high power density and chip temperature of future chips. This problem is called dark silicon problem. This paper presents a task scheduling technique for optimizing the MCSoC performance under temperature constraint for dark silicon. The proposed technique uses both task migration and dynamic voltage frequency scaling (DVFS) to optimize many-core system performance, while the system temperature is kept in a safe operating range. Task migration improves system performance and balances heat distribution among cores by moving tasks from active cores to dark cores, while DVFS reduces core speed in case of thermal limit violation. Simulation results show that using both task migration and DVFS techniques reduces peak temperature by 12° C and keeps the average system temperature under the thermal limit, while the execution time increased by 16% compared with 50% when only DVFS technique is used.

Most existing works on application mapping for Multiprocessor System-on-Chip (MPSoC) use either simulation or analytical modeling to evaluate their mapping solutions. However, the use of these evaluation approaches is not as accurate as prototyping on a real MPSoC system. Rapid prototyping on a reconfigurable logic platform for design space exploration is also not trivial as tasks have to be developed ground-up. This paper proposes a development environment for fast NoC-based MPSoC application prototyping. A conversion method called CAL2NoC is proposed to convert a high-level dataflow model of real-world applications to multiple executable C codes (tasks). These application tasks are executed on emulated Network-on-Chip (NoC) based MPSoC platform and run-time performance traces are collected. CAL2NoC facilitates prototype-based design space exploration for real-world applications using emulated MPSoC platform for practical performance evaluation. As a proof-of-concept, JPEG encoder is profiled using the proposed method. It has been shown that the proposed method facilitates a rapid development of emulated MPSoC for accurate application mapping evaluation.

Optical Character Recognition (OCR) plays an important role in the retrieval of information from pixel-based images to searchable and machine-editable text formats. In old or poorly printed documents, printed characters are typically broken and blurred, making character recognition potentially far more complex. In this work, deep neural network using Inception V3 is used to train and perform OCR. The Inception V3 network is trained with 53,342 noisy character images, which were collected from receipts and newspapers. Our experimental results show that the proposed deep neural network achieved significantly better recognition accuracy on poor quality text images and resulted in an overall 21.5% reduction in error rate compared to existing OCRs.

In recent years, digital image forgery detection has become an active research area due to the advancement of photo editing software. This paper focuses on passive forgery detection on images tampered using copy move technique, better known as Copy Move Forgery Detection (CMFD). A CMFD technique consisting of oriented Features from Accelerated Segment Test and rotated Binary Robust Independent Elementary Features (Oriented FAST and rotated BRIEF) as the feature extraction method and 2 Nearest Neighbour (2NN) with Hierarchical Agglomerative Clustering (HAC) as the feature matching method is proposed. Evaluation of the proposed CMFD technique was performed on images that underwent various geometrical attacks. With the proposed technique, an overall accuracy rate of 84.33% and 82.79% are obtained for evaluation carried out with images from the MICC-F600 and MICC-F2000 databases. Forgery detection achieved True Positive Rate of more than 91% for tampered images with object translation, different degree of rotation and enlargement.

Face recognition in video surveillance is challenging as there is no control on the quality of the face image captured especially under uncooperative situations with head pose variation, occlusion, and low-quality image. These issues create large discrepancy between probe and gallery images which affects the performance of recognition. To overcome these issues, pose correction is proposed to narrow the difference between probe and gallery images and image enhancer to highlight face image details. Face representation is improved by creating an average face image to reduce the effect of non-facial details captured such as background, occlusion and noise. The proposed methods are tested on ChokePoint dataset and resulted in improved face recognition.

The high efficiency video compression standard (HEVC) is the latest video engineering marvel that is designed to launch video coding towards the domain of the 8K. This new standard with all the advanced video coding techniques built into it has an overload of computational complexities, which result to very high latency in the encoding process. Mode decision in this standard is one of the units that constitutes a significant fraction of the complexities. This work utilizes prediction residuals in the inter 2N × 2N part mode, in depths two and three, to prune down decisions over the four asymmetric motion partitions in each of these depths. Experimental results show that this algorithm offers a speedup of 72 % at best when linked with the mode decision scheme implemented in HM14 reference software.

Aortic stenosis (AS) is a condition where the calcification deposit within the heart leaflets narrows the valve and restricts the blood from flowing through it. This disease is progressive over time where it may affect the mechanism of the heart valve. To alleviate this condition without resorting to surgery, which runs the risk of mortality, a new method of treatment has been introduced: Transcatheter Aortic Valve Implantation (TAVI), in which imagery acquired from real-time echocardiogram (Echo) are needed to determine the exact size of aortic annulus. However, Echo data often suffers from speckle noise and low pixel resolution, which may result in incorrect sizing of the annulus. Our study therefore aims to perform an automated detection and measurement of aortic annulus size from Echo imagery. Two stages of algorithm are presented — image denoising and object detection. For the removal of speckle noise, Wavelet thresholding technique is applied. It consists of three sequential steps; applying linear discrete wavelet transform, thresholding wavelet coefficients and performing linear inverse wavelet transform. For the next stage of analysis, several morphological operations are used to perform object detection as well as valve sizing. The results showed that the automated system is able to produce more accurate sizing based on ground truth.

This paper presents the hardware design of a 2-dimensional Hadamard transform used the in the rate distortion optimization module in state-of-the-art HEVC video encoder. The transform is mainly used to quickly determine optimum block size for encoding part of a video frame. The proposed design is both scalable and fast by 1) implementing a unified architecture for sizes 4x4 to 32x32, and 2) pipelining and feed through control that allows high performance for all block sizes. The design starts with high-level algorithmic loop unrolling optimization to determine suitable level of parallelism. Based on this, a suitable hardware architecture is devised using transpose memory buffer as pipeline memory for maximum performance. The design is synthesized and implemented on Xilinx Kintex Ultrascale FPGA. Results indicate variable performance obtained for different block sizes and higher operating frequency compared to a similar work in literature. The proposed design can be used as a hardware accelerator to speed up the rate distortion optimization operation in HEVC video encoders.

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication among all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. This paper evaluates the energy and latency performance of a closed loop power management mechanism which enables transmitting power reconfiguration in WiNoC based on number of erroneous received packets. The scheme achieves significant energy savings with limited performance degradation and insignificant impact on throughput.

This paper presents a VLSI implementation of a high speed Kogge-Stone adder (KSA) using 0.18µm process technology. The adder is known to be one of the fastest adder architectures, and this is validated through a comparison with other adder architectures including the standard ripple carry adder and the carry look ahead adder. Furthermore, our KSA adder is also compared with a default optmized adder from the Artisan standard cell library. The adders are compared for bit widths of 8, 16, and 32. The adders are designed using Verilog and synthesized using both front-end and back-end tools, with complete validation and verification stages, including analysis for performance, power, and area. Results show that in terms of performance, KSA results in the lowest propagation delay with almost constant delay for all bit widths, with up to 70% less delay as compared to all other architectures. Area and power penalty is found to also increase by roughly 59%. In terms of energy usage, the KSA adder results in up to 64% less. In the case when speed and energy are critical, this fast and energy efficient KSA adder can be readily integrated into custom VLSI designs.

This paper presents two fast motion estimation algorithms based on the structure of the triangle and the pentagon, respectively, for HEVC/H.265 video coding. These new search patterns determine motion vectors faster than the two Tzsearch patterns - diamond and square - that are built into the motion estimation engine of the HEVC. The proposed algorithms are capable of achieving a faster run-time with negligible video quality loss and increase in bit rate. Experimental results show that, at their best, the triangle and pentagon algorithms can offer 63 % and 61.9 % speed-up in run-time respectively compared to the Tzsearch algorithms in HEVC reference software.

This paper presents a Very Large Scale Integrated (VLSI) design and implementation of a fixed-point 8x8 multiplierless Discrete Cosine Transform (DCT) using the ISO/IEC 23002-2 algorithm. The standard DCT algorithm, which is mainly used in image and video compression technology, consists of only adders, subtractors, and shifters, therefore making it efficient for hardware implementation. The VLSI implementation of the algorithm given in this paper further enhances the performance of the transform unit. Furthermore, circuit pipelining has been applied to the base design of the DCT, which significantly improves the performance by reducing the longest path in the non-pipeline design. The DCT has been implemented using semi-custom VLSI design methodology using the TSMC 0.13um process technology. Results show that our DCT designs can run up to around 1.7 Giga pixels/s, which is well above the timing required for real-time ultra-high definition 8K video.

This paper presents the design space exploration of the hardware-based inverse fixed-point integer transform for High Efficiency Video Coding (HEVC). The designs are specified at high-level using CAL dataflow language and automatically synthesized to HDL for FPGA implementation. Several parallel design alternatives are proposed with trade-off between performance and resource. The HEVC transform consists of several independent components from 4x4 to 32x32 discrete cosine transform and 4x4 discrete sine transform. This work explores the strategies to efficiently compute the transforms by applying data parallelism on the different components. Results show that an intermediate version of parallelism, whereby the 4x4 and 8x8 are merged together, and the 16x16 and 32x32 merged together gives the best trade-off between performance and resource. The results presented in this work also give an insight on how the HEVC transform can be designed efficiently in parallel for hardware implementation.

Signal processing designs are becoming increasingly complex with demands for more advanced algorithms. Designers are now seeking high-level tools and methodology to help manage complexity and increase productivity. Recently, CAL dataflow language has been specified which is capable of synthesizing dataflow description into RTL codes for hardware implementation, and based on several case studies, have shown promising results. However, no work has been done on global network analysis, which could increase the optimization space. In this paper, we introduce methodologies to analyze and optimize CAL programs by determining which actions should be parallelized, pipelined, or refactored for the highest throughput gain, and then providing tools and techniques to achieve this using minimum resource. As a case study on the RVC MPEG-4 SP Intra decoder for implementation on Virtex-5 FPGA, experimental results confirmed our analysis with throughput gain of up to 3.5x using relatively-minor additional slice compared to the reference design.

The specification of complex signal processing systems in hardware by means of HDL is no longer the appropriate way since they are known to be time consuming to design, and less flexible to extend features. Recently, Cal dataflow language was specified to increase productivity and scalability, with ability to synthesize to HDL for hardware implementation. In this paper, a new methodology to improve throughput of dataflow-based hardware designs is given by analyzing Cal programs using the profiling tool. As a case study, we analyzed the RVC MPEG-4 SP Intra decoder and found that the texture decoding part has the highest improvement factor. We have also introduced the luminance texture splitting technique as the improvement method by increasing the level of parallelism in the decoder. Experimental results of implementation on Virtex-5 FPGA confirmed our analysis with throughput increase of up to 50.5% with only 4.3% additional slice.