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49 results on '"AUDSLEY, NEIL C."'

1. Errata for Three Papers (2004-05) on Fixed-Priority Scheduling with Self-Suspensions

Author

Bletsas, Konstantinos, Audsley, Neil C., Huang, Wen-Hung, Chen, Jian-Jia, and Nelissen, Geoffrey

Subjects
real-time, scheduling, self-suspension, worst-case response time analysis, Technology, Electrical engineering. Electronics. Nuclear engineering, TK1-9971, Electronics, TK7800-8360
Abstract

The purpose of this article is to (i) highlight the flaws in three previously published works [Audsley, 2004a; Audsley, 2004b; Bletsas, 2005] on the worst-case response time analysis for tasks with self-suspensions and (ii) provide straightforward fixes for those flaws, hence rendering the analysis safe.

Published
2018
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2. Dynamic and Static Task Allocation for Hard Real-Time Video Stream Decoding on NoCs

Author

Mendis, Hashan R., Audsley, Neil C., and Indrusiak, Leandro Soares

Subjects
real-time multimedia, task mapping, network-on-chip, Technology, Electrical engineering. Electronics. Nuclear engineering, TK1-9971, Electronics, TK7800-8360
Abstract

Hard real-time (HRT) video systems require admission control decisions that rely on two factors. Firstly, schedulability analysis of the data-dependent, communicating tasks within the application need to be carried out in order to guarantee timing and predictability. Secondly, the allocation of the tasks to multi-core processing elements would generate different results in the schedulability analysis. Due to the conservative nature of the state-of-the-art schedulability analysis of tasks and message flows, and the unpredictability in the application, the system resources are often under-utilised. In this paper we propose two blocking-aware dynamic task allocation techniques that exploit application and platform characteristics, in order to increase the number of simultaneous, fully schedulable, video streams handled by the system. A novel, worst-case response time aware, search-based, static hard real-time task mapper is introduced to act as an upper-baseline to the proposed techniques. Further evaluations are carried out against existing heuristic-based dynamic mappers. Improvements to the admission rates and the system utilisation under a range of different workloads and platform sizes are explored.

Published
2017
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4. Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs

Author

Jiang, Zhe, Yang, Kecheng, Fisher, Nathan, Guan, Nan, Audsley, Neil C., and Dong, Zheng

Abstract

Following the trend of increasing autonomy in real-time systems, multi-core System-on-Chips (SoCs) have enabled devices to better handle the large streams of data and intensive computation required by such autonomous systems. In modern multi-core SoCs, each L1 cache is designed to be tied to an individual processor, and a processor can only access its own L1 cache. This design method ensures the system's average throughput, but also limits the possibility of parallelism, significantly reducing the system's real-time schedulability. To overcome this problem, we present a new system framework for highly-parallel multi-core systems, Hopscotch. Hopscotch introduces re-sizable L1 cache which is shared between processors in the same computing cluster. At execution, Hopscotch dynamically allocates L1 cache capacity to the tasks executed by the processors, unblocking the available parallelism in the system. Based on the new hardware architecture, we also present a new theoretical model and schedulability analysis providing cache size selection methods and corresponding timing guarantees for the system. As demonstrated in the evaluations, Hopscotch effectively improves system-level schedulability with negligible extra overhead.

Published
2024
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10. AXI-IC<inline-formula><tex-math notation="LaTeX">$^{\mathrm{ RT}}$</tex-math><alternatives><mml:math><mml:msup><mml:mrow/><mml:mi> RT </mml:mi></mml:msup></mml:math><inline-graphic xlink:href="dong-ieq1-3179227.gif"/></alternatives></inline-formula>: Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs

Author

Jiang, Zhe, Yang, Kecheng, Fisher, Nathan, Gray, Ian, Audsley, Neil C., and Dong, Zheng

Abstract

In modern real-time heterogeneous System-on-Chips (SoCs), ensuring the predictability of interconnects is becoming increasingly important. Most of the existing interconnects are mainly designed to achieve high throughput, with their micro-architectures usually based on FIFO queues. The FIFO-based design prevents transaction prioritization based on importance and leads to occurrences of physical priority inversion. Such problems lead to difficulties in ensuring transaction predictability, especially when the system scales to a large number of elements. In this paper, we introduce AXI-Interconnect$^{\mathrm {RT}}$ RT (AXI-IC$^{\mathrm {RT}}$ RT , for short) – a real-time AXI interconnect for heterogeneous SoCs, which redefines the micro-architecture of interconnects by enabling random accesses of buffered transactions and organizing transactions through compositional scheduling. This hardware-software co-design approach provides predictable and scalable real-time performance for highly integrated SoCs.

Published
2023
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11. BlueVisor: Time-Predictable Hardware Hypervisor for Many-Core Embedded Systems.

Author

Jiang, Zhe, Wei, Ran, Dong, Pan, Zhuang, Yan, Audsley, Neil C., and Gray, Ian

Subjects
COMPUTING platforms, HYPERVISOR (Computer software), COMPUTER systems, VIRTUAL machine systems, HARDWARE
Abstract

Whilst virtualization was once restricted to large-scale computing platforms, it is now widely deployed on modern embedded computing systems. This has been driven by the availability of hardware support which alleviates the performance penalties incurred by traditional software virtualization technologies. In the domain of hard real-time systems, specialist virtualization technology which respects restricted timing requirements and constraints can be deployed to allow sharing of processors. However, other aspects of the embedded system (I/O, memory, and communication) are harder to analyze. In this paper, we argue that in order to support real-time virtualization on modern embedded systems, additional system-wide hardware support is required. We propose BlueVisor, an analyzable and scalable hardware hypervisor for many-core embedded systems, which enables time-predictable CPU, memory, and I/O virtualization, as well as supporting a fast interrupt handler, and inter-VM communication. We describe the design and implementation of the real-time hypervisor, and demonstrate how a BlueVisor-based virtualization system can be leveraged to meet real-time requirements with significant improvement in system performance, and with a low-performance cost when executing different types of software. [ABSTRACT FROM AUTHOR]

Published
2022
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16. Errata for Three Papers (2004-05) on Fixed-Priority Scheduling with Self-Suspensions

Author

Konstantinos Bletsas and Neil C. Audsley and Wen-Hung Huang and Jian-Jia Chen and Geoffrey Nelissen, Bletsas, Konstantinos, Audsley, Neil C., Huang, Wen-Hung, Chen, Jian-Jia, Nelissen, Geoffrey, Konstantinos Bletsas and Neil C. Audsley and Wen-Hung Huang and Jian-Jia Chen and Geoffrey Nelissen, Bletsas, Konstantinos, Audsley, Neil C., Huang, Wen-Hung, Chen, Jian-Jia, and Nelissen, Geoffrey

Abstract

The purpose of this article is to (i) highlight the flaws in three previously published works [Audsley, 2004a; Audsley, 2004b; Bletsas, 2005] on the worst-case response time analysis for tasks with self-suspensions and (ii) provide straightforward fixes for those flaws, hence rendering the analysis safe.

Published
2018
Full Text
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19. Dynamic and Static Task Allocation for Hard Real-Time Video Stream Decoding on NoCs

Author

Hashan R. Mendis and Neil C. Audsley and Leandro Soares Indrusiak, Mendis, Hashan R., Audsley, Neil C., Indrusiak, Leandro Soares, Hashan R. Mendis and Neil C. Audsley and Leandro Soares Indrusiak, Mendis, Hashan R., Audsley, Neil C., and Indrusiak, Leandro Soares

Abstract

Hard real-time (HRT) video systems require admission control decisions that rely on two factors. Firstly, schedulability analysis of the data-dependent, communicating tasks within the application need to be carried out in order to guarantee timing and predictability. Secondly, the allocation of the tasks to multi-core processing elements would generate different results in the schedulability analysis. Due to the conservative nature of the state-of-the-art schedulability analysis of tasks and message flows, and the unpredictability in the application, the system resources are often under-utilised. In this paper we propose two blocking-aware dynamic task allocation techniques that exploit application and platform characteristics, in order to increase the number of simultaneous, fully schedulable, video streams handled by the system. A novel, worst-case response time aware, search-based, static hard real-time task mapper is introduced to act as an upper-baseline to the proposed techniques. Further evaluations are carried out against existing heuristic-based dynamic mappers. Improvements to the admission rates and the system utilisation under a range of different workloads and platform sizes are explored.

Published
2017
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45. Efficient Access of Remote Resources in Embedded Networked Computer Systems.

Author

Enokido, Tomoya, Lu Yan, Bin Xiao, Daeyoung Kim, Yuanshun Dai, Yang, Laurence T., Usher, Paul S., and Audsley, Neil C.

Abstract

Fixed networks of limited resource heterogeneous computers need to allow applications to access remote devices in order to overcome any local resource deficiencies. Current operating systems would use a file system, network stack and middleware to implement such access but the volume of functionality involved can be a barrier to performance. This paper examines the 2.4 series Linux kernel to show that networked operating systems lack flexibility and performance in this environment. It also presents a low level approach that can reduce the overheads incurred and improve performance when remote devices are accessed. [ABSTRACT FROM AUTHOR]

Published
2005
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48. Errata for three papers (2004-05) on fixed-priority scheduling with self-suspensions

Author

Blestas, Konstantinos, Audsley, Neil C., Huang, Wen-Hung, Jian-Jia Chen, Nelissen, Geoffrey, and Repositório Científico do Instituto Politécnico do Porto

Subjects
Scheduling, Worst-case response time analysis, 0202 electrical engineering, electronic engineering, information engineering, 020207 software engineering, 02 engineering and technology, Self-suspension, Embedded systems, Real-time systems, Real-time schedulability, Real-time, 020202 computer hardware & architecture, real-time, scheduling, self-suspension, worst-case response time analysis
Abstract

The purpose of this article is to (i) highlight the flaws in three previously published works [Audsley, 2004a; Audsley, 2004b; Bletsas, 2005] on the worst-case response time analysis for tasks with self-suspensions and (ii) provide straightforward fixes for those flaws, hence rendering the analysis safe., Leibniz Transactions on Embedded Systems, Vol 5, No 1 (2018)

49. Virtual memory on a many-core NoC

Author

McMenamin, Adrian Ciaran, Audsley, Neil C., and Wellings, Andy

Subjects
004
Abstract

Many-core devices are likely to become increasingly common in real-time and embedded systems as computational demands grow and as expectations for higher performance can generally only be met by by increasing core numbers rather than relying on higher clock speeds. Network-on-chip devices, where multiple cores share a single slice of silicon and employ packetised communications, are a widely-deployed many-core option for system designers. As NoCs are expected to run larger and more complex programs, the small amount of fast, on-chip memory available to each core is unlikely to be sufficient for all but the simplest of tasks, and it is necessary to find an efficient, effective, and time-bounded, means of accessing resources stored in off-chip memory, such as DRAM or Flash storage. The abstraction of paged virtual memory is a familiar technique to manage similar tasks in general computing but has often been shunned by real-time developers because of concern about time predictability. We show it can be a poor choice for a many-core NoC system as, unmodified, it typically uses page sizes optimised for interaction with spinning disks and not solid state media, and transports significant volumes of subsequently unused data across already congested links. In this work we outline and simulate an efficient partial paging algorithm where only those memory resources that are locally accessed are transported between global and local storage. We further show that smaller page sizes add to efficiency. We examine the factors that lead to timing delays in such systems, and show we can predict worst case execution times at even safety-critical thresholds by using statistical methods from extreme value theory. We also show these results are applicable to systems with a variety of connections to memory.

Published
2019

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