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International audience

Netrin-1 is upregulated in a large fraction of human neoplasms. In multiple animal models, interference with netrin-1 is associated with inhibition of tumor growth and metastasis. Although netrin-1 upregulation was initially described in cancer cells, we report here that in the human colorectal cancer database, the expression of netrin-1 and its receptor UNC5B correlates with a cancer-associated fibroblasts (CAF) signature. Both colon and lung CAF secreted netrin-1 when cocultured with respective cancer cells, and netrin-1 upregulation in CAF was associated with increased cancer cell stemness. Pharmacologic inhibition of netrin-1 with a netrin-1–mAb (Net1–mAb) abrogated the CAF-mediated increase of cancer stemness both in coculture experiments and in mice. Net-1–mAb inhibited intercellular signaling between CAF and cancer cells by modulating CAF-mediated expression of cytokines such as IL6. Together these data demonstrate that netrin-1 is upregulated not only in cancer cells but also in cancer-associated stromal cells. In addition to its direct activity on cancer cells, inhibition of netrin-1 may reduce proneoplastic CAF–cancer cell cross-talk, thus inhibiting cancer plasticity. Significance: Netrin-1, a navigation cue during embryonic development, is upregulated in cancer-associated fibroblasts and regulates cancer cell stemness.

International audience

International audience; The proper tissue-specific regulation of gene expression is essential for development and homeostasis in metazoans. However, the illegitimate expression of normally tissue-restricted genes-like testis- or placenta-specific genes-is frequently observed in tumors; this promotes transformation, but also allows immunotherapy. Two important questions are: how is the expression of these genes controlled in healthy cells? And how is this altered in cancer? To address these questions, we used an unbiased approach to test the ability of 350 distinct genetic or epigenetic perturbations to induce the illegitimate expression of over 40 tissue-restricted genes in primary human cells. We find that almost all of these genes are remarkably resistant to reactivation by a single alteration in signaling pathways or chromatin regulation. However, a few genes differ and are more readily activated; one is the placenta-expressed gene ADAM12, which promotes invasion. Using cellular systems, an animal model, and bioinformatics, we find that a non-canonical but druggable TGF-β/KAT2A/TAK1 axis controls ADAM12 induction in normal and cancer cells. More broadly, our data show that illegitimate gene expression in cancer is an heterogeneous phenomenon, with a few genes activatable by simple events, and most genes likely requiring a combination of events to become reactivated.

Cellular senescence is a response characterized by a stable cell proliferation arrest and a senescence-associated secretory phenotype (SASP) which can be induced by many stresses, including telomere shortening and oncogene activation. Senescence is crucially involved in a variety of physiopathological contexts, such as cancer and aging. Given the fundamental role of this process, senescence needs to be tightly regulated. In the last decade, the key implication of nuclear receptors in cellular senescence has emerged. Here we will review the mechanisms involved in the control of cellular senescence by retinoid X receptors (RXRs) and their partners. We will also present our current knowledge on the regulation of these receptors during senescence and on their potential role in senescence-associated physiopathological conditions.

International audience; Calcium signaling is emerging as a key pathway controlling cellular senescence, astable cell proliferation arrest playing a fundamental role in pathophysiological conditions, such as embryonic development, wound healing, cancer, and aging. However, how calcium signaling is regulated is still only partially understood. The inositol 1, 4, 5‐trisphosphate receptor type 2 (ITPR2), an endoplasmic reticulum calcium release channel, was recently shown to critically contribute to the implementation of senescence, but how ITPR2 expression is controlled is unclear. To gain insights into the regulation of ITPR2 expression, we performed an siRNA screen targeting160 transcription factors and epigenetic regulators. Interestingly, we discovered that the retinoid X receptor alpha (RXRA), which belongs to the nuclear receptor family,represses ITPR2 expression and regulates calcium signaling though ITPR2 and themitochondrial calcium uniporter (MCU). Knockdown of RXRA induces the production of reactive oxygen species (ROS) and DNA damage via the ITPR2‐MCU calcium signaling axis and consequently triggers cellular senescence by activating p53,whereas RXRA overexpression decreases DNA damage accumulation and then delays replicative senescence. Altogether, our work sheds light on a novel mechanism controlling calcium signaling and cellular senescence and provides new insights into the role of nuclear receptors.

International audience; Oncogenic signals lead to premature senescence in normal human cells causing a proliferation arrest and the elimination of these defective cells by immune cells. Oncogene-induced senescence (OIS) prevents aberrant cell division and tumor initiation. In order to identify new regulators of OIS, we performed a loss-of-function genetic screen and identified that the loss of SCN9A allowed cells to escape from OIS. The expression of this sodium channel increased in senescent cells during OIS. This upregulation was mediated by NF-kappaB transcription factors, which are well-known regulators of senescence. Importantly, the induction of SCN9A by an oncogenic signal or by p53 activation led to plasma membrane depolarization, which in turn, was able to induce premature senescence. Computational and experimental analyses revealed that SCN9A and plasma membrane depolarization mediated the repression of mitotic genes through a calcium/Rb/E2F pathway to promote senescence. Taken together, our work delineates a new pathway, which involves the NF-kappaB transcription factor, SCN9A expression, plasma membrane depolarization, increased calcium, the Rb/E2F pathway and mitotic gene repression in the regulation of senescence. This work thus provides new insight into the involvement of ion channels and plasma membrane potential in the control of senescence.

Cellular senescence response is (i) activated by numerous stresses, (ii) is characterized by a stable proliferation arrest, and (iii) by a set of specific features. Timely regulated senescence is thought to be beneficial, whereas chronic senescence such as during normal or premature aging is deleterious as it favors most, if not all, age-related diseases. In this study, using in-house or publicly available microarray analyses of transcriptomes of senescent cells, as well as analyses of the level of expression of several DNA repair genes by RT-qPCR and immunoblot, we show that repression of DNA repair gene expression is associated with cellular senescence. This repression is mediated by the RB/E2F pathway and it may play a causal role in senescence induction, as single DNA repair gene repression by siRNA induced features of premature senescence. Importantly, activating RB independently of direct DNA damage also results in repression of DNA repair genes and in the subsequent induction of DNA damage and senescence. The dogma is that DNA damage observed during cellular senescence is directly provoked by DNA lesions following genotoxic attack (UV, IR, and ROS) or by induction of replicative stress upon oncogenic activation. Our in vitro results support a largely unsuspected contribution of the loss of DNA repair gene expression in the induction and the accumulation of the DNA damage observed in most, if not all, kinds of cellular senescence, and thus in the induction of cellular senescence. Further demonstration using in vivo models will help to generalize our findings.

International audience

A new concept for improving efficiency of a charge pump system is presented. The concept is based on a set of elementary charge pumps connected in parallel in addition to the detection of the number of memory cells to be programmed at the same time. The proposed solution is able to supply current to a memory cell, while operating with maximum efficiency by activating one, two or more charge pumps. The proposed system is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. In the worst case where only one cell is to be programmed, simulation results show an improvement of power efficiency by a factor 2. The area penalty of the proposed system is only 3.8%.

An ultra-low power regulated charge pump system based on charge recycling between a tank capacitor and the charge pump output load capacitor is presented. The proposed circuit is implemented using a 55 nm UMC High Voltage CMOS technology with a power supply of 1.2V. Simulation results show a maximum current reduction of about 38% compared to a conventional regulated charge pump system. Rise time until the steady state is reached is also reduced by 17%.

International audience; This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

International audience; These design techniques target EEPROMs embedded in portable, battery-powered devices that operate under a wide supply voltage range. A current-controlled ring oscillator provides stable programming pulse generation, optimizing write time. Logic delay optimization and a word line boosting technique decrease read access time.

International audience; This paper presents an overview of the switching noise analysis in a DCDC converter by considering the first order parasitic elements involved in the noise generation. Simplified theory is provided in order to help circuit designers selecting the optimum components for low noise operation. Theory versus simulation and measurement are carried out.

The first part of this thesis presents a state of the art of different DFM approaches in the industrial production flow. A new DFM design methodology is defined. It is called DFM², and it is mainly based on the intensification of interactions between design and process. The cell design is the center of these interactions in order to apply DFM optimizations before the circuit conception. The following of the study presents results about the decrease of the design dependence versus process variations in many domains, such as planarity or lithography for both FEOL and BEOL. A statistical study about the metallization step is then proposed, in order to model the impact of metal filling patterns on electrical performances of circuits. The results obtained allow defining new simulations corners in order to take into account this effect at the cell design step. Finally, an aided-cell design tool (DUTY) is proposed. Its goal is to help designers to adopt DFM² methodology by proposing DFM optimizations, mainly based on previous obtained results. Furthermore, the goal of DUTY is to correlate DFM modifications with yield optimization.; La première partie du manuscrit présente un état de l'art des différentes visions du DFM au sein du processus de conception industriel. Une nouvelle méthode de conception orientée DFM baptisée le DFM² est définie, se basant principalement sur l'intensification des interactions entre la conception et la fabrication. L'étape de conception de cellules se place au coeur de ces interactions afin d'appliquer les améliorations DFM en amont de la conception du circuit. La suite de l'étude présente des résultats visant à s'affranchir de la variabilité observée lors de la fabrication, concernant des domaines comme la planéité ou la lithographie à la fois pour le FEOL et le BEOL. Une étude statistique sur l'étape de métallisation est ensuite proposée, visant à modéliser l'impact de la géométrie du motif des dispositifs de remplissage métalliques sur les performances électriques des circuits. Les résultats permettent de définir de nouvelles conditions de simulation afin de prendre en compte cet effet dès la conception des cellules. Enfin, un outil d'aide à la conception de cellules (DUTY) est proposé. Son objectif est en premier lieu d'accompagner les concepteurs dans la mise en place du DFM² en leur proposant des améliorations DFM basées principalement sur les résultats obtenus précédemment. De plus, son but à long terme est de corréler les modifications DFM réalisées avec les améliorations de rendement attendues.

The first part of this thesis presents a state of the art of different DFM approaches in the industrial production flow. A new DFM design methodology is defined. It is called DFM², and it is mainly based on the intensification of interactions between design and process. The cell design is the center of these interactions in order to apply DFM optimizations before the circuit conception. The following of the study presents results about the decrease of the design dependence versus process variations in many domains, such as planarity or lithography for both FEOL and BEOL. A statistical study about the metallization step is then proposed, in order to model the impact of metal filling patterns on electrical performances of circuits. The results obtained allow defining new simulations corners in order to take into account this effect at the cell design step. Finally, an aided-cell design tool (DUTY) is proposed. Its goal is to help designers to adopt DFM² methodology by proposing DFM optimizations, mainly based on previous obtained results. Furthermore, the goal of DUTY is to correlate DFM modifications with yield optimization.; La première partie du manuscrit présente un état de l'art des différentes visions du DFM au sein du processus de conception industriel. Une nouvelle méthode de conception orientée DFM baptisée le DFM² est définie, se basant principalement sur l'intensification des interactions entre la conception et la fabrication. L'étape de conception de cellules se place au coeur de ces interactions afin d'appliquer les améliorations DFM en amont de la conception du circuit. La suite de l'étude présente des résultats visant à s'affranchir de la variabilité observée lors de la fabrication, concernant des domaines comme la planéité ou la lithographie à la fois pour le FEOL et le BEOL. Une étude statistique sur l'étape de métallisation est ensuite proposée, visant à modéliser l'impact de la géométrie du motif des dispositifs de remplissage métalliques sur les performances électriques des circuits. Les résultats permettent de définir de nouvelles conditions de simulation afin de prendre en compte cet effet dès la conception des cellules. Enfin, un outil d'aide à la conception de cellules (DUTY) est proposé. Son objectif est en premier lieu d'accompagner les concepteurs dans la mise en place du DFM² en leur proposant des améliorations DFM basées principalement sur les résultats obtenus précédemment. De plus, son but à long terme est de corréler les modifications DFM réalisées avec les améliorations de rendement attendues.

Over the last 20 years, the industry of microelectronics and particularly the non-volatile memory market has known a considerable growth, in terms of integration capacity increasing and cost reduction. Consumers have been able to access to electronic products (mobile phones, MP3 players, flash drives, digital cameras...) which are currently very successful. However, scaling of standard Flash memories will face in a near future several limitations. Consequently, new paths are investigated in order to push the scaling limits of these devices. Within this context, the main purpose of this PhD is the experimental and theoretical study of nonvolatile silicon nanocrystal memories. First, several options of silicon nanocrystal integration using a standard process have been shown. A 32Mb NOR silicon nanocrystal Flash memory demonstrator has been fabricated from an ATMEL product. Then, electrical characterization of memory cells and arrays has been performed. An exhaustive study of the influence of programming conditions and technological parameters has been carried out. The influence of some parameters has been understood through modeling of Fowler- Nordheim erasing and gate disturb. Finally, the localization of the trapped charges in silicon nanocrystal devices written by Hot Electron injection has been investigated through TCAD simulations and an exhaustive set of experimental data explained by an analytical model.; Depuis une vingtaine d'années, l'industrie de la microélectronique et en particulier le marché des mémoires non-volatiles connaît une évolution considérable, en termes d'augmentation de la capacité d'intégration et de diminution du prix de revient. Ceci a permis au grand public d'accéder aux produits électroniques (téléphones portables, baladeurs MP3, clés USB, appareils photos numériques...) qui connaissent actuellement un énorme succès. Cependant, la miniaturisation des mémoires Flash risque de rencontrer des limitations. C'est pourquoi les industriels et les laboratoires recherchent actuellement de nouvelles voies qui permettraient de prolonger la durée de vie de ces dispositifs. Dans ce contexte, l'objectif premier de cette thèse est l'étude expérimentale et théorique des mémoires non-volatiles à nanocristaux de silicium. Nous avons montré les différentes possibilités d'intégration des nanocristaux de silicium à partir d'un procédé de fabrication standard. Un démonstrateur Flash NOR 32 Mb à nanocristaux de silicium a été réalisé à partir d'un produit ATMEL. Nous nous sommes ensuite intéressés à la caractérisation électrique des cellules et matrices mémoires. Une étude exhaustive de l'influence des conditions de programmation ainsi que des paramètres technologiques sur les performances électriques a été menée. La modélisation de l'effacement Fowler-Nordheim et du « gate disturb » a permis de comprendre l'influence de certains de ces paramètres. Concernant l'écriture par porteurs chauds, nous avons étudié l'influence des conditions d'écriture sur la localisation de la charge à l'aide de simulations TCAD et d'un modèle analytique couplé à des mesures expérimentales.

Over the last 20 years, the industry of microelectronics and particularly the non-volatile memory market has known a considerable growth, in terms of integration capacity increasing and cost reduction. Consumers have been able to access to electronic products (mobile phones, MP3 players, flash drives, digital cameras...) which are currently very successful. However, scaling of standard Flash memories will face in a near future several limitations. Consequently, new paths are investigated in order to push the scaling limits of these devices. Within this context, the main purpose of this PhD is the experimental and theoretical study of nonvolatile silicon nanocrystal memories. First, several options of silicon nanocrystal integration using a standard process have been shown. A 32Mb NOR silicon nanocrystal Flash memory demonstrator has been fabricated from an ATMEL product. Then, electrical characterization of memory cells and arrays has been performed. An exhaustive study of the influence of programming conditions and technological parameters has been carried out. The influence of some parameters has been understood through modeling of Fowler- Nordheim erasing and gate disturb. Finally, the localization of the trapped charges in silicon nanocrystal devices written by Hot Electron injection has been investigated through TCAD simulations and an exhaustive set of experimental data explained by an analytical model.; Depuis une vingtaine d'années, l'industrie de la microélectronique et en particulier le marché des mémoires non-volatiles connaît une évolution considérable, en termes d'augmentation de la capacité d'intégration et de diminution du prix de revient. Ceci a permis au grand public d'accéder aux produits électroniques (téléphones portables, baladeurs MP3, clés USB, appareils photos numériques...) qui connaissent actuellement un énorme succès. Cependant, la miniaturisation des mémoires Flash risque de rencontrer des limitations. C'est pourquoi les industriels et les laboratoires recherchent actuellement de nouvelles voies qui permettraient de prolonger la durée de vie de ces dispositifs. Dans ce contexte, l'objectif premier de cette thèse est l'étude expérimentale et théorique des mémoires non-volatiles à nanocristaux de silicium. Nous avons montré les différentes possibilités d'intégration des nanocristaux de silicium à partir d'un procédé de fabrication standard. Un démonstrateur Flash NOR 32 Mb à nanocristaux de silicium a été réalisé à partir d'un produit ATMEL. Nous nous sommes ensuite intéressés à la caractérisation électrique des cellules et matrices mémoires. Une étude exhaustive de l'influence des conditions de programmation ainsi que des paramètres technologiques sur les performances électriques a été menée. La modélisation de l'effacement Fowler-Nordheim et du « gate disturb » a permis de comprendre l'influence de certains de ces paramètres. Concernant l'écriture par porteurs chauds, nous avons étudié l'influence des conditions d'écriture sur la localisation de la charge à l'aide de simulations TCAD et d'un modèle analytique couplé à des mesures expérimentales.

The aim of this study is to characterize the Pt influence on the formation of nickel silicides in the salicide process and especially on the low resistivity phase NiSi, that is believed to become the next silicide used as contacting material on source and drain region in flash memory transistors. We thus studied the nature, the sequence and the kinetics of the formed phases on various systems: firstly on the Ni1-xPtx/Si(100) (0% ≤ x ≤ 30%), and more especially on the Ni(13%Pt)/Si(100) system that presents very interesting properties for microelectronic devices. Two types of deposition techniques have been used and compared: layers deposited using a single Ni(13%Pt) alloyed target and co-deposited using two separated targets. Several in-situ characterization technique were coupled (x-ray diffraction and reflectivity, 4-points probe sheet resistance) in order to understand the mechanisms involved in this system. In particular, in-situ x-ray reflectivity experiments were performed using the synchrotron radiation (ESRF) and analyzed using the fast Fourier transform; these experiments show original results: the phase sequence is modified for the Ni(13%Pt). Finally, sheet resistance measurements have been performed on narrow lines to show the advantages and the limitations of this system.; L'objectif de cette étude est de regarder l'influence du Pt sur la formation des siliciures de Ni dans le procédé Salicide et en particulier sur la phase basse résistivité NiSi, envisagée par l'industrie pour réaliser les contacts avec les zones actives de transistors de type Flash. Pour cela, nous avons étudié la nature, la séquence et la cinétique des phases formées, d'une part sur le système Ni1-xPtx/Si(100) (0% ≤ x ≤ 30%), et plus particulièrement sur un système intéressant pour certaines de ces propriétés, Ni(13%Pt)/Si(100). Deux types de dépôts ont été confrontés : dépôts réalisés avec une cible alliée Ni(13%Pt) ou par codéposition (cibles Ni et Pt dissociées). Ainsi nous avons couplé différentes techniques de caractérisation in situ (diffraction des rayons X, Réflectivité des rayons X (RRX), résistivité 4 pointes) pour essayer de comprendre les mécanismes liés à ce système. En particulier des expériences de RRX in-situ, associées à une analyse par transformée de Fourier inverse, ont été mises en œuvre, en utilisant le rayonnement synchrotron (ESRF), et aboutissent à des résultats originaux : la séquence des phases est modifiée dans le cas du Ni(13%Pt). Enfin, des premières mesures de résistance sur lignes étroites ont été réalisées, soulignant les avantages et les limites associées à l'utilisation d'un tel système.

Flash memories are non-volatile memories present in a growing number of integrated circuits used in portable electronic devices. The non-volatility, low power consumption and flexibility make them extremely popular. Nevertheless, the reliability is a characteristic to improve as far as area needs increase and critical applications are targeted. Effectives fault tolerance solutions that are low cost and that can be easily integrated must be found. In a first time, the work of this thesis was focused on the analysis and the study of Flash reliability. It was the occasion to establish a reliability model for a floating gate cell depending on various parameters. This model was adjusted dependingon parameters coming from a 180 nm technology. In a second time, the work was dedicated on the development of two fault tolerance techniques merging error correcting codes and redundancy. The first technique, called error correction by VT analysis, provides an extended correction capacity by analyzing the charge level of cells. A mathematical study and next, a reliability architecture have been proposed. In this study, it is supposed that a given number of redundancy resources are available to repair the memory as soon as an error is detected. The second developed technique, called hierarchical error correction, uses the fact that correction capacities can be distributed in an originalway into the memory to significantly reduce the cost usually associated with advanced error correction techniques. This code has also been integrated in a reliability architecture having some redundancy resources. A mathematical study based on Continuous Time Markov Chain has allowed to demonstrate the effectiveness of this structure. Developed techniques are alternatives solutions to standard scheme used in the industry. They allows to improve significantly the mean time to failure of a system by many times at a reasonable area cost.; Les mémoires non-volatiles de type Flash sont présentes dans un grand nombre de circuits visant des applications électroniques portatives. Leur non-volatilité et flexibilité en font des mémoires extrêmement populaires. Néanmoins, la fiabilité devient une caractéristique à améliorer en raison des besoins en surface grandissants et de leur intégration dans des applications sensibles. Des solutions de tolérance aux fautes peu coûteuses et faciles à intégrer doivent être mises en place. Tout d'abord, cette étude s'est portée sur l'analyse et l'étude de la fiabilité des Flash. Il fut l'occasion d'établir un modèle de fiabilité d'une cellule à grille flottante. Ce modèle a été ajusté suivant les paramètres issus d'une technologie Flash 180nm. Dans un second temps, deux techniques de tolérance aux fautes mêlant codes correcteurs d'erreurs et redondance ont été mises au point. La première technique, nommée correction d'erreurs par analyse de VT, fournit des capacités de correction accrues par l'analyse du niveau de programmation des cellules mémoire. Une étude mathématique puis une architecture de fiabilisation ont été proposées. Dans cette étude, on suppose que des ressources de redondance sont disponibles afin de réparer la mémoire lorsqu'une erreur est détectée. La seconde technique, appelée correction d'erreur hiérarchique, utilise des capacités de correction distribuées dans la mémoire Flash afin de réduire significativement le coût associé à une correction d'erreur avancée. Cette technique a été intégrée dans une architecture de fiabilisation disposant de ressources de redondance. Une étude basée sur les Chaines de Markov à Temps Continu a démontré l'efficacité de cette structure. Ces techniques constituent des solutions alternatives aux schémas standards utilisés dans l'industrie. Elles augmentent significativement le temps moyen à la défaillance du système sans faire exploser la surface requise à l'intégration une structure de toléranceaux fautes.

International audience; This paper introduces a complete simulation model of a Direct Power Injection (DPI) setup, used to measure the immunity of integrated circuits to conducted continuous-wave interference. This model encompasses the whole measurement setup itself as well as the integrated circuit under test and its environment (printed circuit board, power supply). Furthermore, power losses are theoretically computed, and the most significant ones are included in the model. Therefore, the injected power level causing a malfunction of an integrated circuit, according to a given criterion, can be identified and predicted at any frequency up to 1 GHz. In addition to that, the relationship between immunity and impedance is illustrated. Simulation results obtained from the model are compared to measurement results and demonstrate the validity of this approach.

International audience; This paper presents a methodology for analyzing the behavior of nanometer technologies regarding "Multiple Event Transients" (MET) caused by nuclear reaction induced by atmospheric neutrons. For the first time, currents collected by several sensitive areas of an ASIC cell resulting from a nuclear reaction are addressed by simulation. Libraries of several thousand types of currents are obtained for neutron energy range between 1 and 200 MeV. Group of currents are simultaneously injected at SPICE level and their effects are monitored on the cell output. Following an amplitude criterion, output transient duration and associated occurrence probability are recorded. A 130nm NAND gate from ATMEL Corporation is first used to illustrate the methodology and a comparison between Single Event Transients and Multiple Event Transients effects is presented. Finally, results regarding five different combinational cells in the ATMEL 130nm library are presented and discussed.

International audience; This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18mum standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240 MHz without increasing the power consumption, which is 2.4 mW at 240 MHz.

International audience; In this paper, design aspects, protection capabilities and applications of Low-Voltage-Triggered bipolar PNP in comparison with grounded-gate NMOS protection are presented. Experimental results are obtained in an embedded 0.18 μm salicided CMOS process.

16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings; International audience; This paper introduces two low power design techniques to improve both the jitter and phase noise of PLL frequency synthesizers used in ASICs. These techniques focus on the noise current reduction in wideband ring VCOs. Two PLLs embedding such VCOs were implemented, in 0.18μm and 0.13μm CMOS technologies, under 1.8V and 1.2V supply voltages respectively. The maximum improvement was observed for a 1.8V PLL running at 160MHz and consuming 1.6mW, which phase noise was reduced from -81.4dBc/Hz to -88.4dBc/Hz.

In order to improve the efficiency of an industrial atmospheric pressure chemical vapour deposition (APCVD) moving belt reactor depositing silicon dioxide SiO2 films from tetraethoxysilane Si(OC2H5)4 (TEOS) andozone O3, a 2D simulation model based on the computational fluid dynamics (CFD) software ESTET has been developed. On the basis of the global chemical scheme of Zhou et al. [1997. Fifth International Conference on Advanced Thermal Processing of Semiconductors, RTP’97, New Orleans, LA, USA, pp. 257–268], a new kinetic model has been developed to conveniently represent our own set of experimental data. In particular, a chemical limitation for TEOS has been introduced, conferring increased chemical validity to the model. Simulations have shown that for the nominal conditions, TEOS conversion into SiO2 layers was too low andthat an increase in ozone concentration or in the nitrogen flow rates through the injector did not offer any advantage. Conversely, a decrease in the curtain nitrogen flow rate or an increase in that of the shieldcan enhance the process productivity and TEOS conversion.

International audience; The ICEM draft proposal deals with an extension of the IBIS [1] standard, aimed at predicting conducted-mode as well as radiated-mode emission [2]. This proposal provides a modeling methodology for the power supply network and the current activity of an integrated circuit. Thanks to these models, predicting conducted-mode emission levels on the chip as well as on the application board becomes possible by the means of SPICE-based analog simulations. This allows the chipmaker to better choose the chip package as well as the number of power supply pairs, and the integrator to fine tune the number of power supply networks and decoupling capacitors. The corresponding models may be elaborated either in the design phase or from measurements performed as soon as the silicon becomes available. This article briefly summarizes the ICEM model, then introduces the proposed methodology aimed at obtaining the current activity model from the measurements performed on the current consumed on the power supply pins of an IC.

International audience; This paper introduces a set of analytical formulations for 3D modelling of inter- and intra-layer capacitance. Based on real silicon data, we have developed and validated efficient and accurate analytical models that are an helpful alternative to lookup tables or numerical simulations.

A detailed investigation of the switching characteristics for high frequency power devices based on different technologies has been provided: BJT, MOSFET, and MESFET/HEMT structures are considered. Advantages of GaAs power switches over silicon ones have been established and illustrated. Hybrid technology prototypes of DC-to-DC power converters operating above 10 MHz and exclusively using GaAs components have been realized: for a nonoptimized boost converter operating at 100 MHz, a power efficiency of 54% has been achieved with a 6 V/12 V conversion ratio and an output power of 1.5 W. For optimized prototypes, using high frequency assembly techniques, an efficiency of 80% at 50 MHz, 74% at 100 MHz and 60% at 250 MHz have been obtained with 6 V/12 V and 3 W.