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Electrical power connectors are critical points of electrical networks. Failure in high-voltage connectors may result in major power outages, safety risks and important economic consequences. Therefore, there is an imperious need to tackle such issue by developing suitable on-line condition monitoring strategies to minimize the aforementioned problems and to ease the application of predictive maintenance tasks. This work develops an on-line condition monitoring method to predict early failures in power connectors from data acquired on-line (electric current and voltage drop across the connector, and temperature) to determine the instantaneous value of the connector resistance, since it is used as a signature or indicator of its health condition. The proposed approach combines a parametric degradation model of the resistance of the connector, whose parameters are identified by means of the Markov chain Monte Carlo stochastic method, which also provides the confidence intervals of the electrical resistance. This fast approach allows an on-line diagnosis of the health condition of the connector, anticipating its failure and thus, easing the application of predictive maintenance plans. Laboratory results emulating the ageing conditions of the connectors prove the suitability and feasibility of the proposed approach, which could be applied to other power products and apparatus.

©2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Low pressure environments, situate insulation systems in a challenging position since partial discharges (PDs), corona and arc tracking are more likely to develop. Therefore, specific solutions are required to detect such harmful phenomena before major failure occurrence. This paper deals with three low-cost and small-size sensing methods, i.e., a single loop antenna, a visible-UV imaging sensor and the measurement of the leakage current to detect corona in the early stage, thus anticipating the appearance of severer effects such as arc tracking or disruptive breakdown. The three studied methods can be applied for an on-line monitoring of corona activity under low pressure environments, thus being compatible with predictive maintenance approaches. This on-line monitoring can be used to develop improved electrical protection devices able to detect such effects in an initial stage, thus improving current solutions which are unable to do so. All three studied sensors give consistent linear responses within the studied pressure range, i.e., 10-100 kPa, with almost no drift. The sensitivity of the visible-UV imaging sensor is slightly lower than that of the others, but it has the advantage of directly locating the discharge points. Results presented in this paper can be very useful for the more electrical aircraft (MEA), which is forcing electrical distribution systems to operate at higher voltage levels. Due to the little experience and scarcity of published data, the experimental results presented in this paper can be valuable for a better understanding of the combined action of high voltage and low pressure environments. This work was supported in part by the Generalitat de Catalunya under Project 2017 SGR 967 & in part by the Spanish Ministry of Science and Innovation under Project RTC-2017-6297-3. J.-R. Riba is with the Universitat Politècnica de Catalunya

© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Model-based simulation is one of the effective methods of scientific research. The inherent variability of resistive switching mechanisms has been an obstacle for the massive commercial implementation of the resistive random access memory (RRAM) devices. In this work, we simulated the resistive switching behavior based on an existing RRAM Verilog-A model, in which the simulated switching parameters demonstrated a satisfactory fit with the experimental data by introducing variability into the model. Moreover, a potential application of the troublesome variability was explored in the serial configuration of two RRAM devices, a cell which had been demonstrated to generate unpredictable bits with potential applications in hardware security. Realistic simulation of RRAM based circuits is key for the future development of RRAM based applications.

Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal. This research was supported in part by the Spanish Ministry of Science, Innovation and Universities under Grant PID2019-103869RB-C33/ AEI /10.13039/501100011033, and the FEDER program under Grant TEC2017-84321-C4-1-R.

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications. This research was supported in part by the Spanish Ministry of Science, Innovation and Universities under Grant PID2019-103869RB-C33/ AEI /10.13039/501100011033, and the FEDER program under Grant TEC2017-84321-C4-1-R.

The ageing process of medium voltage power connectors can lead to important power system faults. An on-line prediction of the remaining useful life (RUL) is a convenient strategy to prevent such failures, thus easing the application of predictive maintenance plans. The electrical resistance of the connector is the most widely used health indicator for condition monitoring and RUL prediction, even though its measurement is a challenging task because of its low value, which typically falls in the range of a few micro-ohms. At the present time, the RUL of power connectors is not estimated, since their electrical parameters are not monitored because medium voltage connectors are considered cheap and secondary devices in power systems, despite they play a critical role, so their failure can lead to important power flow interruptions with the consequent safety risks and economic losses. Therefore, there is an imperious need to develop on-line RUL prediction strategies. This paper develops an on-line method to solve this issue, by predicting the RUL of medium voltage connectors based on the degradation trajectory of the electrical resistance, which is characterized by analyzing the electrical resistance time series data by means of the autoregressive integrated moving average (ARIMA) method. The approach proposed in this paper allows applying predictive maintenance plans, since the RUL enables determining when the power connector must be replaced by a new one. Experimental results obtained from several connectors illustrate the feasibility and accuracy of the proposed approach for an on-line RUL prediction of power connectors. This research was partially funded by the Ministerio de Ciencia, Innovación y Universidades de España, grant number RTC‐2017‐6297‐3, and by the Generalitat de Catalunya, grant number 2017 SGR 967

Insulation faults in high-voltage applications often generate partial discharges (PDs) accompanied by corona activity, optical radiation mainly in the ultraviolet (UV) and visible bands. Recent developments in low-cost, small-size, and high-resolution visible imaging sensors, which are also partially sensitive to the UV spectral region, are gaining attention due to their many industrial applications. This paper proposes a method for early PD detection by using digital imaging sensors, which allows the severity of insulation faults to be assessed. The electrical power dissipated by the PDs is correlated to the energy of the acquired visible images, and thus, the severity of insulation faults is determined from the energy of the corona effect. A criterion to quantify the severity of insulation faults based on the energy of the corona images is proposed. To this end, the point-to-plane gap configuration is analyzed in a low-pressure chamber, where digital image photographs of the PDs are taken and evaluated under different pressure conditions ranging from 10 to 100 kPa, which cover the typical pressure range of aeronautic applications. The use of digital imaging sensors also allows an early detection, location and quantification of the PD activity, and thus assessing the severity of insulation faults to perform predictive maintenance tasks, while enabling the cost and complexity of the instrumentation to be reduced. Although the approach proposed in this paper has been applied to detect PDs in aeronautic applications, it can be applied to many other high-voltage applications susceptible of PD occurrence.

This paper provides a comprehensive and critical review and evaluation of the technological state-of-the-art of high-temperature low-sag (HTLS) conductors by analyzing research articles, theses, reports, white papers and international standards. The growth of power demand requires new solutions to develop power transmission systems, while facing the issues related to power systems congestion. A possibility to solve the load growth issue is to increase the capacity of existing transmission systems by reconductoring the lines with new conductors, which are able to operate at higher temperatures, while limiting the sag and maintaining or reducing the required clearances, thus having more current carrying capacity than the existing ones. This paper also describes the limitations of such technology and identifies the research needs to fulfill the requirements of the industry and transmission system operators. This work was supported in part by the Generalitat de Catalunya under Project 2017 SGR 967 and in part by the Spanish Ministry of Economy and Competitiveness under Project RTC-2017-6297-3.

Alternate testing techniques have been progressively adopted as a promising solution due to their effectiveness against classical specification-based test methods. This work presents a built-in test system, which adaptively generates an indirect digital signature characterising the circuit under test, which is later used to diagnose the actual performances relying on a statistical dictionary-based diagnosis method. The system is composed of an integrated digital signature generator and a digital control and acquisition subsystem. The signature generator is based on a converter architecture, in which the analogue range can be adapted to the magnitude of the indirect measure using the well known information of the fault-free circuit. The digital subsystem controls the proposed architecture and stores the digital codes sent by the integrated digital signature generator. The digital signature generator has been designed and fabricated in an industrial 65 nm complementary metal–oxide–semiconductor technology from STMicroelectronics, whereas the digital control and acquisition subsystem have been prototyped in a field-programmable gate array. The fabricated system has been used to test a biquad filter affected by parametric variations. Successful experimental results are reported showing the capabilities of the proposed adaptive test system to diagnose circuit performances with discrepancies as low as 1% of the actual real value.

Substation connectors, like many other high-voltage products, are tested once manufactured. However, the corona behavior of aged specimens can differ from that exhibited by newer ones, thus generating detrimental technical and environmental effects. Manufacturers need to know the long-term corona behavior of substation connectors to offer their customers maximum safety and transparency about such critical products. This paper analyzes the ageing effect on the surface roughness and the visual corona extinction voltage of sand-cast aluminum connectors, which were artificially aged in a salt spray chamber for different periods. The experimental results show an important variability of the surface roughness and corona extinction voltage (CEV) among connectors with the same ageing level due to the sand-casting manufacturing process. The results in this paper also show a slight increase in the surface roughness with the ageing period, although there is not a clear pattern between the applied ageing level and the experimental CEV value. It is concluded that the inherent variability among connectors due to the sand-cast process has more influence than the ageing effect itself. This research was partially funded by Ministerio de Ciencia e Innovación de España, grant number RTC-2017-6297-3 and by the Generalitat de Catalunya, grant number 2017 SGR 967.

Next generation aircrafts will use more electrical power to reduce weight, fuel consumption, system complexity and greenhouse gas emissions. However, new failure modes and challenges arise related to the required voltage increase and consequent rise of electrical stress on wiring insulation materials, thus increasing the risk of electrical arc appearance. This work performs a critical and comprehensive review concerning arc tracking effects in wiring insulation systems, underlying mechanisms, role of materials and possible mitigation strategies, with a special focus on aircraft applications. To this end an evaluation of the scientific and technological state of the art is carried out from the analysis of theses, research articles, technical reports, international standards and white papers. This review paper also reports the limitations of existing insulation materials, standard test methods and mitigation approaches, while identifying the research needs to comply with the future demands of the aircraft industry.

Artificial neural networks allow the identification of black-box models. This paper proposes a method aimed at replicating the static and dynamic behavior of a DC-DC power converter based on a recurrent nonlinear autoregressive exogenous neural network. The method proposed in this work applies an algorithm that trains a neural network based on the inputs and outputs (currents and voltages) of a Buck converter. The approach is validated by means of simulated data of a realistic nonsynchronous Buck converter model programmed in Simulink and by means of experimental results. The predictions made by the neural network are compared to the actual outputs of the system, to determine the accuracy of the method, thus validating the proposed approach. Both simulation and experimental results show the feasibility and accuracy of the proposed black-box approach.

The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative to replace current memory technologies. However, their suitability for this kind of application, where the integrity of the data is crucial, is still under study. Among the different typology of attacks to recover information of secret data, laser attack is one of the most common due to its simplicity. Some preliminary works have already addressed the influence of laser tests on RRAM devices. Nevertheless, the results are not conclusive since different responses have been reported depending on the circuit under testing and the features of the test. In this paper, we have conducted laser tests on individual RRAM devices. For the set of experiments conducted, the devices did not show faulty behaviors. These results contribute to the characterization of RRAMs and, together with the rest of related works, are expected to pave the way for the development of suitable countermeasures against external attacks.

Visual corona tests have been broadly applied for identifying the critical corona points of diverse high-voltage devices, although other approaches based on partial discharge or radio interference voltage measurements are also widely applied to detect corona activity. Nevertheless, these two techniques must be applied in screened laboratories, which are scarce and expensive, require sophisticated instrumentation, and typically do not allow location of the discharge points. This paper describes the detection of the visual corona and location of the critical corona points of a sphere-plane gap configurations under different pressure conditions ranging from 100 to 20 kPa, covering the pressures typically found in aeronautic environments. The corona detection is made with a low-cost CMOS imaging sensor from both the visible and ultraviolet (UV) spectrum, which allows detection of the discharge points and their locations, thus significantly reducing the complexity and costs of the instrumentation required while preserving the sensitivity and accuracy of the measurements. The approach proposed in this paper can be applied in aerospace applications to prevent the arc tracking phenomenon, which can lead to catastrophic consequences since there is not a clear protection solution, due to the low levels of leakage current involved in the pre-arc phenomenon.

One of the most challenging aspects in nowadays microelectronics industry is production test and verification of mixed-signal circuits. In order to cope with some of the drawbacks encountered in this scenario, researchers have found alternate test as a promising solution in achieving such endeavor. This work prospects the possibilities of using space tessellations along multiple directions in order to improve the test decision boundary definition in the alternate measure space. The proposed method is able to reduce false positive test outcomes, i.e. test escapes, with acceptable penalty in test yield loss metric. The key idea presented in this work is to use an ensemble of octrees, each of them tessellating the plane along different directions. Such tessellations create a refinement in the non linear test decision boundaries without the need of including extra circuit samples. The tree ensemble, together with a strict test decision criterion, serve as a classifier during the production testing phase. The proposed multi-directional ensemble tessellation strategy has been applied to test a band-pass Biquad filter affected by parametric variations. The proposed method has reported promising simulation results in lowering the test escapes metric as compared to a single octree classifier. The computational overhead of evaluating several octrees is insignificant since 2n-tree data structures are traversed efficiently. The octree ensemble technique has also been compared against a classic specification guard-banding technique reporting better test yield loss metrics for the same test escape target.

In this letter, a cell with the parallel combination of two TiN/Ti/HfO/W resistive random access memory (RRAM) devices is studied for the generation of unpredictable bits. Measurements confirm that a simultaneous parallel SET operation in which one of the two RRAMs switches to the low-resistance state is an unpredictable process showing random properties for different sets of cells. Furthermore, given a device pair, the same device switches during subsequent write operations. The proposed cell is also analyzed under different current compliances and pulse widths with the same persistent behavior being observed. The features of the proposed cell, which provide data obfuscation without compromising reliability, pave the way for its application in physical unclonable functions for hardware security purposes.

Testing of analogue and M-S circuits using octree encoding in alternate measurements space has been shown effective to detect parametric failures. In this paper, the analysis of the viability to use octree encoding to detect catastrophic faults has been explored. In addition to the classical short and open defects, the class of controlling open faults causing unpredictable behaviour have been considered. In this category, fall some opens causing floating gate defects where the high impedance node gets a voltage imposed by the capacitive coupling of surrounding lines and possible leakage currents to the floating node. The method has been applied to a Biquad filter where a wide class of catastrophic defects (shorts, path opens and floating opens) have been injected. Parametric and catastrophic failures were detected using the same alternate test procedure achieving significant savings in test application time. The results show that with a simple octree based on two indirect measures detectability was guaranteed forall shorts, and path opens. A significant number of floating gate opens is also detectable. The floating gate defects escaping assured detection would be those in which the floating gate during test excitation produces voltages at the open gate(s) similar to the voltage of the non-defective circuit.

Microelectromechanical systems fabrication and packaging may induce parametric defects which have to be efficiently diagnosed to improve fabrication yield and device reliability. In this work, the possibilities of diagnosing single parametric defects in dual axis IC accelerometers are explored. The proposed method is a reuse of a mixed-signal diagnosis strategy based on Lissajous compositions. It consists of a dynamic correlation of the two orthogonal output signals of the device. This leads to a Lissajous trace which is able to manifest parametric deviations. Several device parameters have been studied and characterized under different deviation levels. The definition of a metric and the evaluation of its diagnosis efficiency is used to optimize the diagnosis procedure against noisy measurements. The method has been experimentally applied to diagnose the misalignment degree in a commercial dual axis accelerometer. The Lissajous characterization of the defect is illustrated and experimental results are reported. Misalignment diagnosis results show the viability of the proposal.

This work proposes a criterion to select a subset of indirect measurements avoiding redundant information. The key idea of the proposal is to reduce the actual number of measurements to be performed to those strictly providing relevant information to the testing procedure, therefore keeping the incurred misclassification costs at acceptable levels. The proposed method selects the measurements presenting minimum mean and spread of the correlations between all the possible pairs formed by the measurements within the target subset. In order to show the viability of the proposal, the method has been applied to select a subset of indirect measurements in several analog filters affected by parametric variations. The obtained misclassification levels using the subset of measurements indicated by the proposed method are considerably low. In average, the number of misclassified circuits using the selected subset are within the first 2.4% of the misclassification population obtained when all the possible subsets are explored, therefore validating the proposal.

Indirect test strategies have risen as a promising solution to overcome the challenges encountered in analog and mixed-signal circuit testing and the ever increasing device verification costs. This work explores the possibilities of using multidirectional tessellations in the indirect measure space aiming to reduce false positive test outcomes. The key idea of the proposal is to use several rotated 2n-ary trees in order to tessellate and encode the indirect measure space along multiple directions. Such tessellations create a refinement in the highly non linear test decision boundary without the need of including more circuit samples within the training set. The trained trees, together with a strict test decision criterion, serve as a classifier during the production testing phase. The proposed multi-directional tessellation methodology has been applied to test a Biquad filter under the presence of parametric variations. Promising simulation results report considerable improvements in lowering test escape metrics by an average factor of 50 as compared to a single octree tessellation as well as low computational overhead.

Testing mixed-signal circuits is a challenging task requiring high amounts of human and technical resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure CUT information. In this work, the acceptance/rejection regions are encoded using octrees with arbitrary precision regardless of the complexity of the boundary separating these regions. The strategy relies on two phases: (1) A statistical training phase generates the circuit samples to encode the acceptance/rejection regions using octrees. (2) The testing phase corresponds to the actual production testing of the fabricated ICs. The first phase is performed only once and requires sufficient samples of each pass/fail region to generate the octree under realistic CUT variations. The second phase is fast and only requires to evaluate the octree using the measures of the tested IC. In order to illustrate the proposal, the method has been applied to test a band-pass Biquad filter. Successful simulation results are reported showing considerable advantages in terms of test application time.

Binning after volume production is a widely accepted technique to classify fabricated integrated circuits (ICs) into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell nonoptimal devices at lower rates, so adapting to customer’s quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time-consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly nonlinear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this paper functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases: 1) the training phase and 2) the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a support vector machine (SVM)-based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is $5\times $ times faster using octrees than using the SVM-based classifier.