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Spintronics is a new discipline in which the spin of the electron is used as an additional degree of freedom besides its electrical charge to build innovative electronic components. Magnetic materials can be used as spin polarizer/analyzer in association with semiconductors or insulators, resulting in hybrid CMOS/magnetic architectures. Magnetic Tunnel Junctions (MTJ) are the basic elements of a new kind of memory, called MRAM (Magnetic Random Access Memory). Besides MRAM, it has recently been shown that by combining MTJ and CMOS components, one can also develop new functionalities for logic devices. This paper aims at giving a general overview of these novel hybrid magnetic/CMOS architectures and the design tools required for their design.

In solid organic dielectrics subjected to high and non-uniform electric stress gradients, failure usually occurs by a mechanism called treeing. The type of damage which progresses through the dielectric under electric stress in dry environment is called electrical treeing. In extruded dielectrics, failures, which do not occur promptly but rather appear to be the result of an aging process, are most likely due to electrical treeing. Materials of different molecular structures have different degrees of resistance to failure by treeing.

Due to rapidly expanding networking industry demands, there is a corresponding need for high speed search capability, reduced power consumption and data masking within Content Addressable Memory (CAM) devices. These devices are used in applications requiring fast database searches. Image or voice systems, computer and communication systems are all CAM users. CAM have advantages in term of performance over other memory search algorithms. This is due to the simultaneous comparison of the desired information against the entire list of pre-stored entries. CAM have arrays designed to enable stored values to be located quickly by comparing input data to memory data to locate a match. This paper presents a design of a 18 Kb non-volatile Ternary Content Addressable Memory (TCAM) integrating Magnetic Random Access Memory (MRAM) devices. Magnetic Ternary Content Addressable Memory (MTCAM) can simplify conventional TCAM cell from sixteen transistors to 2 MRAM cells and 6 transistors. Furthermore, such device is intrinsically non volatile, e.g. power-failure-resistant. The MRAM cells are used both to store the information and to compare it (search) to the inputted data like an XOR logic function, whilst the CMOS part is used to detect and amplify the cell state.

The general purpose of spin-electronics is to take advantage of the spin of the electrons in addition to their electrical charge to conceive innovative electronic components. These components combine magnetic materials which are used as spin-polarizer or analyzer together with semiconductors or insulators. SPINTEC Laboratory works on the development of these components and their integration in innovative hybrid CMOS/magnetic architectures. We study in particular the use of magnetic tunnel junctions (MTJ) for the design of magnetic random access memories (MRAM), magnetic FPGA (MFPGA) and non-reprogrammable logical devices (transceivers, adders, decoders). The design of these hybrid architectures requires to develop electrical equivalent models of the magnetic elementary components (magnetic tunnel junctions, spin-valves, Hall crosses) compatible with SPICE-like simulators. Complete simulations of the hybrid devices are performed before experimental realization and testing.

International audience; Spintronics aims at extending the possibility of conventional electronics by using not only the charge of the electron, but also its spin. The resulting spintronic devices, combining the front-end CMOS technology of electronics with a magnetic backend technology, employ Magnetic Tunnel Junctions (MTJs) as core elements. With the intent of simulating a circuit without fabricating it first, a reliable MTJ electrical model which is applicable to the standard SPICE (Simulation Program with Integrated Circuit Emphasis) simulator is required. Since such a model was lacking so far, we present an accurate MTJ SPICE model whose magnetic state is written by using the Spin-Transfer Torque (STT) effect. This model has been developed in C language and validated on the Cadence Virtuoso Platform with Spectre simulator. Its operation is similar to those of the standard BSIM (Berkeley Short-channel IGFET Model) SPICE model of the MOS transistor and fully compatible with the SPICE electrical simulator. In order to illustrate the model performance, we studied the tunneling conductance and STT-driven magnetization dynamics by comparing our simulation results with theoretical macrospin calculations and results found in the literature.