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In this paper, we design a low noise amplifier to support ka-band satellite communication systems using 65-nm RFCMOS process. The proposed low noise amplifier is designed with high-gain mode and low-gain mode, and is designed to control the gain according to the magnitude of the input signal. In order to reduce the power consumption, the supply voltage of the entire circuit is limited to 1 V or less. We proposed the gain control circuit that consists of the inverter structure. The 3D EM simulator is used to reduce the size of the circuit. The size of the designed amplifier including pad is 0.33mm2. The fabricated amplifier has a -7 dB gain control range in 3 dB bandwidth and the reflection coefficient is less than -6 dB in high gain mode and less than -15 dB in low gain mode. [ABSTRACT FROM AUTHOR]

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure. [ABSTRACT FROM AUTHOR]

In this paper, we design a power amplifier to support quad-band in wireless communication devices using RF CMOS 180-nm process. The proposed power amplifier consists of low-band 0.9, 1.8, and 2.4 GHz and high-band 5 GHz. We proposed a structure that can support each input matching network without using a switch. For maximum linear output power, the output matching network was designed for impedance conversion to the power matching point. The fabricated quad-band power amplifier was verified using modulation signals. The long-term evolution(LTE) 10 MHz modulated signal was used for 0.9 and 1.8 GHz, and the measured output power is 23.55 and 24.23 dBm, respectively. The LTE 20 MHz modulated signal was used for 1.8 GHz, and the measured output power is 22.24 dBm. The wireless local area network(WLAN) 802.11n modulated signal was used for 2.4 GHz and 5.0 GHz. We obtain maximum linear output power of 20.58 dBm at 2.4 GHz and 17.7 dBm at 5.0 GHz. [ABSTRACT FROM AUTHOR]

In this study, we proposed an asymmetric differential inductor to improve the linearity of differential power amplifiers. Considering the phase error between differential signals of the differential amplifier, the location of the center tap of the differential inductor was modified to minimize the error. As a result, the center tap was positioned asymmetrically inside the differential inductor. With the asymmetric differential inductor, the AM-to-AM and AM-to-PM distortions of the amplifier were suppressed. To confirm the feasibility of the inductor, we designed a 2.4 GHz differential CMOS PA for IEEE 802.11n WLAN applications with a 64-quadrature amplitude modulation (QAM), 9.6 dB peak-to-average power ratio (PAPR), and a bandwidth of 20 MHz. The designed power amplifier was fabricated using the 180-nm RF CMOS process. The measured maximum linear output power was 17 dBm, whereas EVM was 5%. [ABSTRACT FROM AUTHOR]

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%. [ABSTRACT FROM AUTHOR]

Endoscopic retrograde cholangiopancreatography (ERCP)-related perforations of the duodenum are rare but serious complications. Some ERCP-related perforations can be successfully managed without surgery. However, the presence of duodenal perforation may lead to premature termination of the ERCP and need for additional procedure such as percutaneous biliary drainage. If the ERCP-related perforation is identified early during the procedure, primary closure of the perforation can be attempted first or after completion of ERCP. We report two cases of duodenal perforation during ERCP in which ERCP was successfully completed after primary closure of the perforation. [ABSTRACT FROM AUTHOR]

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using 0.18 μm standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage’s different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88～5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage. [ABSTRACT FROM AUTHOR]