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The S vacancy at metal/ MoS 2 interface plays a much important role than the semiconductor itself. In this work, the influence of different configurations of S vacancy concentrations on the effective work function and band structure of the Au/ MoS 2 interface has been investigated systematically using first-principles calculations. The study specifically explores the effective work function of the Au/ MoS 2 interface, the deviation of interface effects from the vacuum work function, and the dipole moment caused by interface charge transfer. The results reveal that the electronic work function of Au/ MoS 2 increases with the increase in S vacancy concentration, but the rate of increase tends to slow down with higher S concentrations. The variation in the effective work function of the Au/ MoS 2 interface may be attributed to the presence of S vacancies and the exposure of Mo atoms. S vacancies lead to a reduction in the Schottky barrier, resulting in increased leakage current. The Fermi pinning caused by S vacancy concentration and location is also observed. The results obtained in this study can serve as a theoretical foundation for applications in electronic devices that rely on metal/ MoS 2 contact. [ABSTRACT FROM AUTHOR]

Polymer dielectrics with excellent capacitive performance are urgently needed in advanced electrical and electronic systems. However, due to the dramatic increase in the conduction loss, the energy density and efficiency of polymers degrade severely at elevated temperatures, limiting their application in harsh environments up to 150 °C. Herein, an all-organic polyurea (PU)/polyetherimide (PEI) blend film is designed to prepare high-temperature polymer dielectric. It is found that carrier traps can be introduced by blending, and the hydrogen bond between PU and PEI increases the trap depth, leading to suppressed leakage current and enhanced breakdown strength, thus improving the energy storage performance. PU/30%PEI exhibits a high discharged energy density of ∼3.74 J/cm3 with an efficiency higher than 90% at 150 °C, which is 78% and 70% higher than pristine PU and PEI, respectively. This work provides a facile strategy to improve the energy storage performance of polymer dielectrics by introducing deep traps through blending. [ABSTRACT FROM AUTHOR]

This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. IDS = f(VGS) and IDS = f(VDS) measurements are conducted at 25 and 150 °C, respectively, in forward and blocking modes. The gate recessed depth (50, 150, and 350 nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom (μbot) and the entire sidewall region mobility (μT), without distinction from the corner. The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner (μcorner) and sidewall (μSW) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one (μcorner < μSW) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance (RON). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain–source leakage current in reason of a lower gate electrostatic control. Technology Computer Aided Design (TCAD) simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology. [ABSTRACT FROM AUTHOR]

Amorphous composite polymers are widely used as insulators in microelectronics due to their high dielectric strength, mechanical robustness, and thermal stability. However, organic–inorganic composite systems suffer from undesirable performance and accelerated degradation due to leakage current ( J Tot ). Unfortunately, the underlying mechanism of J Tot and its components (e.g., ionic and electronic constituents) are inadequately understood, particularly in extreme use conditions (e.g., high humidity and temperature). In this study, we use numerical simulation and experimental J Tot data (in amorphous epoxy polymer with silica fillers) to (i) unify the electrostatic model for J Tot in composite polymers, (ii) illustrate that the early part of J Tot (i.e., external current) is primarily due to the image charge associated with ion transport/ localization ( J ion ) near the metallic contacts, (iii) demonstrate that the accumulated counter-ions reduce the barrier for electronic charge injection (by band bending) and facilitate electronic injection from the metals ( J elec ), and (iv) provide an algorithm for the in situ ion transport characterization of composite insulators by exploiting J ion . This work provides new insights regarding the leakage current mechanism and how it can be used as a probe into the complex transport mechanisms of the composite material. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

In this work, bottom-Schottky-structure InGaZnOx (IGZO) Schottky barrier diodes (SBDs) with sputtered PtOx anodes were fabricated and annealed in oxygen at different temperatures. Critical parameters and negative bias stress (NBS) stability of SBDs with different annealing temperatures are investigated. With the annealing temperature increases, the barrier height and rectification ratio of the SBDs exhibited a rising-then-declining trend, while the ideality factor slightly increased until 200 °C. The SBDs show up overall reliability except for a leakage current rising trend under light, which can be attributed to free electron generation from the ionized oxygen vacancy. Among all the SBDs, the 175 °C annealed ones exhibited the best overall performance, including a high barrier height of 0.89 eV, an ideality factor of 1.14, and a large rectification ratio of over 108. Compared to the initial SBDs, the annealed ones showed up great improvement in NBS stability except for the 200 °C annealed ones, which was permanently degraded and not able to recover to original states. According to experimental result analysis and IGZO material characteristics, a stability model based on the subgap trap transition from V O 2 + to VO and new V O 2 + creation was proposed, which applies to both the short-term and long-term NBS tests. The results above demonstrate that oxygen annealing at appropriate temperature is an effective method to improve both device performance and NBS stability for PtOx–IGZO SBDs. [ABSTRACT FROM AUTHOR]

β-Ga2O3 is of great interest for power electronic devices with efficiency beyond current generation Si, 4H-SiC, and GaN devices due to its large breakdown electric field of ∼8 MV/cm. However, taking advantage of this large field strength in power diodes requires device engineering to reduce leakage current that arises at high electric fields. In this work, we elucidate the current transport mechanisms of metal/TiO2/β-Ga2O3 diodes, showing that thermionic emission is an excellent descriptor of current in forward and reverse bias. It is shown that tunneling current is greatly suppressed, and consequently, that the diodes with the TiO2 interlayer can block orders of magnitude more current than Schottky barrier diodes with the same barrier heights. Finally, a 1200 V diode structure is designed based on the derived transport models, and calculated on- and off-state current characteristics closely align with those of state-of-the-art 4H-SiC commercial devices, indicating that this diode structure is ready to enable the realization of β-Ga2O3 power diodes. [ABSTRACT FROM AUTHOR]

This study presents a comprehensive investigation of the impact of the deposition temperature on the HfxZr1−xO2 (HZO) ferroelectric layer of ferroelectric random access memory with TaN electrodes. This investigation mainly focuses on its electrical characteristics and compares the differences. It is revealed that the deposition temperature plays a crucial role in determining the crystal structure of HZO, which can exhibit a combination of tetragonal and orthorhombic phases or exist solely in one of the two phases. Furthermore, the grain size of HZO varies with the deposition temperature. These findings correspond well to the electrical measurement results, including leakage current, polarization, capacitance, and reliability tests. The study tracks the phase transition process during the operation of switching cycles when the phase transition process can be monitored as well. To better understand the observed differences, physical models that shed light on the underlying mechanisms affected by deposition temperature are proposed at the end of the article. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

We have attained low leakage current, low interfacial traps, and low border traps by effectively passivating both p- and n-In0.53Ga0.47As (InGaAs) surfaces using the same gate dielectrics of ultra-high-vacuum deposited Al2O3/Y2O3. Gate leakage currents below 2 × 10−7 A/cm2 at gate fields of ±4 MV/cm were obtained after 800 °C rapid thermal annealing, demonstrating the intactness of the interface and heterostructure. Negligibly small frequency dispersions in the capacitance–voltage (C–V) characteristics of p- and n-type metal-oxide-semiconductor capacitors (MOSCAPs) were obtained from accumulation, flatband, to depletion as measured from 300 K to 77 K, indicative of low border and interfacial trap density; the C–V frequency dispersions in the accumulation region are 1.5%/dec (300 K) and 0.19%/dec (77 K) for p-InGaAs, and 2.2%/dec (300 K) and 0.97%/dec (77 K) for n-InGaAs. Very low interfacial trap densities (Dit's) of (1.7–3.2) × 1011 eV−1cm−2 and (6.7–8.5) × 1010 eV−1cm−2, as extracted from the conductance method, were achieved on p- and n-InGaAs MOSCAPs, respectively. [ABSTRACT FROM AUTHOR]

It is a formidable challenge to find the minority carrier recombination lifetime in low-dimensional devices as low-dimensionality increases the surface recombination rate and often reduces the recombination lifetime to a scale of picoseconds. In this work, we demonstrated a simple but powerful method to quantitatively probe the minority carrier recombination lifetime in silicon nanowires or microwires by fitting the experimental photoresponses with our recently established analytical photoresponse principle of photoconductors. The nanowires were passivated with small molecules and Al2O3 to suppress surface recombination, which will increase the minority recombination lifetimes. As expected, the minority carrier recombination lifetime found by this approach increases by orders of magnitude. These wires were also made into PIN diodes, the leakage of which was reduced at least 1 order of magnitude after surface passivation by Al2O3. The minority recombination lifetime found from the leakage current of these devices is largely consistent with what we found from our analytical photoresponse principle. As a further step, we performed scanning photocurrent microscopy to find the minority diffusion length from which we found that the minority recombination lifetime is close to what we found from the analytical photoresponses. In short, this work validated that our analytical response principle is a reliable method to find the minority recombination lifetime in low-dimensional semiconductors. [ABSTRACT FROM AUTHOR]

We have analyzed and modeled the reverse-biased gate leakage current in a Schottky-gate AlGaN/GaN high electron mobility transistor. While the Poole–Frenkel emission current along conductive threading dislocations dominates at low negative gate bias, the trap-assisted tunneling of thermally energized electrons and the thermal emission of electrons from threading dislocations aided by dislocation-related states at multiple energy levels within the AlGaN bandgap are dominant at moderate to large reverse bias. Additionally, deep trap levels of high density localized near the gate/AlGaN interface cause significant leakage at 473 K at low to moderate reverse bias, which could be specific to the device we have analyzed. We extracted about 10 12 cm − 2 traps near the AlGaN/GaN interface from the difference of the barrier layer electric field profile obtained from the experimental high-frequency capacitance–gate voltage and the one needed for final matching. The thermionic- and the thermionic field-emission currents are considerably low; the latter, however, dominates in the defect-free case. Finally, the simulation framework we developed here helped us identify various conduction mechanisms contributing to the reverse-biased gate leakage and the density and electronic structure of the responsible defects. [ABSTRACT FROM AUTHOR]

Lead-free piezoelectric (K, Na)NbO3 (KNN) is considered one of the promising candidates for the replacement of Pb(ZrxTi1−x)O3. Several studies underlined the issue of K and Na volatility with increasing deposition temperatures, leading to high leakage currents in thin films, which still represents a major drawback for applications. This paper shows how epitaxial growth with concomitant preferred orientation of KNN films on niobium-doped strontium titanate (Nb:STO) depends on growth temperature and substrate strain. A preferred out-of-plane polar (001) orientation of KNN is obtained at high temperatures (>600 °C), while (100) orientation is dominant for lower ones. The (001) orientation is forced out-of-plane due to the sizeable in-plane stress derived from a negative lattice mismatch of pseudo-cubic KNN with respect to the underlying cubic (001) Nb:STO substrate. Moreover, we show that K-Na deficiency and high leakage of epitaxial KNN films deposited at high temperatures are accompanied by the appearance of a pattern of orthogonal spontaneous ferroelectric domains aligned to the [100] and [010] directions of Nb:STO. This pattern, visible in secondary electron microscopy, piezoforce response microscopy, and conductive atomic force microscopy images, is uncorrelated to the surface morphology. Supported by reciprocal space mapping by x-ray diffraction, this phenomenon is interpreted as the result of strain relaxation via ferroelectric domain formation related to K-Na deficient films displaying a sizable and increasing compressive strain when grown on Nb:SrTiO3. Our findings suggest that strain engineering strategies in thin films could be used to stabilize specific configurations of piezo- and ferroelectric domains. [ABSTRACT FROM AUTHOR]

A non-destructive method for detecting sub-micrometer-sized micropipes on an entire wafer surface is investigated. Since it is difficult to detect sub-micrometer-sized micropipes due to their small core size, a non-destructively and accurately detecting method is required. To solve the issue, we focus on a characteristic depression generated around micropipes, namely, line-shaped depressions. In this paper, the location of line-shaped depressions is identified by using optical inspection, and the line-shaped depressions are distinguished whether micropipes exhibit line-shaped depression or not by using mirror electron microscope observation as high-resolution inspection. The accuracy of the distinction results is confirmed by scanning electron microscope observation, and electrical characteristics of the P–N diode are fabricated using the inspected wafer. Furthermore, the sub-micrometer-sized micropipes are observed at the sites of leakage current identified by emission microscopy. Additionally, device simulation of the blocking-voltage characteristics of P–N diodes suggests that the increase in leakage current depends on the electric field at the sub-micrometer-sized micropipes, regardless of their core size. [ABSTRACT FROM AUTHOR]

We investigated leakage current characteristics affected by crystallinity and domain wall currents of epitaxial Bi5Ti3FeO15 (BTFO) thin films on Nb-doped SrTiO3 substrates. Highly a-oriented BTFO thin films, highly c-oriented BTFO thin films, and BTFO thin films with a mixture of a-oriented and c-oriented crystallinity were prepared by controlling the substrate temperature and the pulsed laser deposition deposition rate. Highly c-oriented BTFO thin films exhibited the best leakage current characteristics because the Bi2O2 layers were placed perpendicular to the c-axis to reduce leakage currents. The BTFO thin films with a mixture of a-oriented and c-oriented crystallinity showed larger leakage currents compared to highly c-oriented BTFO thin films. The current domains of the BTFO thin films corresponding to the ferroelectric domain structures were observed by a conducting atomic force microscope, and it was observed that leakage currents were formed around the domain walls. In particular, the largest leakage currents are formed at the boundaries of c-oriented domains and a-oriented domains, and these domain boundaries confirmed that the BTFO thin films with a mixture of a-oriented and c-oriented crystallinity were responsible for the largest leakage currents. [ABSTRACT FROM AUTHOR]

Due to the erratic switching phenomenon of the Si avalanche bipolar junction transistor (ABJT) in the Marx bank circuit (MBC), an explanation of the leakage current trigger mode in the overvoltage state with a lack of displacement current is proposed. There are random switching properties (i.e., switching or non-switching) in the ABJT with emitter–base shorted, triggered by a voltage ramp to the overvoltage state temporarily with dV/dt rate close to 0 V/ns. The experimental conditions and characteristics of erratic behaviors are summarized. The optical visualization of the current channel in an erratic switching state is obtained, and the corresponding physical model of the leakage current trigger mode is established. It shows that the switching event occurs with the change in the position of the conductive channel. The process of emitter electron injection is caused by the leakage current in the overvoltage state instead of the displacement current. Meanwhile, the intensity of this trigger mode is weak, and the instability of the leakage current may cause the failure of switching. The study of erratic switching is of great significance for the working reliability of MBCs and failure analysis of ABJTs. The proposed explanation is validated by the agreement between the simulation results and the experimental observations. [ABSTRACT FROM AUTHOR]

We have studied the aging-induced degradation effect and the related mechanism of blue and ultraviolet (UV) laser diodes (LDs). First of all, the F parameter value, leakage current, and yellow luminescence intensity of LDs all increase after 24 h of the aging process, indicating that one of the reasons for the degradation of UV LDs may be the increase of the non-radiative recombination center in the material. Second, irreversible damage may be found on the front cavity surface of the UV and blue LDs. Due to the large UV photon energy, water molecules in the environment atmosphere are ionized to form OH− ions, which combine with dust in air to form SiO2 sediments and then attach to the front cavity surface. In addition, a large photon energy may cause damage to the anti-reflection film on the front cavity surface and lead to a too-high local temperature near the cavity surface, resulting in molten Ga droplets. Both sediment and the precipitation of molten GaN on the cavity surface will directly affect the function of the front cavity surface and the output power of the LD. In order to improve the reliability of the GaN-based UV LDs, it is necessary to reduce the density of material defects, select more stable coating materials on cavity facets, and improve the sealing property of the device package. [ABSTRACT FROM AUTHOR]

This study investigates the structural, electrical, leakage current, and magnetic characteristics of the double perovskite material Nd2NiTiO6 synthesized through the sol–gel citrate auto‐ignition method. The Rietveld refinement of the X‐ray diffraction patterns confirmed a monoclinic symmetry (space group P21/n) with an ordered arrangement of alternate NiO6 and TiO6 octahedra. Impedance spectroscopic analysis exhibited the material's non–Debye‐type relaxation mechanism and semi‐conductive nature. AC conduction analysis revealed that the conduction of charge carriers occurs via the nonoverlapping small polaron hopping mechanism, consistent with Mott's variable range hopping model. Temperature‐ and frequency‐dependent dielectric measurements were interpreted using the Maxwell–Wagner interfacial polarization model. The analysis of thermal‐ and field‐dependent leakage currents established that conduction is ohmic, which the Schottky barrier model explains. Studies on magnetization ruled out the presence of magnetic ordering connected to indirect interaction between Ni2+ ions via Ti4+ ions and the rare‐earth cation (Nd3+) moment. [ABSTRACT FROM AUTHOR]

Incorporating specific defects into complex oxides facilitates the exploration of exotic phenomena and novel functionalities based on the intricate coupling between the defects and lattice/charge. However, methods for maximizing the density of specific defects while enhancing the desired properties have been rarely explored. In this study, the effect of N+ ion bombardment‐driven specific defects on the properties of bismuth ferrite (BFO) thin films was investigated. Furthermore, atomic structure characterization and computational processing revealed the displacement and orientation of the Fe atoms, which are linearly related to the degree of polarization. The ion bombardment introduced deep‐level trap states within the lattice, leading to a significant reduction in the leakage current and improved insulation performance of the films. By precisely engineering the defect content through N+ ion bombardment, the pure BFO thin films with remarkable and stable ferroelectric properties (remnant polarization, Pr = ∼116.8 µC·cm−2; leakage current, J = ∼1.5 × 10−8 A·cm−2) were fabricated. This innovative defect engineering‐based approach enables the customization and optimization of local ferroelectric order parameters, thereby establishing a solid foundation for designing functionalities across various functional material systems. [ABSTRACT FROM AUTHOR]

Electric heaters based on functional materials and innovative designs have been developed for various applications. In this paper, we propose a soft dielectric heater (SDH) using polyvinyl chloride-gel (PVC-gel) as the dielectric heater and hydrogel as stretchable electrodes. Under an AC voltage, the leakage current in the PVC-gel leads to continuous injection and discharge of charges, causing the polarized plasticizers and flexible PVC chains to vibrate and collide, thereby generating heat through dielectric heating. Furthermore, the SDH generates a uniform temperature distribution even under strains up to 400%. Besides, high transmittance over 86% across the visible range renders it suitable for wearable or skin-mountable heaters from an esthetic viewpoint. Its capacitor-like structure achieves a scalable design, enabling extension from a singular cell to a row/column addressable and pixelated array of heaters. The 5 × 5 SDH array can deliver varied thermal information and sensations while maintaining performance even when stretched. [ABSTRACT FROM AUTHOR]

The use of the organic semiconductor copper hexadecafluorophthalocyanine (F16CuPc) in WSe2 based heterostructure field-effect transistors (FETs) is shown to result in a large reduction in electron current while not significantly impacting the hole current. This approach is promising for use in p-channel FETs in which electron transport is undesirable and increases leakage currents and power dissipation in the off-state. The reduction in on-state electron currents, by up to three orders of magnitude, is due to the transfer of electrons to the low-mobility states in F16CuPc due to the greater electron affinity of the organic semiconductor compared to WSe2. The off-state currents under a drain bias are reduced by more than four orders of magnitude due to the effective suppression of electron currents. This is a result of the formation of type II heterostructure between F16CuPc and WSe2. Electrons in this heterostructure FET will preferentially transfer to F16CuPc, while holes will tend to remain in the high mobility WSe2 layer. This effect is more marked in monolayer WSe2 based FETs compared to multilayer WSe2 FETs due to a larger difference in electron affinities with respect to F16CuPc. Also, the magnitude of electron current suppression was further enhanced when F16CuPc is deposited only on a part of the channel near the source of WSe2 +F16CuPc FETs. [ABSTRACT FROM AUTHOR]

AlGaN/GaN Schottky barrier diodes (SBDs) with a low work function W anode and a high work function Ni field plate on sapphire substrates are investigated in this Letter. The low work function metal W leads to the low turn-on voltage, while the high work function metal Ni maintains the leakage current and increases the breakdown voltage. An ultralow turn-on voltage of 0.23 V determined by the positive fixed charge at the AlGaN/Si3N4 interface is achieved in this W/Ni SBD. More importantly, benefitting from the dual-metal anode/field plate structure, the on-resistance decreases from 7.99 to 5.53 Ω mm, and the breakdown voltage increases from 493 to 1219 V. In addition, the turn-on voltage decreases less than 57%, and the on-resistance increases less than 186% at a high temperature up to 120 °C. The W/Ni SBD with a cathode–anode length of 18 μm and a field plate length of 4 μm shows a low turn-on voltage of 0.23 V, a low on-resistance of 5.53 Ω mm, a leakage current of 0.65 mA/mm, and a high breakdown voltage of 1.21 kV, indicating a great potential for power electronic applications. [ABSTRACT FROM AUTHOR]

GaN Schottky barrier diodes (SBDs) have been investigated for a variety of power applications. However, the problems of low on/off current ratio and high threshold voltage caused by the difficult high-quality doping restrict its utilization in power devices. In this work, quasi-vertical MoS2/GaN SBDs with Metal-Oxide-Semiconductor (MOS) structure have been proposed. The MOS structure is formed by the part of anode (Ni/Au) over the Al2O3, Al2O3, and monolayer MoS2. Monolayer MoS2 exhibits n-type doping and p-type doping under forward bias and reverse bias, respectively, which realizes an adjustment in the Fermi level of the monolayer MoS2, resulting in a change in the resistance of the SBDs. The as-prepared SBDs present a high on/off current ratio of 2.40 × 1011, a low threshold voltage of 0.55 V at 1 A/cm2, and a low reverse leakage current of 2.50 × 10−10 A/cm2 at −1 V. This work shows that the MOS-structured MoS2/GaN SBDs are promising for next-generation power electronics. [ABSTRACT FROM AUTHOR]

Multilevel inverters produce waveforms that lead to better power quality. Switched-capacitor inverters are one kind that is capable of generating boosted voltage and encourages a single-stage grid-tied inverter solution. In this paper, a four-times boost nine-level inverter with fewer switches is presented in standalone and grid-connected mode. Two switched capacitors, along with eleven switches and one diode, are employed to generate the required boosted nine-level output. The circuit modulation allows self-charging of the capacitors, with the first capacitor charging to the DC source and the second charges to twice of it by shunting it with the combination of the first capacitor voltage and the DC source. This inverter's application can be as a solar PV microinverter due to its fewer components and small filter requirement. The topology is compared with the single-source nine-level inverters and exhibits the lowest cost of all quadruple boost inverters. The presented inverter operation is verified in Simulink and validated on the laboratory prototype. Further, to minimize the leakage current, the circuit is modified accordingly and tested in a hardware-in-the-loop environment. [ABSTRACT FROM AUTHOR]

Highlights In the present work, the impact of corona aging on the dielectric, thermal, and surface properties of silicone rubber filled with different nanofillers such as alumina (Al2O3), aluminum trihydrate (ATH), boron nitride (BN), and titania (TiO2) are studied. The surface degradation of the silicone rubber nanocomposites after corona aging is evaluated through contact angle measurement, atomic force microscopy (AFM) studies, and by water droplet‐initiated corona inception voltage studies. Alumina filled silicone rubber shows less reduction in surface and hydrophobic properties after corona aging. Water droplet initiated corona inception voltage (CIV) under negative DC voltage is much higher than under positive DC and AC voltages. Al2O3/TiO2‐ filled silicone rubber samples show better CIV performance. The Dielectric Response Spectroscopy (DRS) indicates that TiO2 filled silicone rubber insulating material possesses higher permittivity at lower frequencies. Boron nitride added composites have high thermal conductivity whereas ATH filled silicone rubber composites shows higher decay rate, as observed through laser‐induced thermography studies. A significantly high surface leakage current is observed in all samples after corona aging. The Space Charge Limited Current (SCLC) studies clearly indicate that inclusion of nano‐fillers resulted in an increase in crossover voltage and trap density values compared to base silicone rubber. Al2O3 filled silicone rubber exhibits lower surface roughness even after corona aging. High thermal conductive composites show better performance even after corona aging. ATH, and BN filled silicone rubber have improved thermal conductivity by 35.2% and 76.3%. TiO2 filler added silicone rubber exhibits high permittivity with low tan δ. Al2O3 filled silicone rubber has minimal surface and volume leakage current Crossover voltage and the trap density get enhanced on addition of fillers to the base polymer. [ABSTRACT FROM AUTHOR]

High-k oxide dielectric films are indispensable for low-power-consumption oxide thin-film transistors (TFTs) applied in advanced and portable electronics. However, high-quality oxide dielectric films prepared by solution process typically require sophisticated processes and long thermal annealing time, severely limiting both the throughput manufacturing and cost-effectiveness. In this study, the influence of different heating-up methods on the surface morphology and dielectric properties was systematically investigated. Gradient heating-up method could not only substantially improve the surface morphology and quality of high-k ZrO2 films but also efficiently shorten the annealing time. The gradient heating-up process was further designed on the basis of thermal behavior of the xerogel-like precursor, which successfully realize the preparation of high-quality ZrO2 films with an annealing time of 5 min (i.e. the efficiency of thermal treatment increased by about 89%). The ZrO2 film presented excellent dielectric properties, including a low leakage current density of ∼10−8 A cm−2 (at 2 MV cm−1), a large areal capacitance of 169 nF cm−2 and a high dielectric constant of 20.41 (1 MHz). Furthermore, InSnZnO TFT based on the ZrO2 gate dielectrics shows an acceptable device performances, such as a high carrier mobility of 2.82 cm2 V−1 s, a high on/off current ratio of ∼105 and a low subthreshold swing of 0.19 V decade −1 at a low operation voltage of 5 V. This work provide a highly promising approach to fabricate high-quality solution-processed high-k oxide dielectric films employed for large-scale and low-power-consumption electronics. [ABSTRACT FROM AUTHOR]

The influence of isovalent substitution at B-site by Ge4+ on the dielectric constant and dielectric losses of (Na 0.5 Bi 0.5)TiO 3 has been experimentally investigated. The compositions (Na 0.5 Bi 0.5)(Ti 1-x Ge x)O 3 (x (mol) = 0.00, 0.01, 0.03, and 0.05) were fabricated using the solid-state reaction (SSR) method, with a sintering temperature of 1150 °C for 3 h in air. Rietveld refinement revealed that the phases had a rhombohedral structure and belong to the R 3c space group. Ge4+ substitution inhibits grain growth and improves dielectric properties, with optimized permittivity. Simultaneously, dielectric losses are reduced at both room temperature and elevated temperatures. At room temperature and 1 kHz, it is approximately (tan(δ) ≈ 0.17) for x = 0.03, which is significantly lower than that of NBT (tan(δ) ≈ 0.61), reaching a minimum of 0.02 at 310 °C and 1 MHz. Leakage current is also optimized after Ge4+ modification. Modelling of Nyquist diagrams using an electrical model indicated two contributions: grains and grain boundaries. These results suggest that Ge4+ substitution in the NBT compound could open new possibilities for its application in the manufacturing of capacitors with improved properties. [Display omitted] [ABSTRACT FROM AUTHOR]

In this work, the influence of the Fe and Fe/C co-doped buffer on the AlGaN/GaN HEMTs is systematically investigated and compared. Due to the pronounced Fe tail in the unintentionally doped layer of the Fe-doped buffer compared to the Fe/C co-doped buffer, and the utilization of a two-step C doping process in the Fe/C co-doped buffer, it results in effectively reducing leakage current and increasing breakdown voltage without sacrificing saturation current and peak transconductance. Meanwhile, the RF characteristics of the Fe/C co-doped buffer are also superior to the Fe-doped buffer. More importantly, Drain Transient Current measurements indicate that the current collapse in the Fe/C co-doped buffer is smaller than that in the Fe-doped buffer. Through simulation analysis, the reason was identified: In the near-channel region, the weaker Fe tail effect in Fe/C co-doped buffer leads to a lower acceptor trap ionization. When the concentration of C exceeds 1 × 1016 cm−3, the ionization of traps introduced by Fe is suppressed. Additionally, the two-step C impurity distribution in the Fe/C co-doped buffer design modulates the electric field and potential, reducing the effective range of the electric field and potential, thereby effectively reducing the trap effects. These results are highly meaningful for the design of high-power amplifier epitaxial structures. [ABSTRACT FROM AUTHOR]

Summary: This paper targets to minimize the peak common mode voltage (CMV) in ultra sparse matrix converters (USMC) by applying new zero vectors for the space vector modulation technique (SVM). Conventional zero vectors in the SVM raise the peak CMV by 42.23%. An increased magnitude of CMV is associated with the occurrence of leakage current, hence resulting in insulation degradation. So, the reduction of peak CMV is necessary for USMC. The proposed method offers suitable switching arrangements using auxiliary shoot through (AST) switches to minimize the peak‐to‐peak CMV. This proposed method holds the advantages of the conventional method, like a wide range of modulation index and zero current switching at the rectifier side, and also reduces the CMV problem. This paper also provides a comparative analysis of the existing reported methods and the proposed method. The effectiveness of the proposed method is validated through both simulation and experimental results. [ABSTRACT FROM AUTHOR]

The conventional planar Metal-Oxide-Semiconductor FETs (MOSFETs) are being replaced with Fin Field-Effect Transistors (FinFETs) due to their improved ability to manage power dissipation, propagation delay, leakage current, and short channel effects. Process variability is an issue for planar MOSFETs, however the amount of dopant ions in FinFETs reduces device performance variability. In this study, a Static-Random Access Memory (SRAM) cell employing FinFET technology is designed using three MOS transistors. It is composed of two NMOS plus a single PMOS transistor. One NMOS acts as access transistor while the pull-up and pull-down functions are performed by remaining NMOS and PMOS transistors, respectively. The proposed SRAM cell is simulated using H-SPICE simulator and is compared with existing SRAM cell designs in terms delay, power consumption and transistor count. Performance analysis shows that the proposed SRAM Cell overcomes the constraint and achieves full swing storage of logic values between 0 and 1. This justifies the definition of static. Implementing a single-ended SRAM cell also has the benefit of simplifying the SRAM cell architecture, which also results in a reduction in area. [ABSTRACT FROM AUTHOR]

A picowatt CMOS voltage reference with dual outputs is proposed and simulated in this paper based on a standard 65 nm process. To compensate for the leakage current caused by parasitic reverse-biased PN junctions, an approach employing gate leakage transistors is proposed. Maintaining a maximal temperature coefficient (TC) of 20.40 ppm/°C across an extended temperature range of −10∼155 °C is achieved. Additionally, a voltage divider consisting of diode-connected NMOS transistors is introduced to obtain a lower voltage output without shunting the original branch or utilizing operational amplifiers. Moreover, a novel trimming block is utilized to optimize TC across different process corners. Simulation results demonstrate that a minimum power consumption of only 53.83 pW is achieved and the line sensitivity is 0.077%/V with 0.45 V to 2.5 V supply. The power supply rejection ratio of −76.70 dB at 10 Hz and V D D = 1.8 V is obtained. [ABSTRACT FROM AUTHOR]

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. [ABSTRACT FROM AUTHOR]

In this paper, a novel 120 V-class silicon Schottky contact super barrier rectifier with a deep isolated MOS trench in an epitaxial n-drift layer (DOT-SSBR) is studied through experiments, featuring the deep isolated MOS trenches (DOTs) in an epitaxial layer compared with conventional SSBR. The combination of SSBR and DOT obviously increase the breakdown voltage while preserving the significant advantages of SSBR. The pinching-off electric field effect by the DOTs in the epitaxial n-drift layer increases the average of electric field inside the drift layer and decreases the electric field on the mesa surface when the proposed DOT-SSBR is reversely biased. After the further optimization of the Schottky contact super barrier (SSB) parameters on mesa, the proposed DOT-SSBR maintains almost the same forward voltage, reduces the reverse leakage current at the reverse voltage of 50 V by approximately 10.0%, and greatly increases the breakdown voltage by approximately 38.6%, when compared with the conventional SSBR. The fabrication process, the measured high-temperature characteristics of forward I-V curves and reverse leakage current, and the measured reverse recovery current of the new device are also presented. An auxiliary simulation analysis to provide insight about the physics of the device is also presented. [ABSTRACT FROM AUTHOR]

As a prominent focus in high-voltage power devices, SiC MOSFETs have broad application prospects in the aerospace field. Due to the unique characteristics of the space radiation environment, the reliability of SiC MOSFETs concerning single-event effects (SEEs) has garnered widespread attention. In this study, we employed accelerator-heavy ion irradiation experiments to study the degradation characteristics for SEEs of 1.2 kV SiC MOSFETs under different bias voltages and temperature conditions. The experimental results indicate that when the drain-source voltage (VDS) exceeds 300 V, the device leakage current increases sharply, and even single-event burnout (SEB) occurs. Furthermore, a negative gate bias (VGS) can make SEB more likely via gate damage and Poole–Frenkel emission (PF), reducing the VDS threshold of the device. The radiation degradation behavior of SiC MOSFETs at different temperatures was compared and analyzed, showing that although high temperatures can increase the safe operating voltage of VDS, they can also cause more severe latent gate damage. Through an in-depth analysis of the experimental data, the physical mechanism by which heavy ion irradiation causes gate leakage in SiC MOSFETs was explored. These research findings provide an essential basis for the reliable design of SiC MOSFETs in aerospace applications. [ABSTRACT FROM AUTHOR]

The growing utilization of neural networks has led to a heightened focus on the hardware implementation of such networks. Security concerns associated with these implementations pose a significant challenge in this regard. Among these problems, the vulnerability of these networks against side-channel attacks such as power attacks can be mentioned. This paper presents a technique to enhance the resilience of hardware implementations of neural networks, particularly Hopfield neural networks, to mitigate the risks posed by power attacks. In addition to the fact that the proposed method makes it impossible to attack the network, it also reduces the power consumption of the entire circuit by reducing the leakage currents. The simulation results demonstrate that the proposed approach also achieves about a 10% reduction in energy consumption while concurrently improving the accuracy of the implemented associative memory by 1.1%. [ABSTRACT FROM AUTHOR]

Local control of superconducting circuits by high-impedance electrical gates offers potential advantages in superconducting logic, quantum processing units, and cryoelectronics. Recent experiments have reported gate-controlled supercurrent in Dayem bridges made of metallic superconductors, mediated by direct current leakage, out-of-equilibrium phonons, or possibly other mechanisms. However, a time-domain characterization of this effect has been lacking. Here, we integrate Dayem bridges made of niobium on silicon into coplanar waveguide resonators and measure the effect of the gate voltage at steady state and during pulsed operation. We consider two types of arrangements for the gate: a side-coupled gate and a remote injector. In both cases, we observe sizable changes in the real and the imaginary part of the constriction's impedance for gate voltages of the order of 1 V. However, we find striking differences in the time-domain dynamics, with the remote injector providing a faster and more controlled response. Our results contribute to our understanding of gate-controlled superconducting devices and their suitability for applications. [ABSTRACT FROM AUTHOR]

Diamond electronic devices have attracted significant interest owing to their excellent semiconducting properties. We recently demonstrated that eliminating surface-transfer doping enhances carrier mobility and achieves normally off behavior in diamond field-effect transistors (FETs) with a hexagonal boron nitride (h-BN) gate insulator. In our previous study, the gate electrode was overlapped onto the source/drain electrodes to prevent the increase in access resistance caused by excluding surface-transfer doping. However, it is known that gate overlap increases parasitic capacitance and gate leakage current. In this study, we developed a technique for self-aligning the gate electrode with the edge of h-BN using oblique-angle deposition. The diamond FET with a self-aligned gate electrode exhibits optimal FET characteristics, including high mobility of ≈ 400 cm2V−1s−1, low sheet resistance of 2.4 k Ω , and output characteristics demonstrating pinch-off behavior. Furthermore, the capacitance-voltage characteristics clearly indicate distinct ON and OFF states, validating the efficacy of this technique. This method enables the fabrication of diamond/h-BN FETs with no gate overlap and without increasing access resistance, making it a promising approach for developing high-speed, low-loss diamond FETs with a wide range of applications. [ABSTRACT FROM AUTHOR]

The THz photoresponse of four different structures of N‐ and Ga‐polar AlGaN/GaN plasma wave high‐electron‐mobility transistors (HEMTs) has been comparatively investigated. Based on these results, an improved N‐polar plasma wave HEMT detector is proposed: an AlGaN cap layer is introduced in the standard N‐polar HEMT, so as to obtain a lower gate leakage current, thus improving the operating characteristics of plasma wave HEMT. The results show that the responsivity of the improved N‐polar HEMT obtains a significant improvement and as the Al component of AlGaN cap layer increases, the noise equivalent power of the improved N‐polar HEMT has also been optimized. [ABSTRACT FROM AUTHOR]

We report an obvious improvement in the performance of a separated absorption charger-layer multiplication Ge/Si avalanche photodetector, achieved by passivating the sidewalls with a low-temperature remote oxygen plasma (ROP) treatment. The dangling bonds on the Ge surface can be efficiently passivated by the formation of an ideal Ge/GeO2 interface. With ROP passivation, the leakage current of the device shows a three- to fourfold decrease at 300 K, resulting in a dark current (I dark) of 3.5 × 10−6 A at 90% avalanche voltage (V br) and 3.4 × 10−7 A at punch-through voltage (V puhch-through) for the 26 μ m-diameter device. A reduction of over tenfold is demonstrated at 200 K and the passivation mechanism is revealed. In addition, a multiplication gain of 94 is obtained under 1550 nm illumination. The device with ROP passivation shows an improved gain bandwidth product of 190 GHz. The enhanced high-frequency response of the device with ROP passivation can be attributed to the alleviation of the retarding effect caused by the interface state on the sidewalls. Without using a trans-impedance amplifier, an opening eye diagram at 28 Gbps is demonstrated, indicating reliable device transmission performance. [ABSTRACT FROM AUTHOR]

In this study, Ga2O3 blocking layers (BLs) are used to improve the properties of dye-sensitized solar cells (DSSCs) by sputtering. The wide energy bandgap of Ga2O3 BLs not only can passivate the surface defects of TiO2 working electrodes but also can prevent the reverse leakage current from narrow energy bandgap of TiO2 working electrode. Compared with conventional narrow energy bandgap BLs, wide energy bandgap BLs are more effective in enhancing the power generation efficiency of DSSCs. After Ga2O3 BL deposited on TiO2 working electrode, the proportions of Ti3+ and Ti2+ can be reduced and the proportion of stable valence Ti4+ can be increased considerably. Moreover, the efficiency of DSSC with Ga2O3 BL increased from 4.06% to 5.72%. According to the results of electrochemical impedance spectroscopy analysis, the Ga2O3 BL increased the DSSC carrier lifetime from 0.17 to 0.35 ms and charge collection efficiency from 55.28% to 61.77%. Accordingly, the results of this study indicate that wide energy bandgap Ga2O3 BLs effectively prevent the formation of reverse leakage current, passivate working electrode defects in DSSCs, and are suitable for improving the performance of optoelectronic devices. [ABSTRACT FROM AUTHOR]

The sublayer thickness of superlattices, as a key factor affecting lattice integrity, interface defects, and strain, deserves in-depth studies about its impact on improving ferroelectric properties. This study described and analyzed the performance of HfO2/ZrO2 superlattices with various sublayer thicknesses. It can be concluded that the structure of the thicker layers will guide the trend of the phase composition of the entire device: when ZrO2 layers are thicker, the superlattices will exhibit antiferroelectricity due to the higher content of the tetragonal phase (t-phase); when HfO2 layers become thicker, the fraction of the monoclinic phase (m-phase) will increase, leading to a decrease in ferroelectricity and an increase in leakage current. In this way, the device with a 1:1 HfO2/ZrO2 thickness ratio was optimized to have the largest remanent polarization and the lowest leakage current. Maintaining the same thickness ratio of the HfO2/ZrO2 superlattices, it was found that HfO2/ZrO2 superlattices with thinner sublayers exhibited a larger remanent polarization (Pr) value due to increased interlayer distortion. On the contrary, the thicker sublayers reduced leakage current, which was beneficial for improving the device lifespan. [ABSTRACT FROM AUTHOR]

Ferroelectric tunnel junctions (FTJs) have gained substantial attention as emerging electronic devices such as nonvolatile memory and artificial synapse, owing to their low power consumption and nonvolatile properties. In this work, a 2D semiconductor (2DS)/α‐In2Se3/metal FTJ structure is proposed that combines a semiconductor ferroelectric material and a semiconducting electrode. The incorporation of 2DS not only enhances the barrier height modulation but also provides an effective approach to mitigate the thermionic current leakage. Notably, the proposed MoS2/α‐In2Se3/Ti FTJs exhibit both room‐temperature negative differential resistance (NDR) effect and high tunnel electroresistance (TER) exceeding 104 simultaneously. Furthermore, the versatility of this structure extends to several 2DS (including MoS2, PdSe2, and SnSe2) and graphene electrodes to rationalize both tunneling and thermionic current transport mechanisms. The proposed 2DS/α‐In2Se3/metal FTJs present great superiority over existing structures in terms of robustness, temperature independence, high TER, and versatility for various potential application scenarios. [ABSTRACT FROM AUTHOR]

In this study, arrays of μLEDs in four different sizes (5 × 5 μm2, 10 × 10 μm2, 25 × 25 μm2, 50 × 50 μm2) were fabricated using a flip-chip bonding process. Two passivation processes were investigated with one involving a single layer of SiO2 deposited using plasma-enhanced chemical vapor deposition (PECVD) and the other incorporating Al2O3 deposited by atomic layer deposition (ALD) beneath the SiO2 layer. Owing to superior coverage and protection, the double-layers passivation process resulted in a three-order lower leakage current of μLEDs in the 5 μm chip-sized μLED arrays. Furthermore, higher light output power of μLEDs was observed in each chip-sized μLED array with double layers passivation. Particularly, the highest EQE value 21.9% of μLEDs array with 5 μm × 5 μm chip size was achieved with the double-layers passivation. The EQE value of μLEDs array was improved by 4.4 times by introducing the double-layers passivation as compared with that of μLEDs array with single layer passivation. Finally, more uniform light emission patterns were observed in the μLEDs with 5 μm × 5 μm chip size fabricated by double-layer passivation process using ImageJ software. [ABSTRACT FROM AUTHOR]

The effects of Ta doping on the thermal and electrical properties of SnO 2 varistors were researched. The results showed that the thermal conductivity is 2.01 WK−1m−1, the nonlinearity coefficient is 43, and the leakage current density is 0.7 μA/cm2 when the Ta doping level reaches 0.2 mol%. According to the measurement results of the EPR, SEM/EDS, and XRD, the Ta dopant can reduce the oxygen vacancy concentration, which was generated during the sintering. The decline of the oxygen vacancy concentration reduces the phonon scattering, then the thermal conductivity of the varistors is improved. On the other hand, the reduction of the oxygen vacancy concentration elevates the barrier height, so the nonlinearity coefficient is improved and the leakage current density is declined. [ABSTRACT FROM AUTHOR]

Featured Application: The results obtained in this study can be applied to optimize engineering design, providing assistance in enhancing the durability of concrete structures. This study examined a newly developed environmentally friendly plant-based corrosion inhibitor (Xanthium sibiricum). The natural potential method, linear polarization method, steel weight loss method, and corrosion area method were employed to verify the inhibitor's effectiveness in chloride-containing concrete. The results indicated that Xanthium sibiricum elevated the natural potential of reinforcing steel in concrete, increased its self-corrosion potential, and reduced the self-corrosion current. After three months of curing, the corrosion rate of steel without an inhibitor was approximately 47.5% faster than the experimental group, with the steel loss rate about 40% more severe. The effectiveness of the inhibitor was influenced by increased chloride content in concrete. A two-dimensional multiphase ion transport model of reinforced concrete with realistic aggregate distribution was established using the finite element method (FEM). This model simulated chloride ion transport under typical civil engineering service environments—the coupled effects of a stray current and chloride environment. A predictive formula for the residual compressive strength of reinforced concrete was derived after corrosion under various voltages and chloride ion concentrations for a specific duration. In conjunction with a pump station project operating in a similar environment, the optimal dosage of the Xanthium sibiricum inhibitor for practical engineering was determined to be 2 g/L. At this dosage, the strength of reinforced concrete specimens increased by approximately 31.1%. Finally, a predictive formula for the residual compressive strength of reinforced concrete with an added inhibitor was obtained after corrosion under various voltages and chloride ion concentrations for a specific duration. The conclusions can enhance the durability and safety of concrete structures in similar projects, showing promising application prospects. [ABSTRACT FROM AUTHOR]

Magnetic shunts efficiently mitigate losses caused by leakage currents in the tank walls of power transformers. Transformer manufacturers frequently utilize vertical magnetic shunts positioned on the inside surfaces of the transformer tank walls. This study investigated the optimum use of horizontal shunts in a power transformer. A 50 MVA power transformer, manufactured on a commercial scale and featuring optimized vertical magnetic shunts integrated into the wall structure, was analyzed using the 3D finite element method for 100 ms at full load. Simulations for analyses were performed using a commercial ANSYS Electronics Desktop 2021 R1 FEM software program. The model's validity was demonstrated by verifying the analysis results with experimental tank loss values. Tank loss samples were obtained by analyzing the transformer tank for two milliseconds with vertical magnetic shunts only on the long front wall and the short side wall. Using these loss samples as a reference, parametric analyses were performed for two milliseconds with horizontal magnetic shunts only on the short side wall and only on the long front wall of the tank. A tank model with horizontal magnetic shunts of an appropriate location and size was obtained via the parametric analyses. This model was analyzed for 100 milliseconds at full load and compared with the experimental results of the transformer manufacturer's vertical magnetic shunt transformer. According to the results, a saving of 25.83% was achieved in the horizontal magnetic shunt volume compared with the vertical magnetic shunt volume. The maximum magnetic flux density was lower in the horizontal magnetic shunts, and the maximum current density was lower in the transformer tank with horizontal magnetic shunts. [ABSTRACT FROM AUTHOR]

Potassium sodium niobate (KNN) has attracted much interest as a promising lead-free ferroelectric candidate with its excellent physical properties for potential applications to novel nano-devices such as non-volatile ferroelectric memory. However, the use of KNN films in actual devices has been limited due to concerns in operational reliability (i.e., a polarization fatigue property). In this work, we demonstrate the enhancement of a polarization fatigue behavior in KNN thin films by doping of Mn ions. Ferroelectric fatigue is significantly suppressed in 0.4 mol% Mn-doped KNN films compared with pure KNN films. The amounts of mobile charged defects (e.g., oxygen vacancies and hole carriers produced with cation vacancies) are reduced in the presence of multivalent Mn dopants resulting in a decrease of leakage current density. The reduction of charged defect density can weaken the domain wall pinning effect enabling the polarization fatigue to be suppressed in KNN films. Our work is of practical interest for realizing lead-free ferroelectric memory devices with high performance. [ABSTRACT FROM AUTHOR]

Piezoelectric and ferroelectric wurtzite are promising to reshape modern microelectronics because they can be easily integrated with mainstream semiconductor technology. Sc doped AlN (Al1‐xScxN) has attracted much attention for its enhanced piezoelectric and emerging ferroelectric properties, yet the commonly used sputtering results in polycrystalline Al1‐xScxN films with high leakage current. Here, the pulsed laser deposition of single crystalline epitaxial Al1‐xScxN thin films on sapphire and 4H‐SiC substrates is reported. Pure wurtzite phase is maintained up to x = 0.3 with ≤0.1 at% oxygen contamination. Polarization is estimated to be 140 µC cm−2 via atomic scale microscopy imaging and found to be switchable via a scanning probe. The piezoelectric coefficient is found to be five times of the undoped one when x = 0.3, making it desirable for high‐frequency radiofrequency (RF) filters and 3D nonvolatile memories. [ABSTRACT FROM AUTHOR]