Search

Aiming for highly efficient solar cells based on wafers with a low carbon footprint, silicon (Si) EpiWafers are grown epitaxially on reusable, highly doped Si substrates with a stack of porous Si layers (PorSi) for detachment. A state‐of‐the‐art p‐type Si EpiWafer exhibiting a minority charge carrier lifetime of up to 2.2 ms detected at an excess charge carrier density of ≈1 × 1015 cm−3 by photoluminescence (PL) imaging is presented. This translates to a predicted solar cell efficiency of 25.6%, calculated by efficiency limiting bulk recombination analysis (ELBA), and corresponds to losses of less than 1%abs compared to the theoretical limit of the investigated solar cell concept. A detailed loss analysis shows that the major remaining quality limitations are structural defects, specifically stacking faults (SFs). Therefore, the recombination activity of isolated SFs in epitaxially grown reference (EpiRef) wafers on polished substrates without a PorSi is assessed by highly resolved μPL mappings. The recombination activity rises with the number of dislocations within an SF as demonstrated by a comparison to microscope images. When using highly doped substrates, as currently required for EpiWafer fabrication, EpiRef wafers show more SFs exhibiting additionally a higher number of dislocations than SFs in EpiRef wafers on moderately doped substrates. [ABSTRACT FROM AUTHOR]

To date, many materials have been successfully grown on substrates through van der Waals epitaxy without adhering to the constraint of lattice matching as is required for traditional chemical epitaxy. However, for elemental semiconductors such as Ge, this has been challenging and therefore it has not been achieved thus far. In this paper, we report the observation of Ge epitaxially grown on mica at a narrow substrate temperature range around 425 °C. Despite the large lattice mismatch (23%) and the lack of high in-plane symmetry in the mica surface, an epitaxial Ge film with [111] out-of-plane orientation is observed. Crystallinity and electrical properties degrade upon deviation from the ideal growth temperature, as shown by Raman spectroscopy, X-ray diffraction, and Hall effect measurements. X-ray pole figure analysis reveals that there exist multiple rotational domains in the epitaxial Ge film with dominant in-plane orientations between Ge[110] and mica[100] of (20n)°, where n=0, 1, 2, 3, 4, 5. A superlattice area mismatch model was used to account for the likelihood of the in-plane orientation formation and was found to be qualitatively consistent with the observed dominant orientations. Our observation of Ge epitaxy with one out-of-plane growth direction through van der Waals forces is a step toward the growth of single crystal Ge films without the constraint in the lattice and symmetry matches with the substrates. [ABSTRACT FROM AUTHOR]

The enhanced diffusion of boron has been investigated by analyzing out-diffusion profiles in the vicinity of the interface between a lightly boron-doped silicon epitaxial layer and a heavily boron-doped silicon substrate with a resistivity of 8.2 mΩ cm and an oxide precipitate (O.P.) density of 108–1010 cm-3. It is found that the boron diffusion during annealing at 850–1000°C is enhanced with the increase of the oxide precipitate density. On the basis of a model for boron diffusion mediated by silicon self-interstitials, we reveal that the enhanced diffusion is attributed to self-interstitials supersaturated as a result of the emission from oxide precipitates and the absorption by punched-out dislocations. In addition, the temperature dependence of the fraction of the self-interstitial emission obtained analyzing the diffusion enhancement well explains the morphology changes of oxide precipitates reported in literature. [ABSTRACT FROM AUTHOR]

In this contribution, we performed the growth of a 3C-SiC/Si/3C-SiC layer stack on a Si(001) substrate by means of chemical vapor deposition. We show that, by tuning the growth conditions, the 3C-SiC epilayer can be grown along either the [111] direction or the [110] direction. The key parameter for the growth of the desired 3C-SiC orientation on the Si(110)/3C-SiC(001)/Si(001) heterostructure is highlighted and is linked to the Si epilayer surface morphology. The epitaxial relation between the layers has been identified using X-ray diffraction and transmission electron microscopy (TEM). We showed that, regardless of the top 3C-SiC epilayer orientation, domains rotated by 90° around the growth direction are present in the epilayer. Furthermore, the difference between the two 3C-SiC orientations was investigated by means of high magnification TEM. The results indicate that the faceted Si(110) epilayer surface morphology results in a (110)-oriented 3C-SiC epilayer, whereas a flat hetero-interface has been observed between 3C-SiC(111) and Si(110). The control of the top 3C-SiC growth direction can be advantageous for the development of new micro-electro-mechanical systems. [ABSTRACT FROM AUTHOR]

Epitaxial films of BaSi2 on Si(111) for solar cell applications possess three epitaxial variants and exhibit a minority carrier diffusion length (ca. 9.4 μm) much larger than the domain size (ca. 0.2 μm); thus, the domain boundaries (DBs) between the variants do not act as carrier recombination centers. In this work, transmission electron microscopy (TEM) was used to observe the atomic arrangements around the DBs in BaSi2 epitaxial films on Si(111), and the most stable atomic configuration was determined by first-principles calculations based on density functional theory to provide possible interface models. Bright-field TEM along the a-axis of BaSi2 revealed that each DB was a twin boundary between two different epitaxial variants, and that Ba(II) atoms form hexagons containing central Ba(I) atoms in both the bulk and DB regions. Four possible interface models containing Ba(I)-atom interface layers were constructed, each consistent with TEM observations and distinguished by the relationship between the Si tetrahedron arrays in the two domains adjacent across the interface. This study assessed the structural relaxation of initial interface models constructed from surface slabs terminated by Ba(I) atoms or from zigzag surface slabs terminated by Si tetrahedra and Ba(II) atoms. In these models, the interactions or relative positions between Si tetrahedra appear to dominate the relaxation behavior and DB energies. One of the four interface models whose relationship between first-neighboring Si tetrahedra across the interface was the same as that in the bulk was particularly stable, with a DB energy of 95 mJ/m2. There were no significant differences in the partial densities of states and band gaps between the bulk and DB regions, and it was therefore concluded that such DBs do not affect the minority carrier properties of BaSi2. [ABSTRACT FROM AUTHOR]

Optical and structural properties of sulfur-doped epitaxial lateral overgrowth (ELOG) InP grown from nano-sized openings on Si are studied by room-temperature cathodoluminescence and cross-sectional transmission electron microscopy (XTEM). The dependence of luminescence intensity on opening orientation and dimension is reported. Impurity enhanced luminescence can be affected by the facet planes bounding the ELOG layer. Dark line defects formed along the [011] direction are identified as the facet planes intersected by the stacking faults in the ELOG layer. XTEM imaging in different diffraction conditions reveals that stacking faults in the seed InP layer can circumvent the SiO2 mask during ELOG and extend to the laterally grown layer over the mask. A model for Suzuki effect enhanced stacking fault propagation over the mask in sulfur-doped ELOG InP is constructed and in-situ thermal annealing process is proposed to eliminate the seeding stacking faults. [ABSTRACT FROM AUTHOR]

The effect of rapid thermal processing (RTP) on the formation of copper precipitation in p/p+ silicon (Si) epitaxial wafers was systematically investigated by defect etching and optical microscopy. After RTP preannealing at high temperature (1250 °C/60 s, with cooling rate 30 K/s) followed by the 750 °C/8 h + 1050 °C/16 h low-high (L-H) two-step annealing, it was revealed that the bulk microdefects were found only inside the p+ substrate, manifesting no defects generated in the epitaxial layer. However, it was found that the width of denude zone (DZ) in samples only subjected to L-H two-step annealing was narrower than that of epitaxial layer, which meant that oxygen precipitation was formed in epitaxial layer. It can be concluded that RTP was beneficial to the formation of DZ. Additionally, it was found that the width of DZ has a sharp dependence on the introducing temperature of copper contamination, that is, the corresponding equilibrium concentration of interstitial copper in the Si influence the thermodynamics and kinetics process of the formation of copper precipitation significantly. [ABSTRACT FROM AUTHOR]

• We demonstrate epitaxy of GeSn and SiGeSn alloys for optical applications. • Both semiconductors are combined to form direct bandgap group IV heterostructures. • Multi quantum wells show highest PL efficiency and lowest lasing thresholds. • Wavelength-tunable electroluminescence is demonstrated at room temperature. The recent rise of GeSn-based optically pumped lasers have multiplied the efforts to fabricate a fully CMOS compatible and group IV-based light emitter. Their integration with Si-based electronics may yield heavily reduced power consumption in integrated circuits and pave the way towards new sensing or medical applications. Here, we discuss the epitaxy of group IV GeSn and SiGeSn semiconductors and show their suitability for light emitting applications. Double and multi quantum well heterostructures are evaluated, whereby the latter enables an inherently easier control over the formation of deleterious misfit defects. Consequently, microdisk lasers fabricated from those show greatly enhanced light emission and reduced lasing thresholds. The use of in-situ p-i-n doping schemes allow the formation of light emitting diodes, resulting in electrically-enabled light emission already at room temperature. [ABSTRACT FROM AUTHOR]

This paper reports a CMOS MEMS (complementary metal oxide semiconductor micro electromechanical system) piezoresistive humidity sensor fabricated by a surface micromachining process. Both pre-CMOS and post-CMOS technologies were used to fabricate the piezoresistive humidity sensor. Compared with a bulk micromachined humidity sensor, the machining precision and the sizes of the surface micromachined humidity sensor were both improved. The package and test systems of the sensor were designed. According to the test results, the sensitivity of the sensor was 7 mV/%RH (relative humidity) and the linearity of the sensor was 1.9% at 20 °C. Both the sensitivity and linearity were not sensitive to the temperature but the curve of the output voltage shifted with the temperature. The hysteresis of the humidity sensor decreased from 3.2% RH to 1.9% RH as the temperature increased from 10 to 40 °C. The recovery time of the sensor was 85 s at room temperature (25 °C).

To enhance the functionality of the standard silicon photonics platform and to overcome its limitations, in particular for light emission, ultrafast modulation, and nonlinear applications, integration with novel materials is being investigated by several groups. In this paper, we will discuss, among others, the integration of silicon waveguides with ferroelectric materials such as lead zirconate titanate (PZT) and barium titanate (BTO), with electro–optically active polymers, with 2-D materials such as graphene and with III–V semiconductors through epitaxy. We discuss both the technology and design aspects. [ABSTRACT FROM AUTHOR]

Abstract Effective process conditions to utilize a slim vertical silicon chemical vapour deposition reactor were studied. Based on a numerical analysis taking into account the gas flow, heat and species transport, particularly over a wide range of the trichlorosilane gas concentrations from 1% to 40% in ambient hydrogen, a heavy and cold gas was shown to quickly go downward to the hot wafer surface through the slim vertical gas channel. The gas phase near the wafer was sufficiently cooled to produce a cold wall thermal condition which enabled the trichlorosilane gas consumption only at the wafer surface, even in a non-axisymmetric and non-steady condition. The slow wafer rotation, less than 30 rpm, had a considerable effect, such as that increasing the gas phase temperature gradient for suppressing the gas phase reaction. [ABSTRACT FROM AUTHOR]

We present a study for large defects called protrusions that form during the hetero-epitaxy of SiC on Si. We focus first on surface morphology, size, three-dimensional shape and internal structure, and second on photoluminescence and Raman features. These defects have a peculiar 3D structure similar to inverted square pyramids with a vertex close to the SiC/Si interface. The size of the square and the height of the pyramid are both related to the thickness of the epi-layer and are spatially limited by the stacking faults in the {1 1 1} planes. The inner core of the defect consists of nano crystals twinned with respect to the substrate orientation. The defects demonstrate broad peculiar emission band at about 750 nm, while the usual photoluminescence signal from band recombination is at 520 nm. The SiC/Si interface is studied in order to investigate the seed of protrusion defect formation. We found that seeds responsible for the formation of protrusions lie 10 nm above the SiC/Si interface. This indicates that protrusion forms after the carbonization process, in particular in the temperature ramp up after carbonization. Modifying the Si/C ratio and some other growth parameters in the post-carbonization process we succeed in reducing the density of protrusion to less than 10 cm −2 . [ABSTRACT FROM AUTHOR]

Epitaxial growth of group III nitrides on silicon substrates is challenging as large lattice and thermal expansion coefficient mismatches have to be accounted for. It is generally accepted that AlN is the best nucleation layer for GaN‐on‐Si growth. However, some open questions remain about this AlN nucleation layer. In this study, it is investigated how the choice of deposition method of the AlN nucleation layer affects the material and electrical properties of a full HFET structure. First, electrical characterization is performed on thin AlN layers deposited on two inch p‐type silicon substrates grown by NH3‐MBE. CV characteristics indicate that electron injection from an inversion‐like layer at the AlN/Si‐interface is suppressed. Based on previous studies, this leads to the expectation that choosing MBE‐AlN may actually result in superior properties at the device level. Finally, the full HFET stack is grown by MOCVD on both types of AlN nucleation layers. Hall measurements on active devices yield comparable mobilities for both nucleation methods. Preliminary data suggest that MBE‐AlN does not have any detrimental impact the dynamic properties of the buffer. The vertical breakdown voltage measured at 1 μA mm−2 is increased by 30% and the leakage current measured at 600 V is reduced by two orders of magnitude. [ABSTRACT FROM AUTHOR]

Mathematical simulation of the cascade of displacements in SiC is used to consider the specific features of Frenkel-pair generation upon the scattering of 8- and 15-MeV protons. The distribution histograms of energies acquired not only by primary knocked-out atoms, but also by recoil atoms generated in displacement cascades, are calculated. An analysis of the histograms considers two energy ranges. In the first range of "low" energies, the spontaneous recombination of genetically related Frenkel pairs is dominant. Recoil atoms in the second range have a higher energy, which enables these atoms to leave the spontaneousrecombination zone and dissociate into isolated components. The compensation of lightly doped n- and p-4H-SiC samples grown by gas-phase epitaxy is experimentally studied under irradiation with 8- and 15-MeV protons. The carrier removal rates are measured. The calculated and experimental data are compared and estimates are obtained for the size of the spontaneous-recombination zone. [ABSTRACT FROM AUTHOR]

Parallel surface reactions in a SiHCl 3 -SiH x -H 2 system were numerically evaluated based on the heat and gas flow in the epitaxial reactor for clarifying the increase in the silicon epitaxial growth rate. H 2 and SiH x are assumed to individually react with the intermediate surface species, *SiCl 2 , which was formed by the chemisorption of SiHCl 3 . The measurement was reproduced by the calculation using the rate constant obtained in this study for the surface reaction between *SiCl 2 and SiH x . The decrease in the surface coverage by *SiCl 2 and the increase in the silicon yield were shown to be caused by the SiH x . Thus, the surface reaction of the *SiCl 2 with the SiH x was theoretically shown to be effective for increasing the growth rate to higher than the saturated value in an ordinary SiHCl 3 -H 2 system. The rate equation for the parallel Langmuir processes in a general form was also described. [ABSTRACT FROM AUTHOR]

The structure, composition and physical parameters of multilayer silicon carbide system synthesized by atom substitution method on the surface of low-dislocation single-crystal (111) oriented silicon were studied by Raman spectroscopy, ellipsometry, X-ray reflectometry, electron diffraction, IR spectroscopy, X-ray diffraction, AFM and profilometry. It was revealed that SiC films consist of layers, differing in Si y C composition, structure and thickness. The upper layers is a single-crystal 3C-SiC and the lower layers lying in depth of the substrate contain silicon carbide nanocrystals with a high degree of structure perfection and average size of 3–7 nm capable of preferential orientation (311), as well as large crystals (60–260 μm). The presence of cubic (3C-SiC) and hexagonal (mainly, 2H-SiC) polytypes with largest content of crystalline SiC phases in films with the composition closest to stoichiometric was established. In all samples there is carbon in super stoichiometric state, and its structure depends on the synthesis conditions. [ABSTRACT FROM AUTHOR]

Silicene, the single layer of silicon atoms arranged in a honeycomb lattice, has been synthesized in recent experiments and attracted significant attentions. Silicene is promising in future nanoelectronic devices due to its outstanding electronic properties. In experiments, however, different silicene superstructures coexist on Ag(111) substrate. For the device applications, homogenous silicene sheet with large scale and high quality is highly desired. Here, for the first time, we investigate both the temperature and the coverage effects on the thermal stability of epitaxial silicene on Ag(111) surface by ab initio molecular dynamics simulations. The relationship between the stability of various silicene superstructures and the growth conditions, including temperature and coverage of silicon atoms, is revealed by plotting the chemical potential phase diagram of silicene on Ag(111) surfaces at different temperatures. Our results are helpful for understanding the observed diversity of silicene phases on Ag(111) surfaces and provide some useful guidance for the synthesis of homogenous silicene phase in experiments. [ABSTRACT FROM AUTHOR]

We developed high quality 2-inch GaAs/Ge/Si (100) epitaxial substrates, which may be used instead of GaAs monolithic substrates for fabrication of solar cells, photodetectors, LEDs, lasers, etc. A 200–300 nm Ge buffer layer was grown on Si substrates using the HW-CVD technique at 300°C, a tantalum strip heated to 1400°C was used as the “hotwire”. The MOCVD method was used to grow a 1 μ GaAs layer on a Ge buffer. The TDD in the GaAs layers did not exceed (1–2)∙105 cm-2 and the surface RMS roughness value was under 1 nm. [ABSTRACT FROM AUTHOR]

We examined the spin accumulation in Fe/n-GaAs Schottky barriers to evaluate the accuracy of the three-terminal (3T) and four-terminal (4T) measurement geometries. A fully epitaxial Fe/n-GaAs junction was grown in situ using cluster molecular beam epitaxy without breaking the vacuum to exclude the formation of an oxide layer or surface roughness at the interface during intermixing. The spin resistance of the 4T nonlocal spin valve (ΔRNLSV = 0.71 Δ) was twice the value obtained using the 4T Hanle effect method (ΔR4TH=0.35 Δ) at 10K, as predicted theoretically, and this value remained constant over the temperature range examined, from 10K to 77 K. The temperaturedependent spin lifetimes measured using the 3T and 4T Hanle effects exhibited similar behaviors. Although the spin resistance obtained using the 3T Hanle effect was enhanced compared with that obtained using the 4T effect, it was reasonable to conclude that the spin signals obtained from the 3T and 4T measurements originated from spin accumulation in n-GaAs due to the absence of an oxide tunnel barrier or a well-defined interface in our samples. These results completely ruled out any other sources of artifacts. [ABSTRACT FROM AUTHOR]

Low temperature Si epitaxy has become increasingly important due to its critical role in the encapsulation and performance of buried nanoscale dopant devices. We demonstrate epitaxial growth up to nominally 25 nm, at 250 °C, with analysis at successive growth steps using STM and cross section TEM to reveal the nature and quality of the epitaxial growth. STM images indicate that growth morphology of both Si on Si and Si on H-terminated Si (H: Si) is epitaxial in nature at temperatures as low as 250 °C. For Si on Si growth at 250 °C, we show that the Si epitaxial growth front maintains a constant morphology after reaching a specific thickness threshold. Although the in-plane mobility of silicon is affected on the H: Si surface due to the presence of H atoms during initial sub-monolayer growth, STM images reveal long range order and demonstrate that growth proceeds by epitaxial island growth albeit with noticeable surface roughening. [ABSTRACT FROM AUTHOR]

A novel FinFET structure with body spacers in sub fin (BSSF) is proposed to improve the fin height variation produced in the manufacturing processes. Device simulation results are presented to show the electrical variations improvement. The effective fin height ( H eff ) of FinFETs with BSSF is well controlled because it only depends on the silicon epi layer thickness ( T Si ). Taking advantage of the precisely controlled epitaxy process, H eff uniformity of FinFETs with BSSF is much better than conventional bulk FinFETs. Benefit from the smaller H eff variation, FinFETs with BSSF show much smaller electrical characteristics variation. For n-FinFETs, the I on variation improves from 33.46% for conventional bulk FinFETs to 8.05% for FinFETs with BSSF. Additionally, manufacturing of FinFETs with BSSF is compatible with that of the state-of-the-art bulk FinFETs, promising for its applications in massive production. [ABSTRACT FROM AUTHOR]

The deposition of silicon using tetrasilane as a vapor precursor is described for an ultra-high vacuum chemical vapor deposition tool. The growth rates and morphology of the Si epitaxial layers over a range of temperatures and pressures are presented. The layers were characterized using transmission electron microscopy, x-ray diffraction, spectroscopic ellipsometry, Atomic Force Microscopy, and secondary ion mass spectrometry. Based on this characterization, high quality single crystal silicon epitaxy was observed. Tetrasilane was found to produce higher growth rates relative to lower order silanes, with the ability to deposit crystalline Si at low temperatures ( T =400 °C), with significant amorphous growth and reactivity measured as low as 325 °C, indicating the suitability of tetrasilane for low temperature chemical vapor deposition such as for SiGeSn alloys. [ABSTRACT FROM AUTHOR]

Despite the excellent performance of silicon-based selector devices, high epitaxy temperature ( \textT\mathrm {epi}\,>\,700~^{\circ }\text{C} ) is the key constraint for Si selector technology compatibility with back-end-of-the-line (BEOL) process. Recently, we have demonstrated the high performance sub-430 °C epitaxial Si p-i-n selector. In this letter, we identify a two-step mechanism that affects the off-current ( I\mathrm{\scriptscriptstyle OFF} ) performance of low temperature epitaxial Si p-i-n diodes using molecular beam epitaxy (MBE). First, the \textT\mathrm {epi} dependent i-region encroachment by surface dopant segregation shows excellent agreement with the surface diffusion model and demonstrates its validity down to 400 °C. Second, the trap assisted tunneling model is used to evaluate the impact of the modified i-region thickness (due to surface dopant segregation) on I\mathrm{\scriptscriptstyle OFF} . Improved ideality factor ( 2\times ) and I\mathrm{\scriptscriptstyle OFF} performance ( 10^{2}\times $ ) of sub-430 °C p-i-n diode is related to contamination control—a critical challenge in BEOL processing. Based on the experimentally validated model, we present the I\mathrm{\scriptscriptstyle OFF} dependence on the i-region thickness. We show that i-region thickness of 50 nm produces sufficiently low leakage, while higher i-region produces marginal I\mathrm{\scriptscriptstyle OFF} improvement. Thus, the low temperature epitaxial Si p-i-n junction technology is a promising step toward BEOL compatible Si selector technology. [ABSTRACT FROM AUTHOR]

High-density micro-circle patterned Si substrates were successfully fabricated for the direct overgrowth of thick AlN templates by using NH3 pulsed-flow multilayer AlN growth and epitaxial lateral overgrowth techniques. The experimental results show that an 8-µm-thick AlN template was grown at a very high growth rate on the substrates. The AlN template had full widths at half maximum of 0.23° and 0.37° for the (002) and (102) reflection planes in X-ray diffraction rocking curves. Atomic force microscopy and transmission electron microscopy confirmed that the roughness of the surface was low (3.5 nm) and the dislocation density was very low (1.5 x 108 cm-2 (screw), 3.7 x 108 (edge) cm-2). [ABSTRACT FROM AUTHOR]

New discoveries on collective processesin materials fabricationand performance are emerging in the mesoscopic size regime betweenthe nanoscale, where atomistic effects dominate, and the macroscale,where bulk-like behavior rules. For semiconductor electronics andphotonics, dimensional control of the architecture in this regimeis the limiting factor for device performance. Epitaxial crystal growthis the major tool enabling simultaneous control of the dimensionsand properties of such architectures. Although size-dependent effectshave been studied for many small-scale systems, they have not beenreported for the epitaxial growth of Si crystalline surfaces. Here,we show a strong dependence of epitaxial growth rates on size fornano to microscale radial wires and planar stripes. A model for thisunexpected size-dependent vapor phase epitaxy behavior at small dimensionssuggests that these effects are universal and result from an enhancedsurface desorption of the silane (SiH4) growth precursornear facet edges. Introducing phosphorus or boron dopants during thesilicon epitaxy further decreases the growth rates and, for phosphorus,gives rise to a critical layer thickness for single crystalline epitaxialgrowth. This previously unknown mesoscopic size-dependent growth effectat mesoscopic dimensions points to a new mechanism in vapor phasegrowth and promises greater control of advanced device geometries. [ABSTRACT FROM AUTHOR]

We have investigated atomic ordering of Heusler alloy Fe3Si(111) epitaxially grown on Si(111) by using ion beam analysis. The total atomic displacement along Si<111> directions was deduced from the minimum yield χmin and the critical angle Ψ1/2 for channeling. The total displacement consists of both one-dimensional thermal vibrations computed by the Debye theory and static displacements due to imperfections, lattice mismatch, thermal expansion etc. The atomic displacement increased as the annealing temperature increased from 373 to 573 K. We found that this static displacement came from a difference in thermal expansion between the Fe3Si film and Si substrates at the anneal temperature and was quenched into room temperature as a remnant displacement. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

The calibration curve for the carbon concentration in silicon epitaxial layers was obtained by photo-luminescence spectroscopy after carbon ion implantation and electron irradiation. Low carbon concentrations on the order of 1014 atoms/cm3 affected properties such as the on-resistance and carrier lifetime of insulated gate bipolar transistors (IGBTs). We focused on carbon impurities because interstitial carbon can form complexes, such as complexes of interstitial and substitutional carbon (Ci-Cs) and of interstitial carbon and oxygen (Ci-Oi), which produce deep levels in the energy band gap. To verify the effects of carbon impurities separately from those of oxygen impurities, oxygen-free silicon epitaxial layers were studied. The carbon concentration in silicon epitaxial wafers was evaluated quantitatively by using our calibration curve. Carbon ion implantation and photoluminescence spectrum measurements were performed to obtain the slope of the calibration curve. In addition, secondary ion mass spectrometry measurement gave absolute carbon concentration against photo-luminescence intensity for fixing the calibration curve. The calibration curve was used to determine the carbon concentration for each IGBT. Carbon impurity concentrations as low as 1014 atoms/cm3 in silicon epitaxial layers lowered device performance. Therefore, decreasing the carbon impurity concentration is essential for improving the performance of advanced IGBTs. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

The effect of pre-amorphization on the electrical activation of Si implants into In 0.53 Ga 0.47 As is investigated. Electrical measurements show that Si implants into pre-amorphized and crystalline In 0.53 Ga 0.47 As yield similar levels of activation (1.0 × 10 19 cm −3 in the pre-amorphized case and 9.0 × 10 18 cm −3 in the crystalline case) upon rapid thermal annealing for 5 s at 750 °C despite having very different types of resulting damage in the electrically active layers. The subsequent microstructural characterization by TEM indicates that the highly defective regrown layers in the pre-amorphized substrate leads to poor mobility in the active layers, which result in lower sheet resistances. The results suggest that solid phase epitaxy (SPE) in compound semiconductors can lead to some improved activation at lower temperatures and does not prevent substitutional activation of amphoteric dopants upon post SPE annealing. [ABSTRACT FROM AUTHOR]

ABSTRACT The present research and development activities in crystalline silicon photovoltaics include the exploration of doping technologies alternative to the mainstream diffusion process. The goal is to identify those technologies with potential to increase the solar cell efficiency and reduce the cost per watt peak. In that respect, this work presents the selective epitaxial growth of silicon as a candidate for boron doping; showing the results of the evaluation of boron-doped silicon epitaxial emitters on slurry and diamond-coated wire-sliced Czochralski material, their integration in interdigitated back contact solar cells, and the development of a novel process sequence to create the interdigitated rear junction of these devices using selective epitaxial growth. Boron-doped silicon epitaxy is demonstrated to perform in the high efficiency range (>22%), and the use of selective epitaxial growth is proposed as a route for the simplification of the interdigitated back contact solar cell flow. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Several concepts of integration of the epitaxial rare-earth oxides into the emerging advanced semiconductor on silicon technology are presented. Germanium grows epitaxially on gadolinium oxide despite lattice mismatch of more than 4%. Additionally, polymorphism of some of the rare-earth oxides allows engineering of their crystal structure from hexagonal to cubic and formation of buffer layers that can be used for growth of germanium on a lattice matched oxide layer. Molecular beam epitaxy and metal organic chemical vapor deposition of gallium nitride on the rare-earth oxide buffer layers on silicon is discussed. [ABSTRACT FROM AUTHOR]

The formation of Ge layers on boron-doped Si (001) substrates by our sputter epitaxy method has been investigated. The surface morphology of Ge layers grown on Si substrates depends on the substrate resistance, and flat Ge layers are obtained on Si substrates with 0.015 Ω cm resistivity. Highly boron-doped Si substrates cause a transition in the dislocation structure from complex dislocations with 60° dislocation glide planes to 90° pure-edge dislocations, resulting in the formation of flat Ge layers. Furthermore, we have found that the surface morphology of the Ge layers improves with increasing Ge layer thickness. Ge atoms migrating on the deposited Ge layers tend to position themselves at the reactive sites, where the reactivity is related to the number of bonding contacts between the Ge atom and the surface. This modifies the surface morphology, resulting in a flatter surface. Boron dopants together with the sputter epitaxy method effectively suppress the growth of Ge islands and result in the formation of flat Ge layers. [ABSTRACT FROM AUTHOR]

Abstract: Epitaxial layers on a 150-mm-diameter silicon carbide wafer have been grown using a horizontal hot-wall chemical vapor deposition system for three 150-mm-diameter wafers. We investigated the surface morphology and surface defects such as shallow pits and triangular defects of the grown epitaxial layers, as well as the thickness and carrier concentration uniformities. The shallow pit and triangular defect densities were 4.6cm−2 and 1.6cm−2, respectively, and the thickness and the carrier concentration uniformities were 3.9% and 47%, respectively. We focused on improving the carrier concentration distribution for practical use and concluded that the cause of the distribution was the distribution in the effective C/Si ratio in the direction of the gas flow. [Copyright &y& Elsevier]

Abstract: In silicon epitaxy technology, residual O/H2O contamination requires thermal reduction using hydrogen pre-bakes to achieve atomically clean Si surfaces. This H2 pre-bake leads to unwanted increase of thermal budget. The higher the level of interfacial O, the longer the pre-bake period and the higher the temperature have to be for removal of these contaminants. Moisture contamination from the pre-epi chamber etch (immediately before the wafer is loaded), with it's use of high flows of HCl, is identified as a major contributor to the area density of the interfacial O. Stringent control of moisture impurity in the HCl is required to reduce thermal budget. Ultra low temperature technology to desiccate HCl is used to achieve single digit ppb moisture resulting in lower temperature hydrogen pre-bakes than achieved with standard solid media-type HCl purification. [Copyright &y& Elsevier]

We studied the microstructural characteristics and electrical properties of epitaxial Ge films grown on Si(001) substrates by x-ray diffraction, atomic force microscopy, and transmission electron microscopy. The films were grown using a two-step technique by reduced-pressure chemical vapor deposition, where the first step promotes two-dimensional growth at a lower substrate temperature. We observed a decrease in defect density with increasing film thickness. Ge films with thickness of 3.5 μm exhibited threading dislocation densities of 5 × 10 cm, which yielded devices with dark current density of 5 mA cm (1 V reverse bias). We also noted the presence of stacking faults in the form of lines in the films and establish that this is an important defect for Ge films grown by this deposition technique. [ABSTRACT FROM AUTHOR]

Epitaxial circuitry offers a revolution in silicon technology, with components that can be fabricated on atomic scales. We perform the first ab initio calculation of atomically thin epitaxial nanowires in silicon, investigating the fundamental electronic properties of wires two P atoms thick, similar to those produced this year by Weber et al. For the first time, we catch a glimpse of disorder-related effects in the wires—a prerequisite for understanding real fabricated systems. Interwire interactions are made negligible by including 40 ML of silicon in the vertical direction (and the equivalent horizontally). Accurate pictures of band splittings and the electronic density are presented, and for the first time the effective masses of electrons in such device components are calculated. [ABSTRACT FROM AUTHOR]

The fabrication technology and properties of light-emitting Si structures codoped with erbium and oxygen are reported. The layers are deposited onto (100) Si by molecular beam epitaxy (MBE) using an Er-doped silicon sublimation source. The partial pressure of the oxygen-containing gases in the growth chamber of the MBE facility before layer growth is lower than 5 × 10 Torr. The oxygen and erbium concentrations in the Si layers grown at 450°C is ∼1 × 10 and 10 cm, respectively. The silicon epitaxial layers codoped with erbium and oxygen have high crystal quality and yield effective photoluminescence and electroluminescence signals with the dominant optically active Er-1 center forming upon postgrowth annealing at a temperature of 800°C. [ABSTRACT FROM AUTHOR]

Integration of magnetic impurities into semiconductor materials is an essential ingredient for the development of spintronic devices such as dilute magnetic semiconductors. While successful growth of ferromagnetic semiconductors was reported for III-V and II-VI compounds, efforts to build devices with silicon technology were hampered by segregation and clustering of magnetic impurities such as manganese (Mn). Here, we report on a surface-based integration of Mn atoms into a silicon host. Control of Mn diffusion and low-temperature silicon epitaxy lead to confined Mn δ-layers with low interface trap densities, potentially opening the door for a new class of spintronic devices in silicon. [ABSTRACT FROM AUTHOR]

This article reports on the comparison of beryllium oxide and pyrolytic graphite as crucible liners in a high-temperature effusion cell used for boron doping in silicon grown by molecular beam epitaxy. Secondary ion mass spectroscopy analysis indicates decomposition of the beryllium oxide liner, leading to significant incorporation of beryllium and oxygen in the grown films. The resulting films are of poor crystal quality with rough surfaces and broad x-ray diffraction peaks. Alternatively, the use of pyrolytic graphite crucible liners results in higher quality films. [ABSTRACT FROM AUTHOR]

A silicon photodiode detector is presented for use in scanning electron microscopy (SEM). Enhanced imaging capabilities are achieved for sub-keV electron energy values by employing a pure boron (PureB) layer photodiode technology to deposit nanometer-thin photosensitive anodes. As a result, imaging using backscattered electrons is demonstrated for 50-eV electron landing energy values. The detector is built up of several closely packed photodiodes, and to obtain high scanning speed, each photodiode is engineered with low series resistance and low capacitance values. The low capacitance (< \3\ \pF/mm^2) is facilitated by thick, almost intrinsically-doped epitaxial layers grown to achieve the necessarily wide depletion regions. For the low series resistance, diode metallization has been patterned into a conductive grid directly on top of the nanometer-thin PureB-layer front-entrance window. Finally, a through-wafer aperture in the middle of the detector is micromachined for flexible positioning in the SEM system. [ABSTRACT FROM PUBLISHER]

We report on the epitaxial growth of high electron mobility AlSb/InAs heterostructure on exactly oriented (001) Si substrate, using a GaP interfacial layer. The growth conditions are first optimized on GaP substrates to achieve the highest electron mobility. The influence of the Sb flux during the early stage of the GaSb buffer layer is particularly emphasized. Using these optimized growth conditions, the AlSb/InAs heterostructure is grown on a GaP/Si template obtained by metal-organic vapor phase epitaxy. An electron mobility as high as 27 800 cm2 V-1 s-1 and 111 000 cm2 V-1 s-1, respectively, at 300 and 77 K is demonstrated. [ABSTRACT FROM AUTHOR]

We compared the electrical characteristics, including mobility and on -state current Ion, of \n^+-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights Hfin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length Lg decreases, Ion for devices with tall fins becomes worse, probably due to a high parasitic resistance Rp. Furthermore, Vth variation increased with increasing Hfin due to rough etching of the fin sidewall. Process technologies for reducing Rp and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs. [ABSTRACT FROM AUTHOR]

An arsenic doping technique for depositing up to 40-μm-thick high-resistivity layers is presented for fabricating diodes with low RC constants that can be integrated in closely-packed configurations. The doping of the as-grown epi-layers is controlled down to 5 × 1011 cm-3, a value that is solely limited by the cleanness of the epitaxial reactor chamber. To ensure such a low doping concentration, first an As-doped Si seed layer is grown with a concentration of 1016 to 1017 cm-3, after which the dopant gas arsine is turned off and a thick lightly-doped epi-layer is deposited. The final doping in the thick epi-layer relies on the segregation and incorporation of As from the seed layer, and it also depends on the final thickness of the layer, and the exact growth cycles. The obtained epi-layers exhibit a low density of stacking faults, an over-the-wafer doping uniformity of 3.6%, and a lifetime of generated carriers of more than 2.5 ms. Furthermore, the implementation of a segmented photodiode electron detector is demonstrated, featuring a 30 pF capacitance and a 90 Ω series resistance for a 7.6 mm² anode area. [ABSTRACT FROM AUTHOR]

A new concept of edge illuminated solar cells (EISC) based on silicon epitaxial technique has been proposed. In this kind of photovoltaic (PV) devices, sun-light illuminates directly a p-n junction through the edge of the structure which is perpendicular to junction surface. The main motivation of the presented work is preparation of a working model of an edge-illuminated silicon epitaxial solar cell sufficient to cooperation with a luminescent solar concentrator (LSC) consisted of a polymer foil doped with a luminescent material. The technological processes affecting the cell I-V characteristic and PV parameters are considered. [ABSTRACT FROM AUTHOR]

Abstract: Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521cm−1 have a width of 7.8cm−1, which reveals the high crystalline quality of the silicon epitaxy. [ABSTRACT FROM AUTHOR]

Mechanisms governing the aluminum-mediated solid-phase epitaxy of Si on patterned crystalline Si substrates have been identified by studying the deposited material as a function of growth conditions when varying parameters such as temperature, growth time, and layer-stack properties. Early growth stages can be discerned as first formation of “free” Si at the Al/α-Si interface, then diffusion of Si along the Al grain boundaries, nucleation at the Si substrate surface, nuclei rearrangement, and finally crystal growth. The acquired understanding is applied to control the selectivity and completeness of single-crystal growth in various sizes of contact windows to the Si substrate. [ABSTRACT FROM AUTHOR]

A solid-phase epitaxy (SPE) process based on material inversion of an amorphous silicon (alpha-Si) on aluminum layer-stack is applied to form ultrashallow p-type junctions. In this paper, we demonstrate the controllability of the whole process when the junction area is reduced to the sub-100-nm range and the processing temperature is reduced to 400 degC. The SPE-Si to Si-substrate interface, analyzed locally by transmission electron microscopy and more systematically by the fabrication and electrical characterization of p+-n diodes, was found to be practically defect-free. Moreover, it is demonstrated by capacitance-voltage profiling that the Al-dopants do not diffuse into the bulk silicon for the used processing temperatures and the SPE p+-island to n-substrate transition is ideally abrupt. The I-V characteristics of the as-fabricated p+-n diodes are near ideal (n=1.03) and low-ohmic contact resistance to p- and p + regions is reliably obtained [ABSTRACT FROM PUBLISHER]

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic s/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node. [ABSTRACT FROM AUTHOR]

Abstract: A selective epitaxy process for raised sources and drains is investigated, with growth performed at a pressure in the 1Torr regime, rather than the more common CVD (10’s of Torr) or UHV–CVD (1–40mTorr) regimes. It is shown that selective growth can be achieved using a mixture of silane and dichlorosilane without any requirement for Cl2 or HCl in the gas stream. The selectivity of the process can be controlled by varying the silane:dichlorosilane ratio in the gas mixture, with a ratio between 1:1 and 3:1 giving selective growth. Facet-free selective epitaxy is achieved, the process is selective to silicon nitride and a growth activation energy of 2.4eV is obtained. Raised source/drain MOSFET devices with channel lengths down to 50nm have been fabricated and the thickness of the selective epitaxial silicon layer has been varied to investigate the effect of this parameter on device performance. Excellent sub-threshold characteristics are obtained and the sub-threshold slope, S, improves from 102 to 81.9mV/dec as the raised source/drain thickness is increased from 50nm to 100nm. The raised source/drain also improves threshold voltage roll-off and drain induced barrier lowering. A decrease in both I on and I off is seen with increasing RSD thickness, but the overall I off/I on trade-off is unchanged. [Copyright &y& Elsevier]