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A novel methodology for total ionizing dose (TID) hardening of Silicon-on-insulator (SOI) MOSFET is demonstrated by employing a superior type of void embedded SOI (VESOI) substrate. With the successful removal of most of the radiation sensitive area in buried oxide, the TID tolerance of VESOI MOSFET is significantly enhanced in comparison to its conventional SOI counterpart. In particular, the shift of threshold voltage (${V}_{\text {th}}$) and subthreshold swing is only −38.9mV and 11.6mV/dec at radiation doses up to 2Mrad(Si). Further device simulation shows that the radiation immunity can withstand misalignment between the gate and embedded void in a wide range. Our VESOI substrates, offering both high compatibility with planar CMOS process and versatile void embedded device design, exhibit great potential in the development of anti-radiation SOI devices. [ABSTRACT FROM AUTHOR]

Abstract Single‐event transients (SETs) due to heavy‐ion (HI) strikes adversely affect the electronic circuits in the sub‐100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage‐controlled oscillators (VCOs) without affecting the circuit specifications. A circuit asymmetry technique is used for faster recovery of the oscillator in the event of a single event transient (SET) caused by an ion hit. Also, a new SET tolerant inductor capacitor‐voltage controlled oscillator (LC‐VCO) topology is proposed for a radiation environment that shows reduced phase displacement, amplitude displacement, and recovery time. A comparison has been made with various LC‐VCOs that have an inherent rad‐hard capability which proves a significant improvement in SET sensitivity.

This brief presents a new clock-related Single-Event Effect (SEE) mitigation method for Field Programmable Gate Arrays (FPGAs). SEEs are most likely to happen in harsh environments, such as space, and are decently mitigated with Triple Modular Redundancy (TMR). However, clock tree triplication has a high cost for FPGAs; it reduces the total amount of usable clocks and introduces uncontrolled skew variation. Therefore, we propose to instantiate a Programmable Local Clock Filter (PLCF) close to TMRed sequential elements to locally triplicate the clock and filter the SEEs coming from the clock tree. The PLCF mitigation method has demonstrated 100% resilience to SEEs, which target either the clock tree or the PLCF’s logic. Thus, PLCF represents the first programmable clock-related SEE mitigation method and proposes a promising alternative to the state-of-the-art technics applied to FPGAs’ fabric. [ABSTRACT FROM AUTHOR]

Spin-driven thermoelectric (STE) generation based on the combination of the spin Seebeck effect (SSE) and inverse spin Hall effect is an alternative to conventional semiconductor-based thermocouples as it is large scale, low cost, and environment-friendly. The STE device is thought to be radiation hard, making it attractive for space and nuclear technology applications. By using magnetometry, transmission electron microscopy, and the hard X-ray photoemission spectroscopy (HAXPES) measurements, we show that an STE device made of single-crystalline Y3Fe5O12 (YIG)/Pt heterostructures has tolerance to irradiation of high-energy heavy ion beams. We used 200 MeV gold ion beams modeling cumulative damages due to fission products emitted from the surface of spent nuclear fuels. By varying the dose level, we confirmed that the thermoelectric and magnetic properties of the single-crystalline YIG/Pt STE device are finite at the ion-irradiation dose up to 1012 ions/cm2 fluence. In addition, the HAXPES measurements were performed to understand the effects at the interface of YIG/Pt. The HAXPES data suggest that the chemical reaction regarding Fe and O that diminishes the SSE signals is promoted with the increase of the irradiation dose. The understandings of the damage analysis in YIG/Pt are beneficial for developing better STE devices applicable to harsh environmental usages. [ABSTRACT FROM AUTHOR]

We describe the porting of a soft-error (SE) hardened microprocessor to a modern 12-nm bulk CMOS finFET fabrication process and radiation testing results. The microprocessor includes latch-based cache and main register file (RF) arrays, with compact dual-patterned layouts. It is protected by dual modular redundancy (DMR) in the speculative pipeline, RF, and caches. Self-correcting triple modular redundant (TMR) flip-flops provide fine-grain protection in the TMR circuits that hold key architectural state. The DMR circuits are protected by checking circuits at the caches, RF, and crossovers to the TMR state. In the event of a DMR mismatch, an SE exception is taken, and the machine state is repaired via software. This approach also allows the detailed machine state reporting to elucidate the SE root cause circuits and cross sections. Broad beam radiation testing shows that it responds correctly to detected SEs. The by-circuit cross sections of the various circuits are reported for both heavy ions and protons. [ABSTRACT FROM AUTHOR]

Abstract Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard‐gated Quatro cell, and so on, are discussed. The flip‐flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip‐flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard‐gated Quatro FF (GQFF) using guard‐gated Quatro cell and Muller C‐element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual‐input Muller C‐element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead. [ABSTRACT FROM AUTHOR]

Soft errors induced by Single Event Transient (SET) or Single Event Upset (SEU) are a great threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits, we proposed a radiation hardened flip-flop in this paper, namely, Soft Error Detection and Recovery flip-flop (SEDR-FF). Error detection is based on delayed sampling and redundant storage by a redundant latch. A pulsed clock is adopted to control the redundant latch to reduce the hold time constraint of the latch. To generate the pulsed clock, two efficient delay elements are presented in this paper. Error recovery is accomplished by reloading the previous data stored in a history latch. Transistor-level simulations and timing-annotated gate-level simulations under 65 nm technology show that the proposed flip-flop can efficiently detect and correct the soft errors caused by SET or SEU. It has low overhead of setup time, and is suitable for high-performance designs. In addition, compared with other radiation hardened cells, the proposed flip-flop has moderate power and area overhead, and has lower area cost for fixing hold time violations in circuits designs. [ABSTRACT FROM AUTHOR]

As the safety-critical applications (e.g., automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects five benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions. [ABSTRACT FROM AUTHOR]

Double silicon-on-insulator (DSOI) technology featuring two buried oxide layers under silicon film has drawn excessive attention to space applications by modulating the electric field in back channel. This article studied the impact of the total ionizing dose (TID) effect on the n-channel metal oxide semiconductor field effect transistors (nMOSFETs) based on DSOI materials. Radiation-induced degradation in performance only appeared in the metal oxide semiconductor field effect transistor (MOSFET) with $W/L = 0.15~\mu \text{m}$ /10 $\mu \text{m}$ after 1.5 Mrad(Si) irradiation and recovered with negative $V_{\mathrm {bg}}$ applied. However, due to the weak coupling effect between the front and back gates, the threshold voltage ($V_{\mathrm {th}}$) of nMOSFET with $W/L = 10~\mu \text{m}$ /10 $\mu \text{m}$ and $10~\mu \text{m}/0.13~\mu \text{m}$ declined 0.06 V compared with devices before irradiation when $V_{\mathrm {bg}}$ is set to 0 V. The TCAD simulation and testing results reveal that the electric field introduced by negative back-gate bias could effectively mitigate the TID-induced performance degradation in DSOI nMOSFETs. The investigation will facilitate the application of DSOI technology for high-radiation-dose conditions. [ABSTRACT FROM AUTHOR]

Abstract Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high‐charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just‐in‐time fault injection simulator (OVPsim‐FIM) against fault injection campaigns conducted with event‐driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single‐core fault injection campaigns are performed on RTL descriptions of Arm Cortex‐M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex‐A9 scenarios. Campaigns consider different open‐source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim‐FIM is more than 1000× faster than cycle‐accurate simulators and up to 312× faster than event‐driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors.

Single‐event transients (SETs) due to heavy‐ion (HI) strikes adversely affect the electronic circuits in the sub‐100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage‐controlled oscillators (VCOs) without affecting the circuit specifications. A circuit asymmetry technique is used for faster recovery of the oscillator in the event of a single event transient (SET) caused by an ion hit. Also, a new SET tolerant inductor capacitor‐voltage controlled oscillator (LC‐VCO) topology is proposed for a radiation environment that shows reduced phase displacement, amplitude displacement, and recovery time. A comparison has been made with various LC‐VCOs that have an inherent rad‐hard capability which proves a significant improvement in SET sensitivity. [ABSTRACT FROM AUTHOR]

Latches areused extensivelyin digital circuits; however, as technology scaling reaches nanometric feature sizes, externally induced phenomena (such as radiation strikes in aerospace applications) may cause a single event upset (SEU) in either single or double nodes. Rather than masking, mitigation of an SEU is effectively achieved by recovering the correct value throughthe design of hardened latches. Using the polarity of the radiation-induced voltage pulse, a stacked design is proposed; this circuit permits to accomplish protection and SEU recovery at reduced overhead and so at substantially improved performance. The first proposed latch (RH-1) recovers all single node upsets and has an extremely low delay in its operation, because this latch propagates data to the output stage though only a transmission gate. The fast operation of RH-1 is utilized in the second latch (RH-2) proposed in this article. RH-2 consists of two RH-1 modules to guarantee that at least two nodes maintain the latched values under the occurrence of a double node upset. Simulation results are provided; they show that RH-1 (recovering all single node upsets and many double node upsets) has the best delay and power-delay-area product (PDAP, as combined metric) among all considered designs and the second-best area and dynamic power dissipation among the recovering schemes, and meanwhile RH-2 (recovering all double node upsets) has the best dynamic power dissipation and PDAP among all considered designs and the best area and delay among recovering schemes. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) degradation is caused by radiation-induced charge buildup in oxides. Radiation hardening of silicon-on-insulator (SOI) devices with deep submicrometer nodes or nanonodes is mainly concerned with the field oxide and buried oxide. In this article, a back-channel adjustment technique for TID hardening is proposed. The technique is compatible with the 130-nm partially depleted silicon on an insulator (PDSOI) commercial process with no extra effort applied to the design. After testing the key electrical parameters and characterizing the radiation tolerance of the typical T-gate I/O nMOS devices, the results show that the radiation tolerance of the devices can reach more than 1 Mrad(Si) with the back-channel adjustment technique, and electrical performance is comparable to that of commercial process devices. [ABSTRACT FROM AUTHOR]

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell. [ABSTRACT FROM AUTHOR]

We present the design, fabrication, and radiation testing of a custom 20-channel application-specific integrated circuit (ASIC) for amplification and digitization of microvolt signal levels from space instrumentation (e.g., thermopile sensors) operating in harsh space radiation environments. The ASIC is fabricated in a commercial 180-nm complementary metal oxide silicon (CMOS) process node using a combination of radiation hard by design and discrete-time analog signal processing to mitigate leakage, offset, 1/f, and thermal noise. The chip has an input-referred integrated noise voltage of 190 nV in a 240-Hz bandwidth. Irradiation with very high total ionizing dose (TID) and high-energy heavy ions was carried out to evaluate the chip’s radiation hardness. The chip’s postradiation performance evidenced parametric immunity to greater than 50 Mrad (Si) TID and no single-event latch-up up to at least 123.6 MeV-cm2/mg linear energy transfer. [ABSTRACT FROM AUTHOR]

In space, due to high energy particles, which cause single event upsets (SEUs), the traditional 6T SRAM cell becomes more susceptible to soft-error. In order to address this, a radiation hardened memory-by-design 10T (RHMD10T) SRAM cell is proposed in this brief. The relative strength of RHMD10T is estimated by comparing it with other contemporary cells such as QUATRO10T, QUCCE10T, QUATRO12T, QUCCE12T, NS10T and PS10T over various major design metrics. RHMD10T exhibits 1.09 ×/ 1.16 ×/1.26 × shorter read delay than QUCCE10T/ QUATRO10T/ NS10T. RHMD10T has the highest read stability and can tolerate the highest amount of critical charge than all other comparison cells. RHMD10T consumes the lowest hold power than all other comparison cells, except NS10T. In addition, RHMD10T is the least susceptible to SEU, except QUCCE12T. All these aforementioned improvements of RHMD10T are obtained at a cost of slightly longer write delay and lower write ability. [ABSTRACT FROM AUTHOR]

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit–cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly. [ABSTRACT FROM AUTHOR]

This article presents a radiation-hardened Cortex-R4F system-on-chip prototype with integrated total ionizing dose (TID) dynamic compensation capabilities, designed and fabricated in 28-nm fully depleted silicon-on-insulator (FD-SOI) technology. The processor was made robust to single-event effects, thanks to several design techniques: error correcting code (ECC) protected and bit-interleaved memories, optimized radiation-hardened sequential cells, and sensitive logic cells filtering. To counter the TID effects on the processor functionality and performances, the system embeds an integrated digital dosimeter. The dosimeter is capable of computing the TID in real time and providing the information to the system. Using a software lookup table (LUT), coupled with 28-nm FD-SOI technology support of asymmetric and wide-body-biasing, the reported TID can be converted to a request made to an external body-bias generator and be fully compensated. The system, operating at 0.9 V and 500 MHz, was tested under space grade radiations and has shown no failure in the 0 krad(Si) to 50 krad(Si) TID range. [ABSTRACT FROM AUTHOR]

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications. [ABSTRACT FROM AUTHOR]

In the harsh space environment, the phase-locked loop (PLL) circuit is vulnerable to radiation effects, which will lead to performance degradation or even function interrupts. In this article, a rad-hard low-noise PLL is designed with low power and area overhead and verified in a 130-nm silicon-on-insulator process. Heavy ion test demonstrates that the proposed PLL is immune to the single-event effect up to 83.7 MeV·cm2/mg. Furthermore, its single-event sensitivity is characterized and compared with an unhardened PLL by the pulsed laser test. Finally, the gamma-ray radiation experiment confirms that it can provide >300 krad(Si) total ionizing dose assurance. [ABSTRACT FROM AUTHOR]

We have investigated the deterioration of field effect transistors based on two-dimensional materials due to irradiation with swift heavy ions. Devices were prepared with exfoliated single layers of MoS2 and graphene, respectively. They were characterized before and after irradiation with 1.14 GeV U28+ ions using three different fluences. By electrical characterization, atomic force microscopy, and Raman spectroscopy, we show that the irradiation leads to significant changes of structural and electrical properties. At the highest fluence of 4 × 1011 ions/cm2, the MoS2 transistor is destroyed, while the graphene based device remains operational, albeit with an inferior performance. [ABSTRACT FROM AUTHOR]

There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits. Aiming at reliability evaluation of very-large-scale integration circuits implemented in SRAM-based field programmable gate arrays, a fault injection platform is constructed based on the soft error mitigation controller in this study. The authors adopt a 16K-point fast Fourier transformation processor as the design under test (DUT) and inject errors into different positions. The effectiveness of this platform is varied by comparing the results of DUT with Golden data. Compared with the traditional reliability testing techniques, the fault injection method proposed in this study has the advantages of low cost, short test period and low resource consumption. Hence, the proposed fault injection design is suitable for circuits consuming huge resources and large number of repeating tests.

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification.

The 13T static random-access memory (SRAM) cell was designed as a low-voltage single-event upset (SEU)-tolerant device for ultralow power space applications, showing full read and write functionality down to the subthreshold voltage of 300 mV. In order to assess the SEU hardness of the device experimentally, it was tested under heavy-ion beams at the Cyclotron Resource Center, Louvain-la-Neuve, Belgium. After irradiation, bit upsets from “1” to “0” were observed, whereas bit upsets from “0” to “1” were extremely rare. Since multiple upsets occurred within addresses, we assume that in addition to random ion hits on the memory cells, the reason for the high SEU rate is ions impinging on the nonhardened peripheral circuitry. Furthermore, heavy-ion experiments and Monte Carlo simulations were performed in order to clarify the upset mechanism. [ABSTRACT FROM AUTHOR]

Capabilities of rad-hard electronics are often degraded by post-irradiation annealing, whose effects need to be considered in designing complex systems, such as CMOS image sensors (CISs). In particular, the commonly accepted behavior of annealing cannot be systematically assumed, because reverse annealing does not necessarily come from the degradation of the defects, but could be the result of defects annealing non-uniformities. This article provides an extensive study of the dark current and pixel readout electronic behavior of CISs during irradiation and annealing, in order to provide some insights on these annealing non-uniformities. The isochronal annealing performed up to 300 °C demonstrates that, up until a certain temperature, reverse annealing is almost always present, but the 300 °C annealing always heals the system very efficiently. When performed on specially designed gated pixels for ultrahigh dose applications, adding a N+ drain further mitigates the radiation effects along with the reverse annealing. This proves the efficiency of these rad-hard designs and calls for further research in this radiation-hardening direction. [ABSTRACT FROM AUTHOR]

Radiation-hardening techniques can be extensively used in the design level to improve the robustness of very large-scale integration (VLSI) circuits used in space applications. Accordingly, this work analyzes the efficiency of transistor folding layout in improving the single-event transient (SET) robustness of digital circuits. Additionally, diffusion splitting is proposed to reduce the area overhead of multiple-finger designs. Besides increasing threshold linear energy transfer, results show that both techniques can also reduce the overall cross section and the in-orbit SET rate for protons and heavy ions in low-earth orbit (LEO) and international space station (ISS) orbits. [ABSTRACT FROM AUTHOR]

For embedded systems in harsh environments, a radiation robust circuit design is still an open challenge. As complementary–metal–oxide semiconductor (CMOS) processes get denser and smaller, their immunity toward particle strikes decreases drastically. Due to its good radiation effects tolerance and its inherent nonvolatility, spin-transfer torque magnetic tunnel junction (STT-MTJ) is considered a promising candidate for high-reliability electronics. Nevertheless, when integrated in a CMOS circuit, these magnetic devices could still be affected by upsets. To decrease the probability of this occurrence, a radiation robust setup is used to calibrate a physics-based 20-nm MTJ compact model, integrated in a 28-nm Fully Depleted Silicon On Insulator (FD-SOI) technology. Thus, a radiation hardening by design (RHBD) solution is presented, where a nonvolatile sequential block enables one to mitigate the single-event effects (SEEs). [ABSTRACT FROM AUTHOR]

Radiation sensor interface circuits can be mounted on sensor nodes in wireless sensor networks to detect radiation signals. They respond quickly to operators and command centers, allowing appropriate decisions to be made to mitigate nuclear power plant accidents. For instance, high-level radiation leaked from a reactor building during a nuclear plant accident can degrade the performance of the radiation sensor interface implemented by integrated circuits due to threshold voltage shift, leakage current change, and noise increase induced by radiation impact events. To obtain reliable signal measurements in the high radiation environment, radiation-hardening technologies must be applied to radiation sensor interface circuits. The radiation-hardened sensor interface circuit proposed in this article exploits a pair of charge-sensitive amplifiers (CSAs) in dual paths to equivalently cancel out the distorted output signals caused by radiation impacts on the circuits. In addition, a low-power, fully differential successive approximation register (SAR) analog-to-digital converter (ADC) is used to reduce the radiation effects by subtracting the radiation-induced noise of one input from the other. The implemented radiation sensor interface circuit can maintain its performance up to 1.0 mrad (SiO2) of irradiation with only 2.5 mW power consumption, while successfully sensing and transferring the radiation information to the downstream signal-processing network. [ABSTRACT FROM AUTHOR]

In this paper, a novel energy efficient 12T memory cell is proposed which is radiation hardened by design (RHD) to tolerate single-event multiple-node upsets (SEMNU) in near threshold voltage regime. The radiation hardness of the proposed memory cell is improved by controlling the cross coupled inverters’ PMOS devices through dummy access transistors. We validated the proposed memory cell in STMicroelectronics 65-nm CMOS technology. The post layout parasitic extracted simulations show that by employing the proposed RHD-12T memory cell, an average improvement of ~ 42%, 17%, 17%/9% and 6%/7% in layout area, power dissipation, read/write access time, and read/write static noise margin, respectively, is obtained over the recently reported 12T memory cell at supply voltage of 0.4V. We also validated the proposed memory cell at 32-nm CMOS technology node using technology computer-aided design (TCAD) mixed-mode simulations. In the 32-nm technology, the proposed RHD-12T memory cell shows an average improvement of ~15%, 10%/56%, and 8%/10% in power dissipation, read/write access time, and read/write static noise margin, respectively, over the 12T memory cell at supply voltage of 0.3V. Combining layout-topology, HSPICE post layout simulations and TCAD mixed mode simulation results clearly show that the proposed memory cell effectively tolerates single event upset as well as SEMNU. In 32nm technology our memory cell can provide SEMNU tolerance up to the value of LET equals to 62 Mev-cm2/mg. [ABSTRACT FROM AUTHOR]

The development of space applications based on commercial system on chip (SOC) FPGA devices has become an important direction for the development of aerospace technology, but single event upsets (SEUs) in space is a difficult problem for commercial SOC FPGAs for space applications. This article presents an anti-anti method for ARM processors in SOC FPGA. This method makes full use of the hardware resources of dual-core ARM in SoC FPGA and improves the system's anti-SEU capability through dual-core mutual-check and recovery mechanisms. At the same time, the data stream and control flow fault tolerant are used to improve the anti-SEU capability within the processor. Error detection and correction (EDAC) and triple modular redundancy (TMR) are used to improve anti-SEU capability of the data flow. A two-level watchdog and ARM exception handling are used to achieve the anti-SEU capability of the control flow. Experimental results show that the two-level fault-tolerance mechanism proposed here improves the system's anti-SEU capability without adding additional hardware resources. This method is currently carrying out satellite-borne ground application verification. [ABSTRACT FROM AUTHOR]

There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits. Aiming at reliability evaluation of very-large-scale integration circuits implemented in SRAM-based field programmable gate arrays, a fault injection platform is constructed based on the soft error mitigation controller in this study. The authors adopt a 16K-point fast Fourier transformation processor as the design under test (DUT) and inject errors into different positions. The effectiveness of this platform is varied by comparing the results of DUT with Golden data. Compared with the traditional reliability testing techniques, the fault injection method proposed in this study has the advantages of low cost, short test period and low resource consumption. Hence, the proposed fault injection design is suitable for circuits consuming huge resources and large number of repeating tests. [ABSTRACT FROM AUTHOR]

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources. [ABSTRACT FROM AUTHOR]

This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a subthreshold/near-threshold regime. The proposed latch provides the TNU tolerance using two restorer circuits (RCs) to hold the correct state and a three-input clocked combinational majority circuit (CMC). The $RC$ is based on pull-up and pull-down paths, controlled by different susceptible nodes, results in better radiation hardness. We validated the proposed latch in the STMicroelectronics 65-nm CMOS technology. The postlayout parasitic extracted simulations show that, by employing the proposed latch, an average improvement of ~42% in an area-energy-delay product (AEDP) is obtained over the recently reported TNU-hardened latch (TNUHL) at a supply voltage of 0.4 V. We also validated the proposed TNUHL in a 32-nm CMOS technology node using technology computer-aided-design (TCAD) mixed-mode simulations. In the 32-nm technology, our latch can provide a TNU tolerance up to a value of linear energy transfer (LET) equal to 190 Mev-cm2/mg. The HSPICE postlayout simulations and the TCAD mixed-mode simulation results clearly show that the proposed latch effectively tolerates TNU. [ABSTRACT FROM AUTHOR]

The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single‐event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics‐based modelling approach is used for compute radiation response of each component in the circuit. Tri‐state inverter embedded non‐clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip–flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool. [ABSTRACT FROM AUTHOR]

The use of pinned photodiode (PPD)-based CMOS image sensors (CIS) in harsh radiation environment (such as space) is limited by their tolerance to ionizing radiation. Technology computer-aided design (TCAD) simulations are performed to reproduce the radiation-induced defect and therefore the dark current increase in PPD pixels up to 1 kGy (i.e., 100 krad) of total ionizing dose (TID). To do so, the TCAD models are calibrated with measurements performed on irradiated pixels. Then, the influence on the PPD radiation hardness of various manufacturing process and pixel design modifications are explored. This work shows that the proposed modification can improve the radiation hardness of PPD CIS against ionizing. [ABSTRACT FROM AUTHOR]

We present the design and the test results of a dual-channel vertical-cavity surface-emitting laser (VCSEL) driver application-specific integrated circuit (ASIC) LOCld65 for detector front-end readout. LOCld65 is designed in a commercial 65-nm CMOS technology with a power supply of 1.2 V. LOCld65 contains two separate channels with the same structure and the two channels share an I2C slave. Each channel consists of an input amplifier, four stages of limiting amplifiers (LAs), a high-current output driver, and a bias-current generator. In order to extend the bandwidth, the input amplifier uses an inductive peaking technique and the LAs use a shared inductive peaking technique. The input amplifier and the output driver each utilize a continuous-time linear equalizer (CTLE). The LAs employ active feedback. The modulation current, the bias current, the peaking strength of the CTLEs, and the feedback strength of LAs are programmable through an I2C interface. In order to protect from the radiation damage, the I2C slave is implemented with triple modular redundancy. Each channel of LOCld65 is tested to operate up to 14 Gb/s with typical power dissipations (the VCSEL included) of 68.3 and 62.1 mW/channel at the VCSEL voltages of 3.3 and 2.5 V, respectively. LOCld65 survives 4.9 kGy(SiO2). LOCld65 is an excellent match for the serializer-deserializer ASIC low power giga bit transceiver in single- or dual-channel optical transmitters in high-luminosity Large Hadron Collider (HL-LHC) upgrade applications. [ABSTRACT FROM AUTHOR]

This paper addresses a quantitative study of the reliability improvement of the stacked transistor structure. The susceptibility of integrated circuits to single-event effects caused by interaction with ionizing particles is analyzed at the semiconductor level, as well as at the device and circuit levels considering the replacement of each transistor by a stacked silicon-on-insulator (SOI) array. Up-to-date technologic nodes were used as inputs for the simulation and reliability models. A stochastic Markov model was proposed and evaluated. The model output pointed the stacked array as a real alternative for high-reliability in future applications, with exceptional results. For a $10^{5}$ device-count integrated circuit, a success probability of 80% is reached for missions over 100 000 h in the commercial flights altitude, while for the single transistor system, this value is reached for missions under 100 h. [ABSTRACT FROM AUTHOR]

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration random-access memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13- $\mu \text{m}$ CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three orders of magnitude. On the conditions of linear energy transfer being up to 14 MeV $\cdot$ cm2/mg, no SEU errors were observed from DFF in the hardened FPGA design. [ABSTRACT FROM AUTHOR]

This paper presents design techniques and measurement results of a radiation-hardened mixed-signal microcontroller system-on-chip (SoC) dedicated to fully-customized nanosatellites for the civil active space debris (ADR) cleaning missions. The design requirements are firstly given. The architecture of an on-board computer (OBC) is then described. A radiation-hardened-by-design (RHBD) SoC is proposed for such applications to obtain a long operational period. The proposed SoC is composed of a dual-modular redundant (DMR) 16-bit RISC processor, a 1 kB SRAM, a 12-bit pipelined SAR ADC, a 12-bit current-steering DAC and an on-chip clock generator. The radiation-hardened-by-design techniques are adopted to resist the total-ionization-dose (TID) effects. An SoC prototype is designed and fabricated in 180 nm CMOS process. The electronical performance of devices-under-test (DUTs) has been measured based on a customized mother-daughter board. The performance of the proposed SoC meet the requirements of the nanosatellites. Furthermore, the TID radiation effect experiment is performed. It indicated that the proposed SoC can resist the total dose of more than 300 krad (Si) at the dose rate of 50 rad (Si)/s. [ABSTRACT FROM AUTHOR]

Field‐programmable gate arrays are susceptible to radiation‐induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module‐based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round‐robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable‐rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin. [ABSTRACT FROM AUTHOR]

Abstract Mixed signal on-chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with sufficient ruggedness against ionizing radiation and single event burnout. We report on a novel hardening by design approach for radiation tolerant integrated RF NLDMOS transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease TID induced leakage currents the shallow trench isolation (STI) of MOS transistors was replaced by narrow junction isolated regions. For a significant increase of the SEB onset voltage a cascode arrangement consisting of an isolated NMOS and NLDMOS was chosen. The floating NMOS-drain/NLDMOS-source node in the cascode arrangement is always reverse biased which efficiently avoids a turn-on of the parasitic npn bipolar transistor. The rad-hard isolated NMOS/NLDMOS cascode features a breakdown voltage BVDS > 50 V, a maximum cut off frequency f T = 5 GHz and a maximum oscillation frequency f MAX = 14 GHz. In comparison with standard NLDMOS transistors the isolated NMOS/NLDMOS cascode device shows an increase of the SEB onset voltage from 14V to 30V at a linear energy transfer LET of 67.7 MeVcm2/mg and a negligible increase of source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source. [ABSTRACT FROM AUTHOR]

Breakdown voltage (BV) shifting behavior induced by total-ionizing-dose (TID) irradiation is investigated for high-voltage SOI LDMOS, in this letter. The BV increase caused by irradiation is present for the first time, and the degradation mechanism is revealed by modeling and simulation. Irradiation-induced electric field modulation exerts an impact on the competition between the lateral BV and vertical BV and results in BV shifting. The dielectric field is enhanced by irradiation-induced positive oxide trapped charges in the BOX layer, which is responsible for the BV increasing after irradiation. A TID radiation hardening approach is proposed so that the lateral BV is required to be properly higher than vertical BV instead of pursuing equality. [ABSTRACT FROM AUTHOR]