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In this study, we integrated an Indium Gallium Zinc Oxide (IGZO) channel with a superlattice of HfO2/ZrO2 (HZO) under low-thermal-budget microwave annealing to produce nearly wake-up-free ferroelectric capacitors. To eliminate the impact of trap-charges during the atomic layer deposition process, we conducted H2 plasma treatment to eliminate leak defects induced by carbon contamination and maintain neutrality to achieve high-quality IGZO/HZO interfaces, confirmed by x-ray photoelectron spectroscopy. The H2 plasma treatment improved polarization (Pr) and coercive field (Ec), reaching 2Pr: 40 μC/cm2 and Ec: 2.33 MV/cm, enabling a low-power writing speed of 30 ns with eight states (three bits per cell). The defect engineering method ensures endurance of up to 108 cycles and retains ten-year data storage at 90 °C. This research provides a new avenue for improving emerging oxide interfaces controlled by ferroelectric polarization. [ABSTRACT FROM AUTHOR]

Metal oxide transistors have garnered substantial attention for their potential in low-power electronics, yet challenges remain in achieving both high performance and low operating voltages through solution-based fabrication methods. Optimizing interfacial engineering at the dielectric/semiconductor interface is of utmost importance in the fabrication of high-performance thin film transistors (TFTs). In the present article, a bilayer Ti3C2Tx-MXene/SnO2–semiconductor (Tx stands for surface termination) configuration is used to fabricate a high-performance n-type thin film transistor by using an ion-conducting Li-Al2O3 gate dielectric on a p+-Si substrate, where electrical charges are formed and modulated at the Li-Al2O3/SnO2 interface, and Ti3C2Tx-MXene nanosheets serve as the primary electrical charge channel due to their long lateral size and high mobility. A comparative characterization of two distinct TFTs is conducted, one featuring Ti3C2Tx MXene and SnO2 semiconductor layer and the other with SnO2 only. Notably, the TFT with the Ti3C2Tx MXene layer has shown a significant boost in the carrier mobility (10.6 cm2/V s), leading to remarkable improvements in the on/off ratio (1.3 × 105) and subthreshold swing (194 mV/decade), whereas the SnO2 TFT without the Ti3C2Tx MXene layer shows a mobility of 1.17 cm2/V s with 8.1 × 102 on/off ratio and 387 mV/decade subthreshold swing. This investigation provides a possible way toward the development of high-performance, low-voltage TFT fabrication with the MXene/semiconductor combination. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

In this work, bottom-Schottky-structure InGaZnOx (IGZO) Schottky barrier diodes (SBDs) with sputtered PtOx anodes were fabricated and annealed in oxygen at different temperatures. Critical parameters and negative bias stress (NBS) stability of SBDs with different annealing temperatures are investigated. With the annealing temperature increases, the barrier height and rectification ratio of the SBDs exhibited a rising-then-declining trend, while the ideality factor slightly increased until 200 °C. The SBDs show up overall reliability except for a leakage current rising trend under light, which can be attributed to free electron generation from the ionized oxygen vacancy. Among all the SBDs, the 175 °C annealed ones exhibited the best overall performance, including a high barrier height of 0.89 eV, an ideality factor of 1.14, and a large rectification ratio of over 108. Compared to the initial SBDs, the annealed ones showed up great improvement in NBS stability except for the 200 °C annealed ones, which was permanently degraded and not able to recover to original states. According to experimental result analysis and IGZO material characteristics, a stability model based on the subgap trap transition from V O 2 + to VO and new V O 2 + creation was proposed, which applies to both the short-term and long-term NBS tests. The results above demonstrate that oxygen annealing at appropriate temperature is an effective method to improve both device performance and NBS stability for PtOx–IGZO SBDs. [ABSTRACT FROM AUTHOR]

In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states. [ABSTRACT FROM AUTHOR]

Information processing and memorizing in the brain take place in a neural network consisting of neurons connected with each other by synapses. Meanwhile, the neural network is immersed in a common electrochemical environment with global parameters regulating the overall functions, which is barely discussed in neuromorphic devices. In this study, organic/inorganic hybrid transistors with sodium alginate as the gate dielectric layer and indium tin oxide as the channel were successfully prepared. We have not only simulated the basic properties of synapses in a single device, but, on top of that, also simulated the global regulation of information processing in the brain due to the incorporation of global grids, achieving excitatory and inhibitory synaptic weight. Moreover, the construction of a 3 × 3 synaptic array enables image learning and memorizing functions. These results demonstrate the significant advantages of electrolyte-gated transistors in enabling complex neural network connectivity and offer a promising opportunity for future artificial synapses. [ABSTRACT FROM AUTHOR]

Electronics today has evolved significantly, including its application in transparent and flexible devices. Flexible electronics offers new product concepts, including low production cost, low energy consumption, and sustainable and environmentally friendly materials. This concept leads to the development of novel materials that realize today's requirements. Incorporating optically transparent and flexible thin-film-based devices into the electronic circuitry helps in maintaining high conductivity along with achieving the similar electronic behavior of the conventional electronic gadgets. Thin-film diodes (TFDs) and thin-film transistors (TFTs) are the core materials to be incorporated as building blocks for flexible devices. Among them, oxide-based thin films have been marked to be significant because of their efficient electrical performance, low temperature processing, and device flexibility. The present article reviews the concepts and application of zinc oxide (ZnO) as the semiconducting material for flexible thin-film devices. We also review flexible and transparent TFDs and TFTs that are based prominently on ZnO as the semiconducting material. Furthermore, the present issues have also been addressed. [ABSTRACT FROM AUTHOR]

Synaptic behavior simulation in transistors based on MoS2 has been reported. MoS2 was utilized as the active layer to prepare ambipolar thin-film transistors. The excitatory postsynaptic current phenomenon was simulated, observing a gradual voltage decay following the removal of applied pulses, ultimately resulting in a response current slightly higher than the initial current. Subsequently, ±5 V voltages were separately applied for ten consecutive pulse voltage tests, revealing short-term potentiation and short-term depression behaviors. After 92 consecutive positive pulses, the device current transitioned from an initial value of 0.14 to 28.3 mA. Similarly, following 88 consecutive negative pulses, the device current changed, indicating long-term potentiation and long-term depression behaviors. We also employed a pair of continuous triangular wave pulses to evaluate paired-pulse facilitation behavior, observing that the response current of the second stimulus pulse was ∼1.2× greater than that of the first stimulus pulse. The advantages and prospects of using MoS2 as a material for thin-film transistors were thoroughly displayed. [ABSTRACT FROM AUTHOR]

The mechanism of gate threshold voltage (VT) shifts observed in high κ/metal gate stacks is investigated by a density functional theory. This finds that VT depends on the band alignments and the chemical trends between the component oxide layers, such as HfO2, SrO, La2O3, Al2O3, and SiO2. Based on the electron counting rule, we have built three insulating SiO2/SrO, SiO2/La2O3, and SiO2/Al2O3 interfaces, all of which feature a clean bandgap. Two methods have been adopted to derive the band alignments between these four oxides, which are consistent with each other. The results show staggered, "staircase" band alignments and enable La2O3 and Al2O3 layers to shift the metal electrode Fermi level in opposite directions and to approach the Si conduction band and valence band edge positions, respectively. This analysis updates previous empirical models of this effect based on metal oxide ion densities or electronegativity scales and confirms that the oxide layer scheme is suitable for controlling the effective metal work functions in metal–oxide–semiconductor field-effect transistors. [ABSTRACT FROM AUTHOR]

It seems impossible to use silicon oxide as a suitable gate dielectric material in metal-oxide-semiconductor field effect transistors. Many researchers have studied various metal oxides, nitrides, composite, and hybrid materials in search of dielectric materials that can replace silicon oxide. Each of these materials has advantages and disadvantages. In the present work, water-induced Lithium oxide (LiOx) with the organic PEIE (polyethylene imine ethoxylated) materials has been synthesized and studied. One advantage of the present work is using deionized water for getting (LiOx) precursor solution from lithium nitrate without the use of any toxic additives, resulting in a low cost-effective and eco-friendly synthesis. By fabricating three organic field effect transistors (OFETs) with LiOx/ PEIE nanocomposite materials with the same weight ratio (1:1), desirable electrical characteristics such as higher carrier mobility (μ) of 47.3 cm2V−1 S−1 , higher on-off current ratio (Ion/Ioff) of ∼105 , minima threshold voltage (Vth) shift of ∼ 0.6 (±0.2) V, lower subthreshold swing (SS) of 3.12 mV/decade and lower tunneling-, and leakage current density (J) of 2 (nA/cm2) could be found which demonstrated eco-friendly water-induced LiOx/ PEIE can be used as an alternative gate dielectric for the future of the OFET devices. [ABSTRACT FROM AUTHOR]

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices. Vertical field-effect transistors (VFETs) have potential for the realization of ultra-scaled devices, but their fabrication is usually limited by trade-offs between scalability and channel length. Here, the authors report a large-scale transfer method to realize indium gallium zinc oxide/graphene VFETs with van der Waals metallic contacts and reduced channel length. [ABSTRACT FROM AUTHOR]

Various methods have been discussed in the literature regarding enabling the over-current (OC) capability of silicon carbide (SiC) MOSFETs. SiC MOSFETs can operate at up to 250 °C without failure. One of their features is to permit transient operation at elevated temperatures. This is possible if the stress on the gate oxide and packaging can be kept to a level that can be handled. This paper, instead, investigates the potential of enabling the OC capability of SiC MOSFETs by modifying the gate-source voltage. Since the on-state resistance ( R D S (o n) ) of SiC MOSFETs decreases with an increase in the gate voltage ( V G S ), the conduction losses can be decreased by increasing the V G S . Experiments and simulations have been performed to predict the R D S (o n) with the increase in V G S . It is found that the simulation models provided by manufacturers can be used to predict R D S (o n) accurately even outside the specifications, hence facilitating the precise estimation of conduction losses. It is also concluded that V G S can be increased during OCs in order to keep the conduction losses within the safety limits. A simple concept for implementing this function on a gate driver is also proposed with the additional functionality of increasing the V G S during OC by measuring the on-state voltage of the MOSFET. [ABSTRACT FROM AUTHOR]

The objective of this study is to develop an efficient process to synthesize wafer scale p-type cuprous oxide (Cu2O) with the back-end-of-line (BEOL) compatible process (<400 °C). Metallic copper is deposited on SiO2/Si substrates followed by rapid thermal oxidation to oxidize it into large-area, uniform Cu2O. Bottom-gate Cu2O thin-film transistors (TFTs) were fabricated as gate dielectric on 100 nm thermal oxide. The results of the ID-VG curve demonstrate that we have successfully fabricated BEOL-compatible p-type Cu2O TFTs. The drain-off current can be achieved to 0.1 pA, with the highest on/off ratio reaching up to 6 orders. Significantly, the TFT with an on/off ratio of 106 is sufficient to meet the requirements for digital circuit applications, including logic circuits, and the BEOL-compatible process (<400 °C) can fulfill the demands of monolithic 3D integrated circuits, expanding the scope of functional integration applications. Additionally, positive bias stress reliability testing indicated a high-quality passivation layer. These findings suggest that material improvements have significantly enhanced the performance of Cu2O TFTs. [ABSTRACT FROM AUTHOR]

Oxide semiconductor-based thin-film transistors (TFTs) are promising candidates for display backplanes and memory device applications. To achieve high device performance and sustain the electrical properties under prolonged operation, it is important to overcome the mobility–stability trade-off in oxide TFTs. Here, we propose a bilayer-structured semiconductor stack formed by plasma-enhanced atomic layer deposition (PEALD), where an indium-free gallium zinc oxide (GZO) film is grown on top of indium gallium zinc oxide (IGZO), to be implemented in top gate devices. Applying a GZO layer (with optimum Ga to Zn ratio) between the IGZO and the gate insulator (GI) resulted in two major effects: interface engineering and band alignment modulation. While maintaining a sufficiently large field effect mobility (31.9 cm2 V−1 s−1), considerable improvements in device reliability were observed concerning positive-bias thermal stress (PBTS) and negative-bias illumination stress (NBIS) compared to TFTs incorporating IGZO single layers. This suggests that proper composition control through PEALD in the bilayer oxide semiconductor TFT may help achieve an appropriate balance between mobility and reliability. [ABSTRACT FROM AUTHOR]

This work presents a normally off high-voltage indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) featuring a drain offset region modulated by the IZO layer (IMO, IMO-IGZO TFT). In addition to decreasing the specific on-resistance (Ron,sp) by more than three orders of magnitude, the IMO structure further elevates the breakdown voltage by optimizing the thickness of the IZO layer (tIZO) compared to the Offset TFT. Through TCAD simulation, the underlying mechanism responsible for the improved performance of the IMO-IGZO TFT is elucidated. The introduced IZO modulating layer effectively increases carrier concentration and rebuilds the electric field within the offset region. Consequently, the IMO-IGZO TFT with a 6 nm thick IZO modulating layer and 3.5 μm length offset region attains a breakdown voltage of 410 V and demonstrates favorable Ron,sp of 5.3 × 103 mΩ × cm2. This results in a Baliga's figure of merit of 31.72 kW/cm2, surpassing conventional and Offset TFTs by factors of 186 and 3048, respectively. [ABSTRACT FROM AUTHOR]

Capacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks. [ABSTRACT FROM AUTHOR]

Amorphous IGZO (a‐IGZO) thin‐film transistors (TFTs) are standard backplane electronics to power active‐matrix organic light‐emitting diode (AMOLED) televisions due to their high carrier mobility and negligible low leakage characteristics. Despite their advantages, limitations in color depth arise from a steep subthreshold swing (SS) (≤ 0.1 V/decade), necessitating costly external compensation for IGZO transistors. For mid‐size mobile applications such as OLED tablets and notebooks, it is important to ensure controllable SS value (≥ 0.3 V/decade). In this study, a conversion mechanism during plasma‐enhanced atomic layer deposition (PEALD) is proposed as a feasible route to control the SS. When a pulse of a diethylzinc (DEZn) precursor is exposed to the M2O3 (M = In or Ga) surface layer, partial conversion of the underlying M2O3 to ZnO is predicted on the basis of density function theory calculations. Notably, significant distinctions between In‐Ga‐Zn (Case I) and In‐Zn‐Ga (Case II) films are observed: Case II exhibits a lower growth rate and larger Ga/In ratio. Case II TFTs with a‐IGZO (subcycle ratio of In:Ga:Zn = 3:1:1) show reasonable SS values (313 mV decade−1) and high mobility (µFE) of 29.3 cm2 Vs−1 (Case I: 84 mV decade−1 and 33.4 cm2 Vs−1). The rationale for Case II's reasonable SS values is discussed, attributing it to the plausible formation of In‐Zn defects, supported by technology computer‐aided design (TCAD) simulations. [ABSTRACT FROM AUTHOR]

Charge storage synaptic circuits employing InGaZnO thin‐film transistors (IGZO TFTs) and capacitors are a promising candidate for on‐chip trainable neural network hardware accelerators. However, IGZO TFTs often exhibit bias instability. For synaptic memory applications, the programming transistors are predominantly exposed to asymmetric off‐state biases, and a unique field‐dependent on‐current reduction under off‐scenario is observed which may result in programming current variation. Further examination of the phenomenon is conducted with transmission line‐like method and degradation recovery tests, and current reduction can be attributed to contact resistance increase by charge trapping in the source and drain electrode and the channel region. The current decrease is subsequently formulated with a stretched exponential model with bias‐dependent parameters for quantitative circuit analysis under off‐state degradation. A neural network hardware acceleration simulator is utilized to assess the complicated impact the off‐state current degradation could instigate on on‐chip trainable IGZO TFT‐based synapse arrays. The simulation results generally demonstrate deteriorated training accuracy with aggravated off‐state instability, and the accuracy trend is elucidated from the perspective of weight symmetry point. [ABSTRACT FROM AUTHOR]

The amorphous In─Ga─Zn─O (a‐IGZO) thin film transistors (TFTs) have attracted attention as a cell transistor for the next generation DRAM architecture because of its low leakage current, high mobility, and the back‐end‐of‐line (BEOL) compatibility that enables monolithic 3D (M3D) integration. IGZO‐based electronic devices used in harsh environments such as radiation exposure can be vulnerable, resulting in functional failure. Here, the behavior of subgap density‐of‐states (DOS) over full subgap range according to the impactful gamma‐ray irradiation in a‐IGZO TFTs is investigated by employing DC current–voltage (I−V) data with multiple‐wavelength light sources. To understand the origins of the radiation effect, IGZO films have been also analyzed by x‐ray photoelectron spectroscopy (XPS). Considering in‐depth electrical and chemical analysis, the unexpected increase of subthreshold leakage current caused by total ionizing dose (TID) is strongly correlated with newly discovered deep‐donor states (gDDγ(E)$g_{DD}^\gamma (E)$) at the specific energy level. In particular, oxygen vacancies caused by the gamma‐ray irradiation give rise to undesirable electrical characteristics such as hysteresis effect and negative shift of threshold voltage (VT). Furthermore, the TCAD simulation results based on DOS model parameters are found to exhibit good agreement with experimental data and plausible explanation including (gDDγ(E)$g_{DD}^\gamma (E)$). [ABSTRACT FROM AUTHOR]

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium–tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility. [ABSTRACT FROM AUTHOR]

This study investigated the potential of indium tungsten oxide (IWO) channel-based inorganic electrolyte transistors as synaptic devices. We comparatively analyzed the electrical characteristics of indium gallium zinc oxide (IGZO) and IWO channels using phosphosilicate glass (PSG)-based electrolyte transistors, focusing on the effects of electric-double-layer (EDL) and electrochemical doping. The results showed the superior current retention characteristics of the IWO channel compared to the IGZO channel. To validate these findings, we compared the DC bias characteristics of SiO2-based field-effect transistors (FETs) with IGZO and IWO channels. Furthermore, by examining the transfer curve characteristics under various gate voltage (VG) sweep ranges for PSG transistors based on IGZO and IWO channels, we confirmed the reliability of the proposed mechanisms. Our results demonstrated the superior short-term plasticity of the IWO channel at VG = 1 V due to EDL operation, as confirmed by excitatory post-synaptic current measurements under pre-synaptic conditions. Additionally, we observed superior long-term plasticity at VG ≥ 2 V due to proton doping. Finally, the IWO channel-based FETs achieved a 92% recognition rate in pattern recognition simulations at VG = 4 V. IWO channel-based inorganic electrolyte transistors, therefore, have remarkable applicability in neuromorphic devices. [ABSTRACT FROM AUTHOR]

Optoelectronic synapses are inevitable for realizing neuromorphic vision systems, which require the integration of image recognition, memory and image processing into a single platform. In this work, we present a three terminal optoelectronic synapse created using zinc oxide (ZnO) thin film transistor. The persistent photoconductivity (PPC) of ZnO thin film is utilized to demonstrate the synaptic behavior. The change in conductance of the device under UV illumination has been interpreted as the weight change in the synapse. The basic synaptic functions such as sensory memory, short term memory, long term memory, duration-time-dependent plasticity and paired pulse facilitation (PPF) have been successfully demonstrated. The device shows a PPF index of 160%, comparable to other optoelectronic synapses reported in literature. Further, to corroborate the existing theory that PPC is caused by oxygen vacancies, additional characterizations are carried out and the presence of oxygen vacancies is detected in the fabricated ZnO device. Subsequently, pattern recognition of MNIST handwritten dataset has been performed using the conductance tuning curves of the proposed ZnO TFT based synapses in a neural network architecture, thereby demonstrating their feasibility to be used in neuromorphic applications. [ABSTRACT FROM AUTHOR]

Solid–liquid interfaces made of functional inorganic materials and liquid electrolytes exhibit various interesting responses by applying an electric bias across the interface. Using an electric-double-layer device fabricated on a thin-film channel of magnetic Weyl semimetal Co3Sn2S2 with an ionic liquid gate electrolyte, we show that the conducting channel thickness can be effectively decreased by applying a negative gate voltage. The application of a gate voltage of −6 V at 250 K gives rise to an irreversible increase in the channel resistance. Transmission electron microscopy reveals that the thickness of the crystallized Co3Sn2S2 region is decreased by applying the negative bias, leaving a Co-poor disordered region on top of the Co3Sn2S2 layer. These results suggest that the preferential dissolution of Co is driven under the application of the negative bias, which leads to the disconnection of Co kagome-lattice layer that is mainly responsible for electrical conduction in Co3Sn2S2. Distinct from conventional bottom-up film growth approaches, this top-down thickness control enables us to examine the thickness dependence of the anomalous transport properties of Co3Sn2S2 in a single sample. The present finding will be useful for experimentally verifying the theoretically discussed ultrathin-film properties of the magnetic Weyl semimetal Co3Sn2S2. [ABSTRACT FROM AUTHOR]

Developing p-type oxide thin-film transistors (TFTs) is an essential path for further application in complementary metal oxide semiconductor (CMOS) components. However, the inferior electrical performance of p-type MO TFTs compared to n-type TFTs remains an ongoing challenge. Herein, for the first time, a low temperature, facile material engineering approach by incorporating n-type nanoparticles (NPs) was proposed for preparing p-type transparent NiOx TFTs. The characteristics of thin films blending NPs and the electrical performances of TFTs were investigated. The field effect mobility of TFTs with doping was nearly 20 times higher than pristine TFTs without doping, which was mainly beneficial from the suitable band alignment between NPs and p-type oxide, the increasing Ni3+ oxidation state in NiOx, as well as the improved dielectric/semiconductor interface quality. Electrons from drain electrode injected into metal oxide turn accepted in NPs rather than being trapped in the dielectric/semiconductor interface due to a strong surface electron depletion effect of NPs. NPs with small particle size and appropriate concentration would promote continuous hole transport by electrons transferring and reducing the interface trap state. The facile material engineering strategy is a promising technique for preparing p-type transparent MO-TFTs at low temperature, which showed great potential to be applicable in CMOS circuits on flexible substrates. [ABSTRACT FROM AUTHOR]

Quasi‐2D(two dimentional) perovskite is one of the potential materials in optoelectronic applications due to the scalable solution processes and low binding energy. Recent studies employing diverse spacer ligands of mono‐ and di‐amine functional groups to form Ruddlesden‐Popper (RP) and Dion‐Jacobson (DJ) phase perovskites efficiently manipulate the perovskite microstructure. However, there is a notable gap in investigating the performance of photomemory devices based on perovskites using different ligands and the accommodability in polymer matrixes. Herein, the perovskite with phenethylammonium bromide (PEABr) or p‐xylylenediamine (PDMA) ligands and methacrylate polymers comprising varied pendent groups (benzene and pyrene) are designed to investigate their effect. The results show that RP‐phase perovskite with polymer‐conferred pyrene group presented an excellent crystalline orientation, fewer grain boundaries, and higher charge transfer efficiency, attributed to superior accommodation between ligands and polymers and appropriate aggregation of pyrene groups. It demonstrates superior memory device characteristics of a high ON/OFF current ratio (2.68 × 104), low operational voltage (−0.1 V), short illumination times (0.1 s), and maintains its decent performance even under thermal environments. This work highlights that leveraging the steric hindrance of ligands and functional polymers to control the microstructure of perovskite is a prospective strategy to promote the photomemory's development. [ABSTRACT FROM AUTHOR]

A stretchable active‐matrix (AM) display is a next‐generation display that breaks away from displaying limited information on flat and curved screens. However, the implementation of stretchable displays requires much more complex fabrication processes and meticulous efforts compared to traditional flat/curved displays. Here, the biaxially stretchable AM micro‐light emitting diode (LED) display on polydimethylsiloxane (PDMS) with liquid metal (LM) interconnects is reported. The pixel islands consisting of oxide TFTs and micro‐LEDs, which are fabricated on the polyimide (PI) substrate, are formed through green laser cutting and transfer to the PDMS substrate. LM interconnects integrate on the pixel island and PDMS by a lift‐off process. The oxide TFTs and micro‐LEDs comprising the 2T1C (2 TFT + 1 capacitor) pixel circuit on the PI island, along with LM interconnects, demonstrate stable electrical characteristics even under a relaxed state as well as when biaxially stretched up to 24%. For 24% stretching of display pixels with the same ratio of PI island and LM interconnects, the LM interconnects operate at 48% stretching. The combination of pixel island array and LM interconnects successfully demonstrates the implementation of a two‐axis stretchable display capable of displaying characters of "A", "D", "R", and "C" through AM driving. [ABSTRACT FROM AUTHOR]

Metabolites are essential molecules involved in various metabolic processes, and their deficiencies and excessive concentrations can trigger significant physiological consequences. The detection of multiple metabolites within a non‐invasively collected biofluid could facilitate early prognosis and diagnosis of severe diseases. Here, a metal oxide heterojunction transistor (HJ‐TFT) sensor is developed for the label‐free, rapid detection of uric acid (UA) and 25(OH)Vitamin‐D3 (Vit‐D3) in human saliva. The HJ‐TFTs utilize a solution‐processed In2O3/ZnO channel functionalized with uricase enzyme and Vit‐D3 antibody for the selective detection of UA and Vit‐D3, respectively. The ultra‐thin tri‐channel architecture facilitates strong coupling between the electrons transported along the buried In2O3/ZnO heterointerface and the electrostatic perturbations caused by the interactions between the surface‐immobilized bioreceptors and target analytes. The biosensors can detect a wide range of concentrations of UA (from 500 nm to 1000 µM) and Vit‐D3 (from 100 pM to 120 nm) in human saliva within 60 s. Moreover, the biosensors exhibit good linearity with the physiological concentration of metabolites and limit of detections of ≈152 nm for UA and ≈7 pM for Vit‐D3 in real saliva. The specificity is demonstrated against various interfering species, including other metabolites and proteins found in saliva, further showcasing its capabilities. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) are promising devices for bioelectronics, such as biosensors. However, current cleanroom‐based microfabrication of OECTs hinders fast prototyping and widespread adoption of this technology for low‐volume, low‐cost applications. To address this limitation, a versatile and scalable approach for ultrafast laser microfabrication of OECTs is herein reported, where a femtosecond laser to pattern insulating polymers (such as parylene C or polyimide) is first used, exposing the underlying metal electrodes serving as transistor terminals (source, drain, or gate). After the first patterning step, conducting polymers, such as poly(3,4‐ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), or semiconducting polymers, are spin‐coated on the device surface. Another femtosecond laser patterning step subsequently defines the active polymer area contributing to the OECT performance by disconnecting the channel and gate from the surrounding spin‐coated film. The effective OECT width can be defined with high resolution (down to 2 µm) in less than a second of exposure. Micropatterning the OECT channel area significantly improved the transistor switching performance in the case of PEDOT:PSS‐based transistors, speeding up the devices by two orders of magnitude. The utility of this OECT manufacturing approach is demonstrated by fabricating complementary logic (inverters) and glucose biosensors, thereby showing its potential to accelerate OECT research. [ABSTRACT FROM AUTHOR]

We report on a device model for thin-film transistors (TFTs) in the framework of Mott's trap-and-release transport theory for disordered semiconductors. The model features a so-called Mott function that is demonstrated to be powerful for analytically deriving the terminal characteristics and other critical parameters of TFTs, including threshold voltage, subthreshold swing, and field-effect mobility. The model is validated by way of application to an amorphous InGaZnO (IGZO)-based TFT, for which good agreement between the analytical and experimental data are obtained. This study offers a simple yet powerful formalism for effective parameter characterization and extraction for oxide and other related TFTs, including those from the organic materials family. [ABSTRACT FROM AUTHOR]

A low‐thermal‐budget fabrication approach is developed to realize high‐performance fluorine‐doped indium oxide (In2O3:F) thin‐film transistors (TFTs) with remarkable bias‐stress stability. The ultrathin transistor channel layer is prepared by a re‐developed atomic layer deposition (ALD) process of using cyclopentadienyl indium(I) (InCp) and O2 plasma to deposit a crystalline In2O3 film, followed by a new fluorine doping strategy to use CF4 plasma to afford the In2O3:F layer. As revealed by the density functional theory (DFT) analysis, the fluorine doping can stabilize the lattice oxygen and electrically passivate the problematic VO defects in In2O3 by forming the FOFi spectator defects. Therefore, the fabricated In2O3:F TFTs show simultaneously excellent electrical performance and remarkable bias‐stress stability, with high µFE of 35.9 cm2 V−1 s−1, positive Vth of 0.36 V, steep SS of 94.3 mV dec−1, small hysteresis of 33 mV, and small ΔVth of −111 and 49 mV under NBS and PBS, respectively. This work demonstrates the high promise of the fluorinated ALD In2O3:F TFTs for the CMOS back‐end‐of‐line (BEOL) compatible technologies toward advanced monolithic 3D integration. [ABSTRACT FROM AUTHOR]

The prostate-specific antigen (PSA) test is considered an important way for preoperative diagnosis and accurate screening of prostate cancer. Current antigen detection methods, including radioimmunoassay, enzyme-linked immunosorbent assay and microfluidic electrochemical detection, feature expensive equipment, long testing time and poor stability. Here, we propose a portable biosensor composed of electrolyte-gated amorphous indium gallium zinc oxide (a-IGZO) transistors with an extended gate, which can achieve real-time, instant PSA detection at a low operating voltage (<2 V) owing to the liquid-free ionic conductive elastomer (ICE) serving as the gate dielectric. The electric double layer (EDL) capacitance in ICE enhances the accumulation of carriers in the IGZO channel, leading to strong gate modulation, which enables the IGZO transistor to have a small subthreshold swing (<0.5 V dec−1) and a high on-state current (∼4 × 10−4 A). The separate, biodegradable, and pluggable sensing pad, serving as an extended gate connected to the IGZO transistor, prevents contamination and depletion arising from direct contact with biomolecular buffers, enabling the IGZO transistor to maintain superior electronic performance for at least six months. The threshold voltage and channel current of the transistor exhibit excellent linear response to PSA molecule concentrations across five orders of magnitude ranging from 1 fg mL−1 to 10 pg mL−1, with a detection limit of 400 ag mL−1 and a detection time of ∼5.1 s. The fabricated biosensors offer a point-of-care system for antigen detection, attesting the feasibility of the electrolyte-gated transistors in clinical screening, healthcare diagnostics and biological management. [ABSTRACT FROM AUTHOR]

The oxide thin‐film transistors (TFTs) with ultrathin (5 nm) crystalline In2O3 channels formed by an atomic layer deposition method are fabricated. The ultrathin In2O3 films are formed at a deposition temperature of 300 °C using (3‐(dimethylamino)propyl)dimethylindium as the indium precursor and ozone as the oxidizing agent. The postannealing is performed in an oxygen atmosphere for 2 h at 300 °C. The scaling behavior of the field‐effect mobility (μFE) is investigated as a function of the channel length (Lch). As Lch increases from 5 to 160 μm, the average μFE is measured and found to increase from 20.2 to 33.6 cm2 V−1 s−1. It shows the average device properties of subthreshold swing of 0.32 V dec−1, turn‐on voltage of −5.5 V, and on/off current ratio of 107. To understand this trend, the transmission line model is utilized to extract the resistance components present across the channel quantitatively. The analyses reveal that among the components comprising the total resistance, the fraction of Rc increases as Lch becomes shorter. Thus, Rc emerges as a dominant parameter that determines μFE. In this regard, the results have technical significance in vertical TFTs and high‐resolution applications in which predictable scaling matters. [ABSTRACT FROM AUTHOR]

This study developed a technology for a vertical field‐effect transistor (VFET) incorporating c‐axis aligned crystal oxide semiconductor on a Gen 3.5 glass substrate. VFETs, with a channel length of 0.5 μm, demonstrated stable characteristics with minimal variation, higher on‐state current compared with low‐temperature polysilicon FETs, and extremely low off‐state leakage current. A prototype 513‐ppi organic light‐emitting diode display that features a red, green, and blue stripe arrangement and includes an internal compensation circuit with a configuration of six transistors and two capacitors was fabricated by harnessing the advantageous features of VFETs. Such a display was previously unattainable with planar FETs. Thus, the developed VFET technology presents a viable pathway for achieving ultrahigh‐resolution panels on glass substrates. [ABSTRACT FROM AUTHOR]

Amorphous indium gallium zinc oxide (a-IGZO) is becoming an increasingly important technological material. Transport in this material is conceptualized as the heavy disorder of the material causing a conduction or mobility band-edge that randomly varies and undulates in space across the entire system. Thus, transport is envisioned as being dominated by percolation physics as carriers traverse this varying band-edge landscape of "hills" and "valleys". It is then something of a missed opportunity to model such a system using only a compact approach—despite this being the primary focus of the existing literature—as such a system can easily be faithfully reproduced as a true microscopic TCAD model with a real physically varying potential. Thus, in this work, we develop such a "microscopic" TCAD model of a-IGZO and detail a number of key aspects of its implementation. We then demonstrate that it can accurately reproduce experimental results and consider the issue of the addition of non-conducting band-tail states in a numerically efficient manner. Finally, two short studies of 3D effects are undertaken to illustrate the utility of the model: specifically, the cases of variation effects as a function of device size and as a function of surface roughness scattering. [ABSTRACT FROM AUTHOR]

The phase‐field method was employed to simulate the effects of pores on grain growth in the indium gallium zinc oxide (IGZO) targets during conventional and two‐stage sintering (TSS). The findings indicated that the TSS method effectively suppressed the rapid growth of grains. With an increase in porosity and a more prominent pore size, the rate of grain growth accelerated, resulting in the formation of coarser grains. Subsequently, IGZO targets were fabricated using the molding‐cold isostatic pressing (CIP) and TSS methods. The densification activation energies of IGZO green compacts were calculated to be 510 and 370 kJ/mol for CIP at 180 and 250 MPa, respectively, utilizing the main sintering curve (MSC). Additionally, by optimizing the TSS process, a highly dense IGZO target with a relative density of 99.53%, a resistivity of 4.3 mΩ/cm, and an average grain size of 8.59 µm was successfully achieved. [ABSTRACT FROM AUTHOR]

In this manuscript, a new vertically stacked GaSb-source stepped oxide split-pocket vertical dielectrically modulated tunnel field effect transistor (SOSPVDMTFET) is presented for the first time. The novelty of this device lies in its stepped oxides with full gate length cavity and n + split-pockets in source region. These design features significantly suppress the ambipolar current at drain/channel junction and improves the drain current (ION), subthreshold swing (SS), threshold voltage (Vth), and current ratio (Iratio). In addition, it enhances the RF parameters such as transconductance (gm), maximum cut-off frequency (fT), transit time (τ), and device efficiency. It is found that the drain current sensitivity of the proposed device is 3000 times higher than the work reported in [Theja and Panchore, "Performance investigation of GaSb/Si heterojunction based gate underlap and overlap vertical TFET biosensor," IEEE Trans. Nano Biosci., Vol. 22, no. 2, pp. 284–91, 2022]. Further, the behavior of biomolecules at different subcavity regions (R1, R2, R3) and cavity thickness has been investigated. The effect of non uniform distribution of biomolecule in cavity region is also discussed. [ABSTRACT FROM AUTHOR]

In low-power electronics, there is a substantial demand for high-performance p-type oxide thin-film transistors (TFTs) that are capable of efficient operation at low voltages. In this study, we employ anodization to form an aluminum oxide gate dielectric layer, enabling the fabrication of p-type tin oxide (SnO) TFTs that effectively operate at a low voltage of 1 V. Under optimal device fabrication conditions, the SnO TFT demonstrates an on/off current ratio exceeding 103 and a saturation mobility of 1.94 cm2 V−1 s−1 at 1 V operation. The optimal SnO TFT fabrication conditions are subsequently used to fabricate a complementary inverter, comprising a SnO TFT and an n-type indium gallium zinc oxide TFT, achieving a gain of up to 38 at a 1 V supply voltage. Notably, the inverter's switching point voltage is finely tuned to the ideal value, precisely half of the supply voltage. This oxide-based complementary inverter showcases promising potential in low-power electronics. [ABSTRACT FROM AUTHOR]

A c-axis aligned crystalline indium gallium zinc oxide (CAAC-IGZO) possesses unique properties beneficial for thin-film transistors (TFTs). In this study, we investigate the effect of oxygen ratio and radio frequency (RF) power on the structural, electrical, and operational characteristics of CAAC-IGZO thin films. Films were deposited on SiO2 substrates using an RF sputtering system equipped with a target containing In, Ga, Zn, and O with a composition ratio of 1:1:1:4. The effect of oxygen percentage on the structural characteristics was analyzed by X-ray diffraction (XRD), transmission electron microscopy (TEM). The oxygen percentage in the film was found to play a crucial role in forming the CAAC-IGZO and orientation of the thin films. With increasing O2 fraction, the (009)-preferred orientation of the films improved. X-ray absorption spectroscopy also validated the improved orientations of the CAAC-IGZO with high O2 concentrations up to 70%. In terms of TFT performance, however, the device with 3.3% oxygen exhibited the best performance with a saturation mobility of 10.9 cm2 V− 1 s− 1. TFT devices were prepared at a low oxygen fraction (10%) with different RF power inputs from 100 to 250 W, where the device prepared with highest power (250 W) showed the best performance. [ABSTRACT FROM AUTHOR]

The depletion of the ozone layer over the last four decades has increased Earth's exposure to ultraviolet (UV) radiation, posing significant health risks. Indium‐Gallium‐Zinc‐Oxide (IGZO) phototransistors have emerged as promising UV detection candidates, boasting a wide bandgap (>3 eV), low off‐current, high on‐current, and stability. However, previous efforts to enhance the photoresponse of IGZO phototransistors focused on visible light absorption layers, neglecting UV detection. Here, zinc oxide (ZnO) nanoparticles (NPs) as an absorption layer in IGZO TFTs for UV phototransistors are introduced. IGZO/ZnO TFTs exhibit robust photoresponsivity for UV light below 360 nm, showcasing rejection ratios (Ruv / Rvis) of 20 258, 62 261, 193 649, and 401 582 for wavelengths of 360, 340, 320, and 300 nm, respectively. The combination of IGZO's wide bandgap with ZnO NPs proves effective for detecting UV light below 360 nm, even at low incident light intensities (15 µW cm−2). Enhanced photoresponse characteristics are confirmed via ultraviolet photoelectron spectroscopy. This research highlights the potential of IGZO materials for UV phototransistors and introduces a novel perspective on the utilization of an additional absorption layer traditionally employed for the conventional extension into the visible light range. [ABSTRACT FROM AUTHOR]

The development of flexible electronics for detecting solar‐blind deep ultraviolet (UV‐C) light holds great promise for emerging technologies. Here, flexible photoelectrochemical photodetectors (PEC‐PDs) are demonstrated for self‐powered solar‐blind UV‐C sensing based on one‐step radio frequency sputtered amorphous gallium oxide (a‐Ga2O3) thin films on indium tin oxide‐coated polyethylene naphthalate (ITO/PEN) substrates in a simple and low‐cost manner. Surface functionalization of the ITO/PEN substrates with silver nanowires (Ag NWs) successfully embedded within the a‐Ga2O3 films significantly enhances the optoelectronic performance. Incorporating Ag NWs reduces charge transfer resistance and potential barrier, while enhancing built‐in electric field at the Ag NWs/a‐Ga2O3 interface, synergistically facilitating efficient electron transport. Consequently, the Ag NW‐modified PEC‐PDs exhibit approximately two‐fold increases in key metrics including responsivity (11.23 mA W−1) and response times (0.07/0.09 s rise/decay) under 254 nm illumination compared to pristine devices. Moreover, the Ag NW‐functionalized PEC‐PDs demonstrate superb mechanical flexibility and fatigue durability, maintaining ≈95% of the initial photoresponse current and responsivity after 500 bending cycles. This work provides valuable insights into designing high‐performance flexible self‐powered PEC‐PDs through ingenious photoanode engineering. [ABSTRACT FROM AUTHOR]

2D van der Waals heterojunctions (vdWH) have emerged as an attractive platform for the realization of optoelectronic synaptic devices, which are critical for energy‐efficient computing systems. Photogating induced by charge traps at the interfaces indeed results in ultrahigh responsivity and tunable photoconductance. Yet, optical potentiation and depression remain mostly modulated by gate bias, requiring relatively high energy inputs. Thus, advanced all‐optical synapse switching strategies are still needed. In this work, a reversible switching between positive photoconductivity (PPC) and negative photoconductivity (NPC) is achieved in graphene/WSe2 vdWH solely through light‐intensity modulation. Consequently, the graphene/WSe2 synaptic device shows tunable optical potentiation and depression behavior with an ultralow power consumption of 127 aJ. The study further unravels the complex interplay of gate bias and incident light power in determining the sign and magnitude of the photocurrent, showing the critical role of charge trapping and photogating at interfaces. Interestingly, it is found that switching between PPC to NPC can be also obtained at 0 mV drain‐source voltage. Overall, the reversible potentiation/depression effect based on light intensity modulation and its combination with additional gate bias tunability is very appealing for the development of energy‐efficient optical communications and neuromorphic computing. [ABSTRACT FROM AUTHOR]

Portable and personalized artificial intelligence (AI)‐driven sensors mimicking human olfactory and gustatory systems have immense potential for the large‐scale deployment and autonomous monitoring systems of Internet of Things (IoT) devices. In this study, an artificial Q‐grader comprising surface‐engineered zinc oxide (ZnO) thin films is developed as the artificial nose, tongue, and AI‐based statistical data analysis as the artificial brain for identifying both aroma and flavor chemicals in coffee beans. A poly(vinylidene fluoride‐co‐hexafluoropropylene)/ZnO thin film transistor (TFT)‐based liquid sensor is the artificial tongue, and an Au, Ag, or Pd nanoparticles/ZnO nanohybrid gas sensor is the artificial nose. In order to classify the flavor of coffee beans (acetic acid (sourness), ethyl butyrate and 2‐furanmethanol (sweetness), caffeine (bitterness)) and the origin of coffee beans (Papua New Guinea, Brazil, Ethiopia, and Colombia‐decaffeine), rational combination of TFT transfer and dynamic response curves capture the liquids and gases‐dependent electrical transport behavior and principal component analysis (PCA)‐assisted machine learning (ML) is implemented. A PCA‐assisted ML model distinguished the four target flavors with >92% prediction accuracy. ML‐based regression model predicts the flavor chemical concentrations with >99% accuracy. Also, the classification model successfully distinguished four different types of coffee‐bean with 100% accuracy. [ABSTRACT FROM AUTHOR]

Many crucial components inside electronic devices are made from non‐renewable, non‐biodegradable, and potentially toxic materials, leading to environmental damage. Finding alternative green dielectric materials is mandatory to align with global sustainable goals. Carboxymethyl cellulose (CMC) is a bio‐polymer derived from cellulose and has outstanding properties. Herein, citric acid, dextrin, and CMC based hydrogels are prepared, which are biocompatible and biodegradable and exhibit rubber‐like mechanical properties, with Young modulus values of 0.89 MPa. Hence, thin film CMC‐based hydrogel is explored as a suitable green high‐k dielectric candidate for operation at low voltages, demonstrating a high dielectric constant of up to 78. These fabricated transistors reveal stable high capacitance (2090 nF cm−2) for ≈±3 V operation. Using a polyelectrolyte‐type approach and poly‐(2‐vinyl anthracene) (PVAn) surface modification, this study demonstrates a thin dielectric layer (d ≈30 nm) with a small voltage threshold (Vth ≈−0.8 V), moderate transconductance (gm ≈65 nS), and high ON–OFF ratio (≈105). Furthermore, the dielectric layer exhibits stable performance under bias stress of ± 3.5 V and 100 cycles of switching tests. The modified CMC‐based hydrogel demonstrates desirable performance as a green dielectric for low‐voltage operation, further highlighting its biocompatibility. [ABSTRACT FROM AUTHOR]

Metal-oxide (MOx) thin-film transistors (TFTs) require complex circuit structures to cope with their depletion mode characteristics, making them applicable only to large-area active matrix (AM) displays despite their low manufacturing cost and decent performance. In this paper, we report a simple MOx 10T-2C scan driver circuit that overcomes the depletion mode characteristics using a series-connected two transistor (STT) configuration and clock signals with two kinds of low-voltage levels. The proposed circuit has a wide operating range of TFT characteristics, i.e., −2.8 V ≤ VTH ≤ +3.0 V. Through the measurement results of the manufactured sample, it was confirmed that the performance and area of our circuit are suitable for high-resolution mobile displays. [ABSTRACT FROM AUTHOR]

Hydrosilanes are highly attractive compounds, which can be processed as liquids with printing technology to amorphous silicon films on nearly any solid substrate. The silicon layers can be processed for electronic devices like transistors or thin‐film solar cells. The endothermic character of hydrosilanes with their positive enthalpies of formation results in favorable properties for processing. The larger the molecules, the lower their decomposition temperature and the higher their photoactivity. Cyclic hydrosilanes such as cyclopentasilane and cyclohexasilane can be easily deposited. The branched neopentasilane is more difficult to deposit but yields better‐quality films after processing. The key challenge is the complex synthesis of the precursors and the hydrosilanes. The available preparative methods are presented in this review and their advantages and disadvantages are evaluated. The following synthesis methods are presented and discussed in this article: Wurtz coupling and other reductive coupling processes, dehydrogenative coupling of silanes, plasma synthesis of chlorinated polysilanes, amine‐ or chloride‐induced disproportionations, and transformation of monosilane to higher silanes. Plasma synthesis is already carried out today as a continuous industrial process. The most effective synthesis methods in the laboratory are currently amine‐ and chloride‐induced disproportionations. There is a great need to further optimize the syntheses of hydrosilanes and to develop new simple synthesis variants. [ABSTRACT FROM AUTHOR]

Among various photoresponsive materials, organic materials have gained interest due to their low cost, large‐scale yields, and compatibility with flexible substrates. However, their low photoresponsivity compared to inorganic counterparts has been consistently pointed out as a limitation. To address this issue, a highly photoresponsive PM6:Y6/IGZO hybrid phototransistor is presented with a broad spectral range of 450–950 nm. The photoresponse of the device is enhanced by controlling the PM6:Y6 blending ratio, active layer thickness, and solvent additive treatment. The PM6:Y6 blending ratio and thickness are optimized to promote charge separation and efficient charge transport, leading to a significant increase in photoresponsivity. Moreover, solvent additives are employed to improve the crystallinity of the PM6:Y6 film, which further enhanced the charge transport. As a result, the PM6:Y6/IGZO hybrid phototransistor exhibited exceptional performance, with an ultrahigh photoresponsivity of 2.2 × 108 A W−1 and specific detectivity of 9.8 × 1016 Jones under 750 nm light with an intensity of only 1.03 nW cm−2. These results highlight the potential of organic materials in developing high‐performance phototransistors. [ABSTRACT FROM AUTHOR]

In this paper, the effect of a buffer layer created using different hydrogen-containing ratios of reactive gas on the electrical properties of a top-gate In-Ga-Zn-O thin-film transistor was thoroughly investigated. The interface roughness between the buffer layer and active layer was characterized using atomic force microscopy and X-ray reflection. The results obtained using Fourier transform infrared spectroscopy show that the hydrogen content of the buffer layer increases with the increase in the hydrogen content of the reaction gas. With the increase in the hydrogen-containing materials in the reactive gas, field effect mobility and negative bias illumination stress stability improve nearly twofold. The reasons for these results are explained using technical computer-aided design simulations. [ABSTRACT FROM AUTHOR]

Improving the carrier separation efficiency plays a decisive role in designing and constructing a high‐efficiency photocatalysis reaction system. Derived from providing a directional transport channel for photogenerated carriers, three‐dimensional (3D) nanostructures greatly improve the charge separation efficiency. Herein, TiO2/ZnO (TZ)/g‐C3N4 3D hierarchical nanostructure was constructed to artificially simulate photosynthesis of green plants. The optimal TZ/g‐C3N4 photoanode exhibits a photocurrent density of 1.46 mA/cm2 at 1.23 V versus reversible hydrogen electrode potential, 1.6 times that of pure TiO2 (0.9 mA/cm2). Moreover, under constant illumination (100 mW/cm2), the hydrogen production reached 80 μmol/cm2 within 180 min. It is worth noting that the TZ/g‐C3N4 photoanode shows surprising stability, which is an important indicator for the practical application of the photoelectrode. The excellent photoelectrochemical performance benefits from the following two aspects: TZ nanotree structure provides a directional transport channel for photogenerated carriers, and the modification of TZ by g‐C3N4 extends the response range to the visible region. [ABSTRACT FROM AUTHOR]

A 12.4‐inch inverted cadmium‐free electroluminescent quantum dot (QD) light emitting diode (LED) display panel based on metal oxide thin film transistors (TFTs) is demonstrated. The backplane of our panel is fabricated by using multiple steps of photolithography processes, and pixel/scan driver circuits are composed by n‐type indium‐gallium‐zinc oxide TFTs. Especially, each sub‐pixel has internal compensation circuit which compensates the threshold voltage of its own driving TFT. Different from the conventional structure, since our QD LEDs have inverted structures, electroluminescent layers from the electron injection layer to the hole injection layer are constructed by sequential inkjet‐printing processes. Our inverted electroluminescent QD LED display based on metal oxide TFTs is very promising structure for premium large‐format displays for the next generation due to its superb performance and cost‐effectiveness. [ABSTRACT FROM AUTHOR]