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Abstract Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines. During the wafer testing stage, deep learning methods are widely used in wafer defect detection due to their powerful feature extraction capabilities. However, most of the current wafer defect patterns classification models have high complexity and slow detection speed, which are difficult to apply in the actual wafer production process. In addition, there is a data imbalance in the wafer dataset that seriously affects the training results of the model. To reduce the complexity of the deep model without affecting the wafer feature expression, this paper adjusts the structure of the dense block in the PeleeNet network and proposes a lightweight network WM‐PeleeNet based on the PeleeNet module. In addition, to reduce the impact of data imbalance on model training, this paper proposes a wafer data augmentation method based on a convolutional autoencoder by adding random Gaussian noise to the hidden layer. The method proposed in this paper has an average accuracy of 95.4% on the WM‐811K wafer dataset with only 173.643 KB of the parameters and 316.194 M of FLOPs, and takes only 22.99 s to detect 1000 wafer pictures. Compared with the original PeleeNet network without optimization, the number of parameters and FLOPs are reduced by 92.68% and 58.85%, respectively. Data augmentation on the minority class wafer map improves the average classification accuracy by 1.8% on the WM‐811K dataset. At the same time, the recognition accuracy of minority classes such as Scratch pattern and Donut pattern are significantly improved.

Two-dimensional (2D) van der Waals materials have attracted great interest and facilitated the development of post-Moore electronics owing to their novel physical properties and high compatibility with traditional microfabrication techniques. Their wafer-scale synthesis has become a critical challenge for large-scale integrated applications. Although the wafer-scale synthesis approaches for some 2D materials have been extensively explored, the preparation of high-quality thin films with well-controlled thickness remains a big challenge. This review focuses on the wafer-scale synthesis of 2D materials and their applications in integrated electronics. Firstly, several representative 2D layered materials including their crystal structures and unique electronic properties were introduced. Then, the current synthesis strategies of 2D layered materials at the wafer scale, which are divided into “top-down” and “bottom-up”, were reviewed in depth. Afterwards, the applications of 2D materials wafer in integrated electrical and optoelectronic devices were discussed. Finally, the current challenges and future prospects for 2D integrated electronics were presented. It is hoped that this review will provide comprehensive and insightful guidance for the development of wafer-scale 2D materials and their integrated applications.

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics-which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al2O3 or HfO2 dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS2 monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 μF/cm2, equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10-7 A/cm2. The fabricated top-gate MoS2 transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~107, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×109 cm-2 eV-1. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

Purpose: Wafer bonding is a key process for 3 D advanced packaging of integrated circuits. It requires very high accuracy for the wafer alignment. To solve the problems of large movement stroke, position calibration error and low production efficiency in optical alignment, this paper aims to propose a new wafer magnetic alignment technology (MAT) which is based on tunnel magneto resistance effect. MAT can realize micro distance alignment and reduces the design and manufacturing difficulty of wafer bonding equipment. Design/methodology/approach: The current methods and existing problems of wafer optical alignment are introduced, and the mechanism and realization process of wafer magnetic alignment are proposed. Micro magnetic column (MMC) marks are designed on the wafer by the semiconductor manufacturing process. The mathematical model of the space magnetic field of the MMC is established, and the magnetic field distribution of the MMC alignment is numerically simulated and visualized. The relationship between the alignment accuracy and the MMC diameter, MMC remanence, MMC thickness and sensor measurement height was studied. Findings: The simulation analysis shows that the overlapping double MMCs can align the wafer with accuracy within 1 µm and can control the bonding distance within the micrometer range to improve the alignment efficiency. Originality/value: Magnetic alignment technology provides a new idea for wafer bonding alignment, which is expected to improve the accuracy and efficiency of wafer bonding. [ABSTRACT FROM AUTHOR]

Chipping has emerged as a significant issue in semiconductor manufacturing, particularly during the dicing process. The existing conventional single-sided wafer mounting technique does not have sufficient holding capability which contributes to instability during dicing and causes higher chipping performance. The objective of the study is to develop a novel wafer mounting technique that can hold the wafer firmly during dicing and improve the chipping performance. In the experiment, chipping and vibration performance during the dicing process on novel double-sided semi and full-sandwich wafer mounting were investigated and compared with the conventional single-sided wafer mounting technique. Chipping was measured using high power scope and ImageJ software while the vibration was initiated using the NI 9234 Sound-Vibration Module and SDT1-028K Piezoelectric film. Implementing extended surface tape coverage on double-sided UV mounting tape for the full sandwich wafer mounting technique resulted in superior wafer gripping during dicing and produced the lowest topside and backside wafer chipping performance. The novel double-sided full sandwich wafer mounting technique has demonstrated higher wafer holding capability, resulting in lower vibration during dicing and improved overall chipping performance [ABSTRACT FROM AUTHOR]

The paper describes the process of designing the cutting tool feed drive of a special metalworking machine, which due to the circuit solution and automatic control system will increase the productivity of processing one cell of wafer background on sheet material up to 10–15 seconds. On the basis of the analysis of the technology of milling of a given regular pattern of wafer background and peculiarities of the equipment operation it proposed to replace the traditional ball bearing gear in the cutting tool feed drive with a flat combined crank-slide mechanism. Geometrical parameters of the lever transmission mechanism calculated in accordance with the known dimensions of the regular cell pattern and the recommended value of the angle of motion transmission. The analysis of kinematic and power characteristics of the lever mechanism allowed to justify the technical characteristics of the electric motor. In order to realize the required trapezoidal law of the output link speed change, the inverse problem of kinematics solved, numerical values of the instantaneous angular velocity of the input crank and pulse control signals to the servomotor obtained.

Abstract The demand for high-resolution and large-area imaging systems for non-destructive wafer inspection has grown owing to the increasing complexity and extremely fine nature of semiconductor processes. Several studies have focused on developing high-resolution imaging systems; however, they were limited by the tradeoff between image resolution and field of view. Hence, computational imaging has arisen as an alternative method to conventional optical imaging, aimed at enhancing the aforementioned parameters. This study proposes a method for improving the resolution and field of view of an image in a lens-less reflection-type system. Our method was verified by computationally restoring the final image from diffraction images measured at various illumination positions using a visible light source. We introduced speckle illumination to expand the numerical aperture of the entire system, simultaneously improving image resolution and field of view. The image reconstruction process was accelerated by employing a convolutional neural network. Using the reconstructed phase images, we implemented high-resolution topography and demonstrated its applicability in wafer surface inspection. Furthermore, we demonstrated an ideal diffraction-limited spatial resolution of 1.7 μm over a field of view of 1.8 × 1.8 mm2 for the topographic imaging of targets with various surface roughness. The proposed approach is suitable for applications that simultaneously require high throughput and resolution, such as wafer-wide integrated metrology, owing to its compact design, cost-effectiveness, and mechanical robustness.

Abstract The field of integrated photonics has advanced rapidly due to wafer-scale fabrication, with integrated-photonics platforms and fabrication processes being demonstrated at both infrared and visible wavelengths. However, these demonstrations have primarily focused on fabrication processes on silicon substrates that result in rigid photonic wafers and chips, which limit the potential application spaces. There are many application areas that would benefit from mechanically-flexible integrated-photonics wafers, such as wearable healthcare monitors and pliable displays. Although there have been demonstrations of mechanically-flexible photonics fabrication, they have been limited to fabrication processes on the individual device or chip scale, which limits scalability. In this paper, we propose, develop, and experimentally characterize the first 300-mm wafer-scale platform and fabrication process that results in mechanically-flexible photonic wafers and chips. First, we develop and describe the 300-mm wafer-scale CMOS-compatible flexible platform and fabrication process. Next, we experimentally demonstrate key optical functionality at visible wavelengths, including chip coupling, waveguide routing, and passive devices. Then, we perform a bend-durability study to characterize the mechanical flexibility of the photonic chips, demonstrating bending a single chip 2000 times down to a bend diameter of 0.5 inch with no degradation in the optical performance. Finally, we experimentally characterize polarization-rotation effects induced by bending the flexible photonic chips. This work will enable the field of integrated photonics to advance into new application areas that require flexible photonic chips.

Abstract A self‐confined solid‐state dewetting mechanism is reported that can fundamentally reduce the use of sophisticated nanofabrication techniques, enabling efficient wafer‐scale patterning of non‐closely packed (ncp) gold nanoparticle arrays. When combined with a soft lithography process, this approach can address the reproducibility challenges associated with colloidal crystal self‐assembly, allowing for the batch fabrication of ncp gold arrays with consistent ordering and even optical properties. The resulting dewetted ncp gold nanoparticle arrays exhibit strong surface lattice resonance properties when excited in inhomogeneous environments under normal white‐light incidence. With these SLR properties, the sensitive plasmonic sensing of molecular interactions is achieved using a simple transmission setup. This study will advance the development of miniaturized and portable devices.

Abstract Organic field‐effect transistors switched by insulated gates are the most essential building blocks, while usually plagued with degraded gate control arising from complicated dielectric engineering. Subsequently, the resulting large supply voltage and power consumption remain an essential issue for portable electronics driven by a single battery of only 1.5 V. Herein, wafer‐scale organic Schottky‐gate transistor arrays using inkjet‐printed few‐layer organic semiconducting crystals are reported. The transistors exhibit steep switching characteristics with an average subthreshold swing of 55 mV per dec and high signal amplification efficiency over 45 S A‐1, attributed to efficient Schottky gating and enhanced charge injection. Thereafter, high‐gain inverters are successfully demonstrated with an ultralow power consumption of only 800 pW; also, they are integrated as 1 V driven sequential logic circuits. A coplanar double‐gate geometry is also introduced for low‐voltage, single‐device AND logic. Therefore, the work opens new avenues toward the sustainable advancement in single‐battery‐driven, ultralow‐power organic electronics.