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This paper presents a novel readout circuit for a pH sensitive Programmable-Gate Ion-Sensitive Field Effect Transistor (PG-ISFET) to overcome bias issues due to threshold voltage variation and increase output-referred sensitivity. Compared to other commonly-used ISFET readouts, this circuit uses two extra programmable nodes which are driven by a feedback configuration. Using the device in a source follower configuration, one node is used to evaluate and cancel the offset of the intrinsic device while the other tracks and amplifies changes in pH. A sample and hold protocol has been developed to minimize the leakage effects and improve the pH sensing range. The system has been designed and fabricated in AMS 0.35µm, to compensate for a threshold voltage variation of ±10.5V and provide a pH sensitivity of 200mV/pH.

Neuroprosthetics is a relatively new topic but it has already shown its potential. Since the application of this science, it has already significantly improved the quality of life of over 60,000 individuals who previously suffered from severely impaired hearing or total deafness. Today, through use of cochlear implants, children born totally deaf can enjoy going to regular schools and communicating normally. Individuals suffering from dizziness and balance disorders can also benefit from the progress made in cochlear prosthetics. The inner ear's vestibular system provides cues about self-motion and help stabilise vision during movement. Damage to this system can result in dizziness, imbalance, blurred vision and instability in locomotion, a leading cause of death in the elderly. We propose a hybrid CMOS/MEMS platform for bypassing a dysfunctional pathway in individuals that suffer from balance-related disorders. Combining MEMS-based inertia sensing with CMOS-based neural monitoring and processing electronics, this prosthesis aims to deliver a corrective artificial stimulus to the vestibulocochlear (VIII) nerve. We describe a novel system outlining the architectural aspects and implementation methodology used in the design.

This paper presents a batch encapsulation technique for CMOS based chemical sensors. SU-8 photoresist is employed as the encapsulant while the sensing membrane of the sensor is directly exposed to the solution. This approach is based on standard photolithographic techniques and thus can be used for processing multiple dies containing chemical sensors in a single step.

This demonstrator presents an ultra low power mixed-signal implementation of a cochlear prosthesis system. A laptop PC provides an audio stimulus to the cochlear chip. A microcontroller on the demonstrator board monitors the output channels of the chip and returns these to the PC to be displayed as a spectrogram. The audiological settings of the implant chip are controlled via a GUI running on the PC.

This work presents an eight channel neural stimulator interface based on an address event communication protocol. The system developed decodes, integrates and interleaves the spike patterns using a continuous interleave sampling (CIS) strategy, which drives a complex biphasic current waveform to a bipolar electrode configuration. This paper describes the basic concept, circuit design, simulation results and hardware implementation in a standard 0.35mum CMOS technology

A spiking chemical sensor (SCS) is presented for detection of neurogenic ion concentration associated with active nerve fibres in nerve bundles. Based on the "integrate-and-fire" circuit, the SCS uses a chemically-modified ISFET front end encoding the sense data in the spike domain. Used in an array, it provides a spatio-temporal map of chemical activity around the nerve bundle which may be relayed off chip using low power asynchronous communication hardware. The circuit is shown to be tunable to yield a linear relation with either pH or actual hydrogen ion concentration. Furthermore, its compact pixel footprint in addition to efficient use of the sensing surface, makes it ideal for use in neuro-chemical imaging.

An ISFET-based integrate and fire neuron, forming the front-end of a chemical pixel sensor, is introduced. With the sense data being encoded in the spike domain, i.e. asynchronous/continuous time and discrete value, it is directly compatible with asynchronous communication hardware, e.g. address event representation. The circuit is shown to be tunable to yield a linear relation with both pH and actual hydrogen ion concentration, with a peak power consumption of 35 muW. Furthermore, its compact pixel footprint of under 6500 mum 2 , makes it ideal for use in arrayed architectures with application in biochemical imaging

A hybrid vision chip is presented for real-time object-based processing for tasks such as positioning and sizing of enclosed objects. This system presents the first artificial silicon retina capable of position and size determination of multiple objects in true parallel fashion. Based on a novel distributed algorithm, this approach uses the input image to enclose a feedback loop to realise a data-driven pulsating action. The fabricated device is shown to achieve a computation-efficiency of at least 725 million instructions per second per milliwatt and capable of processing up to 2000 frames per second.

In this work we present an adaptable foveating vision chip. This chip has no physical foveation; all its pixels are in the same uniform pattern. However with a given input signal it is possible to define areas of the chip which act as a fovea, returning high spatial resolution. The surrounding peripheral vision acts to return lower spatial resolution but much higher temporal resolution. Our chip is therefore able to achieve full spatial resolution via scanning of the fovea across the visual field. This operation is analogous to the functioning of the human eye. In the human eye however, the limitations of biology enforce a fixed fovea, while the optomechanics are highly efficient. In our structure, we acknowledge the limitations of physical optomechanics but use the advantages of silicon processing to achieve dynamic foveation. This paper discusses the algorithm, its implementation and simulated results describing its responses and power consumption.

In this work we present an adaptable spike generator circuit for intelligent vision chips. Our aim is to realize an adaptable vision chip which can adjust for localized gain control, wide dynamic range, high temporal response, high spatial resolution and low power. To this end we have developed pulse frequency modulation spike encoder which is capable of providing very high dynamic ranges with power consumption similar to animal retina. At lower dynamic ranges, frequency responses of over 2kHz is possible. Our circuit is based on the on-off opponency algorithm used by the human eye, and allows for integration of other functions such as tomographic increase in spatial resolution and information compression. Both silicon area and power consumption are kept to a minimum. This paper discusses the algorithm, its implementation and simulated results describing its response and power consumption.

A useful nanopower circuit is presented for edge detection in integrated vision systems. Based on a compact front-end of only five MOS devices, this circuit features a tunable threshold and discrete output; ideal for interfacing to digital electronics.

A novel and robust distributed architecture for real-time object-based processing is presented for tasks such as object size, centre and count determination. This approach uses the input image to enclose a feedback loop and realise a data-driven pulsating action, ideally suited for implementation in standard CMOS technologies.

A floating-gate pseudo-differential transconductor is presented, in which the differential input signal is allowed to have a dc offset. Normally such an offset would render a normal CMOS differential pair useless. The circuit inherently removes any dc offset from the floating gates by feedback mechanisms involving Fowler-Nordheim electron tunneling and hot-electron injection. This technique can enable direct cascading of several cells without amplifying and accumulating offsets, or can be used to generate differential current mode signals from a single voltage source that has a dc offset, as with an electret microphone.

A novel architecture for running cross-correlation and convolution using bitstream processing is proposed. The computationally intensive multiplications inherent in cross-correlation and convolution are replaced by simple logic operations (AND XOR) using bitstream representation. The reduced complexity enables compact and energy efficient silicon solutions suitable for small, portable devices such as wearable heartbeat detecting electronics embedded in the actual ECG patch.

An adaptive spike generator circuit for intelligent vision chips is presented. A pulse frequency modulation spike encoder, capable of providing very high dynamic ranges with power consumption similar to an animal retina, has been developed. The circuit is inspired by the ON-OFF opponency algorithm used by the human eye.

A robust distributed architecture for real-time object-based processing is presented for tasks such as object size, centre and count determination. This approach uses the input image to enclose a feedback loop to realize a data-driven pulsating action. Outlined is the top level design for hardware implementation in a standard CMOS technology.

This paper presents a novel implantable electro-chemical sensor with a built-in readout circuit, with an ultimate aim of measuring dopamine levels in human striatum. The chosen material as the ultra-micro electrode (UME) of the sensor is niobium wire around which a carbon nanospike layer is grown (Nb/CNS) by means of plasma-enhanced chemical vapor deposition. The main focus of this paper is the design of an ultra-low-power wide-range dual-slope analog-to-digital converter that is specifically designed for an Nb/CNS probe to measure Fast-Scan Cyclic Voltammetry (FSCV) current pulses within the range of +/- 2.56 mu A. The dual-slope ADC has a sampling rate of 10 kHz with a 10 MHz clock frequency while requiring an average power consumption of 1.57 mu W. The circuit has a root-mean-squared input noise of 30 pA, a resolution of 100 pA and a dynamic range of 58 dB with a 10-bit output.