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A neural network IC based on a dynamic charge injection is described. The hardware design is space and power efficient, and achieves massive parallelism of analog inner products via charge-based multipliers and spatially distributed summing buses. Basic synaptic cells are constructed of exponential pulse-decay modulation (EPDM) dynamic injection multipliers operating sequentially on propagating signal vectors and locally stored analog weights. Individually adjustable gain controls on each neutron reduce the effects of limited weight dynamic range. A hardware simulator/trainer has been developed which incorporates the physical (nonideal) characteristics of actual circuit components into the training process, thus absorbing nonlinearities and parametric deviations into the macroscopic performance of the network. Results show that charge-based techniques may achieve a high degree of neural density and throughput using standard CMOS processes.

Results are presented from a preliminary study on the effects of weight decay and resolution on the performance of typical three-layer, feedforward neural networks. Two types of decay are investigated, unilateral decay toward the most negative weight (unipolar) and bilateral decay toward the median or zero weight value (bipolar), and compared with Gaussian weight perturbations. This analysis is pertinent to the area of VLSI-based network implementations with analog weight storage. The results show that, if weight decay is unavoidable, bipolar decay achieves an order-of-magnitude better performance than unipolar and that the weight resolution required in actual implementations of feedforward, connectionist hardware is higher than predicted by computer simulations of network responses to random or Gaussian weight perturbations.