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Several approaches to reduce the form factor of packaged systems by using the third physical dimension are described in this chapter. Important commercial methods, such as system-in-package (SiP) and interposer-based (2.5-D) technologies are included. The most recent developments in the manufacturing of 2.5-D systems are reviewed. In addition to mainstream packaging techniques, such as SiP, other approaches that have been prototyped but have yet to reach high volume manufacturing are discussed, covering the entire spectrum of three-dimensional packaging. Particular attention is placed on the fabrication of interposers, as this integration technology has only recently appeared in the marketplace and is expected that new interposer-based products will soon appear.

Miniaturization and advanced manufacturing of MEMS technologies have allowed their integration in compact and wearable sensing devices, opening the way to advanced applications in human motion analysis, activity recognition, and health monitoring. The limited form factor and the need for comfortable solutions open interesting research challenges, which will be illustrated in this chapter. The reader will be introduced to hardware and software development of wearable MEMS solutions that provide advanced sensing, processing, and communication capabilities, with limited power consumption and adequate ergonomic characteristics. The general development scenario and tools will be illustrated through the design of a wearable inertial measurement unit, which will be shown in healthcare applications for gait analysis, rehabilitation, and assessment of physical conditions.

Large touch screens are an increasingly common platform for education. Effective design for this form factor will directly influence the effectiveness of these screens as educational tools. The sheer size of a large touch display can bring up issues related to distal access of touch targets and limited field of vision. The visibility of the screen at a distance and the ability for large groups to gather in front of such a display also mean that designers must create applications that are effective teaching tools for proximal visitors who only see part of the screen as well as attractive for distal visitors who see the screen from afar. We discuss our approach to these design challenges through the iterative design and qualitative evaluation of a touch screen exhibit about the life of Alfred Nobel hosted on an 82-inch touch screen. From this early investigation into the efficacy of large displays as informal educational tools, we present practical guidelines for designers working with this form factor.

This chapter focuses on the reasons behind starting a small spacecraft program. In this context, both programs started for educational benefit and those launched for research or other purposes are considered. An overview of reasons for program initiation is provided. Then, research and educational benefits are discussed. Broader benefits that could be provided by a small spacecraft program to society-at-large are then considered. Finally, the chapter discusses the potential of using a small spacecraft program to develop, demonstrate, or advance national space competency, before concluding.

This study analyzes the use of a Raspberry Pi (RPi) as part of a Penetration Tester’s toolkit. The RPi’s form factor, performance to cost ratio, used in conjunction with modified Linux, allows the RPi to be a very versatile product. Whatsmore, the RPi retails for $35 and is available from many hobby shops and on Amazon.com. Included in this research is the use of a virtual lab where the RPi is attached using an Ethernet connection. Simple attacks are carried out with a few suggestions for preventing this scenario from playing out in the real world.

The advantages associated with neuromorphic computation are rich areas of complex research. We address the fabrication challenge of building neuromorphic devices on structurally foldable platform with high integration density. We present a CMOS compatible fabrication process to demonstrate for the first time memristive devices fabricated on bulk monocrystalline silicon (100) which is next transformed into a flexible thin sheet of silicon fabric with all the pre-fabricated devices. This process preserves the ultra-high integration density advantage unachievable on other flexible substrates. In addition, the memristive devices are of the size of a motor neuron and the flexible/folded architectural form factor is critical to match brain cortex's folded pattern for ultra-compact design.

Recent TSV based 3D Integrated Circuit (IC) technology needs more powerful thermal management techniques. However, because cooling cost and form factor are restricted, thermal management are emphasis on software based techniques. But in case of throttling thermal management which one of the most candidate technique, increasing bus occupation induce total performance decrease. To solve communication bottleneck issue in TSV based 3D SoC, we proposed adaptive throttling technique Experimental results show that the proposed method can improve throughput by about 72% compare with minimal path routing.

Large market growth in head-mounted and wearable displays is predicted in the near future covering applications areas such as sport, security and entertainment. These application areas are often cost sensitive and form factor critical. In this paper two novel CMOS microdisplays are presented for application in wearable sports and head-mounted display applications. The microdisplays are implemented in a standard 0.35 μm CMOS process requiring no post-processing. The presented microdisplays offer a cost effective alternative to conventional LC and OLED-based displays, while maintaining a small form factor.

Although the use of augmented reality has been well described over the past several years, available devices suffer from high cost, an uncomfortable form factor, suboptimal battery life, and lack an app-based developer ecosystem. This article describes the potential use of a novel, consumer-based, wearable device to assist surgeons in real time during limb preservation surgery and clinical consultation. Using routine intraoperative, clinical, and educational case examples, we describe the use of a wearable augmented reality device (Google Glass; Google, Mountain View, CA). The device facilitated hands-free, rapid communication, documentation, and consultation. An eyeglass-mounted screen form factor has the potential to improve communication, safety, and efficiency of intraoperative and clinical care. We believe this represents a natural progression toward union of medical devices with consumer technology.

Architectural Form Factor Xue Minghui1, a, Zhang Hongzhe2,b, Liu Nan3,c1 Harbin Institute of Technology School of Architecture, China 2 Harbin University of Science And Technology, China 3 Northeast Forestry University, China aminghui1220@126.com, bzhanghongzhe126@126.com,c5484913@qq.com Keywords: Architectural Form ,Abstract Factor, Extenics Design Analysis Abstract. Architectural form factor is the reflection of architectural surface and decide its forms. This paper use extenics design analysis and make analysis on architectural design examples from four basic elements including point, line, surface, body. It is aimed at making better and clear relationship of abstract elements and finding the content in architectural design forms.

The increasing adoption of advanced wafer-level packaging (WLP) technologies and high density interposer concepts clearly reflect the permanent need for form factor reduction, smaller process geometries and higher-count I/O on ICs. Currently, several strategies are being pursued to achieve these goals. The most promising approaches are summarized under the concept of three-dimensional integrated circuits (3D-IC) and three-dimensional wafer level packaging (3D-WLP) technology. A key component for 3D device integration schemes is the requirement of vertical through-silicon-via (TSV) interconnections that enables electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias. Despite the potential benefits associated with the integration of TSVs also significant challenges have to be overcome. One of the greatest challenges for present and even more for upcoming TSV design strategies still remains the processing of photoresist and other functional polymers at and within TSV geometries. To this day, it is still very difficult to achieve a conformal polymer coating in deep cavities, along steep side walls and especially within the extreme aspect ratios of TSV. Mainly this is due to the fact that standard surface coating methods such as spin coating were just not developed to meet the requirements posed by these high aspect ratio microstructures. New and innovative approaches are needed to meet these new challenges. Spray coating is one of the most promising technologies to overcome current barriers. However, even most of the available spray deposition equipment is facing its limits with steadily decreasing via diameters and increasing aspect ratios on the other hand. Successively, the multitude of these challenging technological developments in the 3D-IC and wafer-level packaging area has created the demand for innovative manufacturing approaches, new equipment and related tools. Herein we present our new EVG ®NanoSprayTM coating technology with unique capabilities to overcome the present limits of conformal resist coating over extreme topography. We demonstrate one particularly promising application for conformal polymer coatings; as an annular lining at the interface between the conducting metal filling in the TSV and the silicon wafer. The intrinsic properties of the polymer allow a TSV design solution that is more forgiving on coefficient of thermal expansion (CTE) mismatch-induced stress between the silicon substrate and the interfacing metal. Consequently, this new type of polymer buffered TSV interconnect design promises to significantly reduce thermal stress-induced TSV delamination as one of the dominant failure modes for 3-D interconnects. We further demonstrate the application of EVG ®NanoSprayTM as enabling coating technology for llithographic processing of conformal coated TSVs. The patterning of thin photoresist layers at the bottom of vias and along the steep sidewalls of deep cavities allows for more degrees of freedom in electrical contact formation. The presented EVG ®NanoSprayTM coating technology opens new dimensions in advanced wafer level packaging and provokes reconsidering prevailing limitations in interconnect design.

We present a survey of pointing devices for wearable computers, which are body-mounted devices that users can access at any time. Since traditional pointing devices (i.e., mouse, touchpad, and trackpoint) were designed to be used on a steady and flat surface they are inappropriate for wearable computers. Just as the advent of laptops resulted in the development of the touchpad and trackpoint, the emergence of wearable computers is leading to the development of pointing devices designed for them. However, unlike laptops, since wearable computers are operated from different body positions under different environmental conditions for different uses, researchers have developed a variety of innovative pointing devices for wearable computers characterized by their sensing mechanism, control mechanism, and form factor. We survey a representative set of pointing devices for wearable computers using an “adaptation of traditional devices” versus “new devices” dichotomy and study devices according to their control and sensing mechanisms and form factor. The objective of this paper is to showcase a variety of pointing devices developed for wearable computers and bring structure to the design space for wearable pointing devices. We conclude that a de facto pointing device for wearable computers, unlike laptops, is not likely to emerge.

The long-term trend in automobiles has been increasing electronics content over time. This trend is expected to continue and drives diverse functional, form factor, and reliability requirements. These requirements, in turn, are leading to changes in the package types selected and the performance specifications of the packages used for automotive electronics. Several examples will be given. This abstract covers the development of a distributed high temperature electronics demonstrator for integration with sensor elements to provide digital outputs that can be used by the FADEC (Full Authority Digital Electronic Control) system or the EHMS (Engine Health Monitoring System) on an aircraft engine. This distributed electronics demonstrator eliminates the need for the FADEC or EHMS to process the sensor signal, which will assist in making the overall system more accurate and efficient in processing only digital signals. This will offer weight savings in cables, harnesses and connector pin reduction. The design concept was to take the output from several on-engine sensors, carry out the signal conditioning, multiplexing, analogue to digital conversion and data transmission through a serial data bus. The unit has to meet the environmental requirements of DO-160 with the need to operate at 200°C, with short term operation at temperatures up to 250°C. The work undertaken has been to design an ASIC based on 1.0 μm Silicon on Insulator (SOI) device technology incorporating sensor signal conditioning electronics for sensors including resistance temperature probes, strain gauges, thermocouples, torque and frequency inputs. The ASIC contains analogue multiplexers, temperature stable voltage band-gap reference and bias circuits, ADC, BIST, core logic, DIN inputs and two parallel ARINC 429 serial databuses. The ASIC was tested and showed to be functional up to a maximum temperature of 275°C. The ASIC has been integrated with other high temperature components including voltage regulators, a crystal oscillator, precision resistors, silicon capacitors within a hermetic hybrid package. The hybrid circuit has been assembled within a stainless steel enclosure with high temperature connectors. The high temperature electronics demonstrator has been demonstrated operating from −40°C to +250°C. This work has been carried out under the EU Clean Sky HIGHTECS project with the Project being led by Turbomeca (Fr) and carried out by GE Aviation Systems (UK), GE Research – Munich (D) and Oxford University (UK).

Battery life extension is the principal driver for energy-efficient wireless sensor network (WSN) design. However, there is growing awareness that in order to truly maximize the operating life of battery- powered systems such as sensor nodes, it is important to discharge the battery in a manner that maximizes the amount of charge extracted from it. In spite of this, there is little published data that quantitatively analyzes the effectiveness with which modern wireless sensor nodes discharge their batteries, under different operating conditions. This paper focuses on discharge profiles of battery under different conditions which could play a vital role in the life time of the wireless sensor networks. Power consumption is the limiting factor for the functionality offered by portable devices that operate on batteries. This power consumption problem is caused by a number of factors. Users are demanding more functionality, more processing, longer battery lifetimes, and smaller form factor and with reduced costs. Battery technology is only progressing slowly; the performance improves just a few percent each year. Mobile devices are also getting smaller and smaller, implying that the amount of space for batteries is also decreasing. Decreasing the size of a mobile device results in smaller batteries, and a need for less power consumption.

This chapter proposes a mechanism for securely updating IoT devices across networks and devices of any form factor or function. While not an exhaustive list, several of the problems are administering devices, proper authentication and authorization, securing communications, and firmware security. The chapter addresses updating IoT devices which is an essential part of IoT security. It defines an update as either updating both the operating system and application or just either the application or operating system running on an IoT device. The chapter addresses performing updates to IoT devices in a manner that is secure, and is also based on security standards that the IoT device will need to implement to carry out its functions. The goal of this secure update mechanism is to make recommendations that would cause minimal increases in processing and memory requirements so that it could be used by IoT devices running on constrained platforms and on constrained networks.

This paper explores experiences with ring and bracelet activity tracker form factors. During the first week of a 2-week field study participants (n=6) wore non-functional mock-ups of ring and bracelet wellness trackers, and provided feedback on their experiences. During the second week, participants used a commercial wellness tracking ring, which collected physical exercise and sleep data and visualized it in a mobile application. Our salient findings based on 196 user diary entries suggest, that the ring form factor is considered beautiful, aesthetic and contributing to the wearer's image. However, the bracelet form factor is more practical for active lifestyle, and preferred in situations where the hands are performing tasks requiring gripping objects, such as sport activities, cleaning the car, cooking and washing dishes. Users strongly identified the ring form factor as jewellery that is intended to be seen, whereas bracelets were considered hidden and inconspicuous elements of the user's ensemble.

In this paper, a summary of various sensory technologies and interactions within them in wearable platforms is presented. In the first part of the paper, we discuss the way humans perceive various sensory inputs. Then, we review today's state of art sensor technologies for user interfaces, followed by discussions on opportunities uniquely enabled by the wearable form factor.

This paper discusses the idea of light-based Internet of Things (LIoT), in which light is exploited in two ways, namely, to harvest the energy needed to power up an IoT node, and to provide the node with wireless connectivity using optical links. The LIoT concept can be seen as an “Expose-and-Connect” (E&C) approach, where an energy-autonomous node is wirelessly connected to internet when it is exposed to light. This concept creates an extraordinarily wide array of possible use cases and novel applications. The basic principles of this approach are discussed, including different access architectures and implementation techniques. The role of printed electronics (PE) as a highly attractive implementation technology for LIoT is also discussed in the paper. Very thin printable tags could be created with PE, featuring a number of integrated functionalities, including wireless communications. These tags could be manufactured at very low cost and with any form factor, converting virtually any object on which they are attached, into an IoT node. The LIoT approach is further extended to encompass a much generic and powerful concept called Living Surfaces (LS), where virtually any surface, small or large, can contain different functionalities onboard, such as energy harvesting and storing, sensors and actuators, signal processing and wireless communications. With the advances in PE technology, it is foreseen that every available surface will be provide an opportunity to have on it one or more autonomous nodes, each with a range of possible capabilities. Applications of the LS concept are also discussed. Finally, technical challenges as well as visions for further development are also presented.

Waveguide or lightguide technology has been widely used in the state-of-the-art, see-through, near-eye displays to reduce system weight and form factor. Although a few of the current products use a geometrical lightguide as an optical combiner, its design and performance assessment methods have been barely discussed. In this paper, by taking into account the factors affecting retinal image quality, we presented novel methods for quantifying and evaluating the optical performances and artifacts of geometrical lightguides based on microstructure mirror arrays, and proposed new merit functions and a novel process for systematic optimization of such lightguides. A lightguide design example implementing the evaluation and optimization methods are demonstrated, and the resulted lightguide is then further utilized as a combiner for the design of a lightweight, glasses-like, see-through, near-eye display.

Control and monitoring of experimental facilities as well as laboratory equipment requires handling a blend of different tasks. Often in industrial or scientific fields there are standards or form factor to comply with and electronic interfaces or custom busses to adopt. With such tight boundary conditions, the integration of an off-the-shelf Single Board Computer (SBC) is not always a possible or viable alternative. The availability of electronic schematics and PCBs with open-source Hardware license for various SBCs overcomes such integration problems, making feasible the implementation of a custom architecture composed by a central core inherited from a vendor reference design (most likely the microprocessor, static RAM and flash memory) augmented with application-specific integrated circuits and hardware resources, in order to handle the requirements of the specific environment. The user is then able to exploit most of the supported tools and software provided by opensource community, fulfilling all the constraints enforced by his environment. We have used such an approach for the design and development of the monitoring system of the endcap electromagnetic calorimeter of the Belle II experiment, presently running at KEK Laboratory (Tsukuba, Japan). Here we present and discuss the main aspects of the hardware architectures and noise performances tailored on the needs of a detector designed around CsI crystal scintillators.

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

Western societies all see their healthcare costs outpace GDP growth. To reverse this trend, several public and private initiatives were taken in the last years to make healthcare more cost efficient. It is anticipated that micro and nano-system technology will help enable an increase in the functionality of lifestyle and healthcare devices to gradually reduce cost. This builds on the scaling of mi-croelectronics that additionally provides opportunities for reducing both form factor and power requirements. In the next decade, body area network technology will be one of the advancements that provides medical, lifestyle, as-sisted living, sports or entertainment functions for the us-er. Such a network comprising a series of miniature sen-sor nodes, implanted or located around the body should be able to communicate with other sensor nodes and/or with a gateway node that provides a connection to the outside world using a standard telecommunication infra-structure. Early deployment of technology in different application cases are translated into critical technology obstacles that need to be solved in order to enable wide-spread deployment. For the development of smaller and smarter systems with ever increasing autonomy, key technological challenges are addressed at the level of sensors, energy harvesting, ultra-low-power DSP, wire-less connectivity, and integration and packaging. Healthcare expenditure increase of a few selected coun-tries (OECD data (OECD Health Data, http://www.oecd.org, accessed Jan. 10, 2013) showing a dramatic increase compared to the GDP.

Precise monitoring of human body signals can be achieved by soft, conformal contact and precise arrangement of wearable devices to the desired body positions. So far, no design and fabrication methodology in soft wearable devices is able to address the variations in the form factor of the human body such as the various sizes and shapes of individual body parts, which can significantly cause misalignments and the corresponding inaccurate monitoring. Here, a concept of soft modular electronic blocks (SMEBs) enabling the assembly of soft wearable systems onto human skin with functions and layouts tailored to the form factors of individuals' bodies is presented. Three types of SMEBs are developed as fundamental building blocks for functional modularization. The physical design of SMEBs is optimized for a mechanically stable island‐bridge configuration. The prepared SMEBs can be integrated onto a target body part through rapid, room‐temperature (RT) assembly (

Generally, form factor is determined through ITTC method. Determining the form factor from ITTC method includes the assumption that the form factor of a full-scale ship is the same value as its model ship. In other words, the form factor is independent on Reynolds number. However, for the more appropriate prediction of the resistance performance of a full-scale ship, the form factor must be determined with the consideration of the variation attendant on Reynolds number. In this research, several Geosim ship models are adopted to investigate the scale effect, and correlation lines of form factor are improved to suggest the better extrapolation method for the prediction of the form factor of full-scale ship. The corrected form factors using the correlation lines are compared with those determined from the results of low-speed resistance tests. To consider the influence of hull form, the correlation lines are determined for the group of high-speed ships and the group of low-speed ships, respectively. The corrected form factors have shown good agreement among the prediction results from each Geosim ship model to the full-scale ship.

Lighting consumes a significant amount of generated electrical power in developing countries, and it uses over 20% of the energy supplied in developed countries. Therefore, semiconductor-based light sources with high energy efficiencies are critical technologies for the reduction of global carbon footprint. As an emerging lighting technology, organic light-emitting diode (OLED) has received huge worldwide attention in recent years, partially driven by its success in the flat-panel display market and partially driven by its technology virtues such as an unique thin, flat, foldable form factor. In this review, we will provide an overview on the current status of OLEDs for lighting applications. Specifically, a detailed overview of the state-of-the-art white OLED design concepts including their working principles will be presented. A brief overview on the current status of out-coupling techniques suitable for white OLEDs will also be discussed.

As smartphones are rapidly and widely spread, their applications request gradually larger computation power. Recently, in the personal computer, computing power of hardware has exceeded performance requirement of software sometimes. Computing power of smartphone, however, will not grow at the same pace as demand of applications because of form factor to seek thinner devices and power limitation by relatively slow technical progress of battery. Computation offloading is getting huge attention as one of solution for the problem. It has not commonly used technology in spite of advantages for performance and power consumption since the existing offloading frameworks are difficult for application developer to utilize. This paper presents an application developer-friendly offloading framework, named SorMob. Based on Aspect Oriented Programming model, SorMob provides a convenient environment for application development, and its performance was verified by comparing with the existing offloading framework.Keywords:Computation Offloading, AOP

The ability to monitor and sense environmental conditions in real time over large areas is a difficult and expensive task, especially when it comes to monitoring in harsh environments. Whether it is monitoring suspension bridges that experience immense forces from storms and earthquakes for structural integrity, detecting noxious gases in manufacturing facilities, or making sure the vegetables on the supermarket shelf are still fresh and being kept at the correct temperature and humidity level, these sensors and sensor networks have the ability to greatly improve cognitive intelligence and knowledge of the environment around us, that is, as long as they come at the right price. Current methods for deploying large-scale sensor networks involve miles of cabling that source power and collect data, or battery operated wireless sensors, which pose a serious environmental risk with the disposal of billions of batteries every year. While these methods are necessary in some situations where real-time data or harsh environments prohibit manual monitoring of critical environment parameters, the cost, installation difficulty, and maintenance rarely justify their use over manual inspections and monitoring. This is where the concept of smart skins comes in. Smart skins are cognitive, intelligent skins that sense, wirelessly communicate, and, in the future, will be able to modify environmental parameters using simple passive RFID technology. These skins can be applied everywhere be it a shelf lining in a grocery store or the outside of a Boeing 787, all while maintaining an unobtrusive and lightweight form factor similar to the application of a decal sticker. Smart skins are zero-power devices meaning they scavenge their own energy using ambient electromagnetic, solar, thermal, mechanical, or RFID/Radar-based interrogation techniques. In short, smart skins could prove to be the ultimate sensing tool that could potentially allow for the mass implementation of perpetual wireless networks even in extremely rugged environments. The system overview of a conventional smart skin is shown in Figure 1, which shows a skin consisting of several types of sensors that can be uniquely identified in a sensing matrix, and an interrogation network that is used to poll/interrogate the sensors and relay the data back to a processing hub. This allows realtime knowledge of various sensed parameters, such as the stress gradients due to trucks passing over bridges, or of the propagation rate of a gas leak or fire within a building. The smart skin concept can also be extended to that of body-wearable skins for continuous monitoring and reporting of critical biosignals utilizing novel liquid antenna principles. Biocompatibility and wearability requirements further push the need for autonomous, self-powering sensors.

With the development of 3D integration technology, microsystems with vertical interconnects are attracting attention from researchers and industry applications. Basic elements of integrated passive devices (IPDs), including inductors, capacitors, and resistors, could dramatically save the footprint of the system, optimize the form factor, and improve the performance of radio frequency (RF) systems. In this paper, IPDs using thin film built-up technology are introduced, and the design and characterization of coplanar waveguides (CPWs), inductors, and capacitors are presented.

Inertial sensors based on MEMS technology are fast becoming ubiquitous with their adoption into many types of consumer electronics products, including smart phones, tablets, gaming systems, TV remotes, toys, and even (more recently) power tools and wearable sensors. Now a standard feature of most smart phones, MEMS-based motion tracking enhances the user interface by allowing response to user motions, complements the GPS receiver by providing dead-reckoning indoor navigation and supporting location-based services, and holds the promise of enabling handset optical image stabilization in next-generation handsets by virtue of its lower cost and small form factor. This tutorial provides an overview of MEMS technology and describes the essential features of the mechanical systems underlying the most common sensors accelerometers and gyroscopes. It also highlights some fundamental trade-offs related to mechanical system dynamics, force and charge transduction methods, and their implications for the mixed-signal systems that process the sensor outputs. The presentation of an energy-based metric allows a comparison of the performance of competing sensor solutions. For each type of sensor, descriptions of the underlying mechanical theory, canonical sensor architectures, and key design challenges are also presented. Finally, the tutorial reviews multisensor silicon MEMS/CMOS monolithic integration, which is driving the cost and form factor reduction behind the current proliferation of these devices.

Fan-Out Wafer Level Packages provide a flexible assembly platform for single die, multi-chip, and 3D structures in a minimal form factor. As a result, the FO-WLP has gained rapid acceptance as a competitive package in the fast growing market of mobile devices. The eWLB version of FO-WLP has achieved the greatest commercial success, with millions of units already assembled and shipped in mobile phones. Although multi-chip structures have been discussed previously, one capability of the technology that has not received wide attention is the incorporation of passive devices into the packages. There are two common implementations of 3D packaging with the FO-WLP technology. The first is fan-out packages with one sided redistribution layers (RDL) using laser drilled vias to enable the direct mount of top packages. The second is two sided packages with through-mold vias that enable RDL on both the top and the bottom of the package. Using multichip embedding technology, it is possible to embed discrete components such as capacitors, resistors, or inductors into the body of the fan-out package in very close proximity to the active device. This close proximity to the active device combined with Cu RDL routing provides exceptional performance for decoupling capacitors and other passive devices. In a two sided RDL implementation, routing can be provided on the top of the package to enable integrated inductors and pads for direct mounting of additional passive components. This two sided implementation can reduce the combined board footprint of active devices and their required passives through the use of 3D integration. This presentation will discuss the various implementations of embedded passives in the 3D FO-WLP and the form factors that can be achieved with this solution.

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size > 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements. This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.

With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. With aperture geometries shrinking, anything which can influence solder paste transfer efficiency has to be considered. New process technologies such as ultrasonic squeegees have emerged in recent years to assist the process with some degree of success. However, something which is often overlooked in terms of stencil design influence is that a square shaped aperture, size for size, has a volume which is 21.5% than its circular counterpart. In a process where quite literally every solder particle that can be printed is becoming significant then this fact can be utilized to the process engineer's advantage. In this paper, the merits of stencil aperture shape, in conjunction with ultrasonic squeegees are investigated with the purpose of developing stencil printing guidelines for ultra-fine pitch components such as 0.3mm pitch CSP's.

We provide an overview of the latest market trends and modern competing methods of sapphire crystal growth and the application of sapphire wafers as LED substrates. Almost all methods of high temperature growth from the melt are suitable for sapphire production, but each of these methods has its advantages and disadvantages depending on the application and required finished product form factor. Special attention is paid to the review of defects and imperfections that allow the engineering of new active devices based on sapphire.

This work presents a multichannel electronic nose system that enables a range of novel applications owing to high sensitivity, low form factor and low power consumption. Each channel is based on a combination of doubly-clamped piezoelectric MEMS resonators and CMOS oscillator-based readout designed in TSMC 0.25 μm technology. Using "application specific" polymer coatings, the individual resonators can be tuned to detect mixtures of volatile organic compounds (VOCs). This system achieves ppm-level theoretical limit of detection for ethanol which paves the way towards a broad range of applications such as personalized health and environment air quality.

ITER project's long time span and the nature of the instrumentation and control (I&C) procurement procedures for the Plant Systems require that the ITER Organization defines and follows well recognized standards which are used both by the industry and in physics experiments. The ITER I&C standards are defined in the Plant Control Design Handbook (PCDH) [1] . The ITER Organization has selected PCI Express and Ethernet for IO intercommunication to be used for plant system instrumentation for fast controllers. The decision on the usage of serialized I/O bus protocols is based on the impressive performance and the commercial availability. The form factors that will be supported by CODAC include PXIe, MicroTCA, and AdvancedTCA platforms. While the PXIe form factor is already well established for instrumentation purposes through the PXI Systems Alliance ( www.pxisa.org ), the AdvancedTCA and MicroTCA platforms which were originally targeted for the telecommunications market ( www.picmg.org ) are currently optimized and specified for instrumentation use through the xTCA extensions for physics [2] . The objective of this study is the evaluation of an integrated ATCA controller design using only commercial components.

EURATOM/CIEMAT and the Technical University of Madrid UPM are involved in the development of a FPSC (fast plant system control) prototype for ITER based on PXIe form factor. The FPSC architecture includes a GPU-based real time high performance computing service which has been integrated under EPICS (experimental physics and industrial control system). In this work we present the design of this service and its performance evaluation with respect to other solutions based in multi-core processors. Plasma pre-processing algorithms, illustrative of the type of tasks that could be required for both control and diagnostics, are used during the performance evaluation.

The introduction of Chip Scale Package (CSP) has become one of the key packaging solutions in the recent semiconductor industry. With the advantages of reducing the package size and stacking capability for higher interconnects, CSP's are continuously evolving into many different types of CSP's packages. One of the key innovative package solutions is the molded wafer level CSP (mWLCSP)1, 2 due to the robust 5 sides or 6 sides protection of the devices with epoxy mold compound (EMC). The advantages of this application include, prevention of chipping and handling damage, sort screening capability due to its form factor at the wafer level, and the enhancement in board level reliability.3 The current singulation method that is the mechanical blade dicing process is encountering many challenges including yield loss, blade lifetime, productivity and its' limitation to achieve a narrow kerf width. We report in this article the unique ASMPT multi beam technology that addresses all the issues of blade dicing and, more importantly, enables a narrow dicing width while maintaining very good yield, reliability, and high productivity.

Additive manufacturing(AM) or 3D printing is one of the fastest growing technologies that has been successfully implemented in various fields. The technique of building components by addition of material rather than the conventional subtractive manufacturing has opened up new realm of product design possibilities. From using AM for prototyping purpose it has evolved to make working parts it started replacing the conventional machines from the production lines. All the engineering disciplines, medical applications, fashion and jewelery designs, hobbyist etc. utilizes 3D printing to build efficient prototypes and products. In this paper, potential application of 3D printing for parts of electrical power converters has been identified and discussed. Surge in the dependence of electromechanical machines had urged to improve the performance of electrical power converters and their form factor. High power density requirements, compactness, rugged environments of usage poses challenges for the converters design. The promising AM technology and their material capabilities could improve the converter design features and assist to meet the requirements. This paper highlights the potential of AM which improved the performance of parts used for thermal management, passive electrical components, PCB construction and other constructional features of the power converters.

We explore how to create interactive systems based on electrical muscle stimulation that offer expressive output. We present muscle-plotter, a system that provides users with input and output access to a computer system while on the go. Using pen-on-paper interaction, muscle-plotter allows users to engage in cognitively demanding activities, such as writing math. Users write formulas using a pen and the system responds by making the users' hand draw charts and widgets. While Anoto technology in the pen tracks users' input, muscle-plotter uses electrical muscle stimulation (EMS) to steer the user's wrist so as to plot charts, fit lines through data points, find data points of interest, or fill in forms. We demonstrate the system at the example of six simple applications, including a wind tunnel simulator.The key idea behind muscle-plotter is to make the user's hand sweep an area on which muscle-plotter renders curves, i.e., series of values, and to persist this EMS output by means of the pen. This allows the system to build up a larger whole. Still, the use of EMS allows muscle-plotter to achieve a compact and mobile form factor. In our user study, muscle-plotter made participants draw random plots with an accuracy of ±4.07 mm and preserved the frequency of functions to be drawn up to 0.3 cycles per cm.

Photonic components have yet to match the power handling, dynamic range, and form factor of RF designs. Comprehensive comparison requires consideration of system-wide performance. Analysis of recent advances in the context of modern electronic warfare system requirements shows photonics-based architectures to be a promising solution.

When developing the SpaceWire based Sirius Data Handling System (DHS) for small satellites AAC Microtec has had to address the dual problem of designing for a low cost and in a small form factor while retaining the high performance, availability and longevity required to support advanced science. In order to achieve the low cost a number of strategies have been applied. Notably, the data handling units are generically designed to be reusable either used for other missions as a part of the platforms they were initially targeted for or for use on other platforms, including CubeSats. Also, COTS components known to withstand the space environment have been used for the designs, in a strategy to reduce component costs. To increase reliability, the Sirius DHS units are designed around a Flash-based FPGA to be tolerant to SEE through triple modular redundancy (TMR) and other fault handling techniques and implements SpaceWire as the main data bus, using nano D-sub connectors to save space and weight. The paper explores in more detail the choices made on the data handling units in order to achieve sufficiently high performance and high reliability in a CubeSat compatible form factor at a reasonable price.

Miniature devices have become wearable beyond the form factor of watches or rings---functional devices can now directly affix to the user's skin, unlocking a much wider canvas for electronics. However, building such small and skin-friendly devices currently requires expensive materials and equipment that is mostly found in the medical domain. We present DuoSkin, a fabrication process that affords rapidly prototyping functional devices directly on the user's skin using gold leaf as the key material, a commodity material that is skin-friendly, robust for everyday wear, and user-friendly in fabrication. We demonstrate how gold leaf enables three types of interaction modalities on DuoSkin devices: sensing touch input, displaying output, and communicating wirelessly with other devices. Importantly, DuoSkin incorporates aesthetic customizations found on body decoration, giving form to exposed interfaces that so far have mostly been concealed by covers. Our technical evaluation confirmed that gold leaf was more durable and preferable when affixed to skin than current commodity materials during everyday wear. This makes gold leaf a viable material for users to build functional and compelling on-skin devices. In our workshop evaluation, participants were able to customize their own on-skin music controllers that reflected personal aesthetics.

In the past decade there have been significant advancements in computer technology that have reduced the hardware form factor as well as increased energy efficient computing. Using network protocols for near field communication such as Body Area Networks (BANs), smaller and lighter computing units with attached sensors have transformed into wearable devices. These devices have served a plethora of purposes including providing assistance to people with disabilities, gathering data, serving as sensors and enhancing human capabilities among other things. Depending on the usage and infrastructure, the devices can be classified into respective domains. In this paper we survey wearable computing devices and classify the same based on the form of assistance that is delivered to the person wearing the device. We also introduce a framework for futuristic devices that can operate in harsh environments.

We are presenting a methodology to optimize the design of a thermally challenging Single Board Computer (SBC) in order to achieve ambitious thermal management goals at reasonable cost. The case study presented describes the design of a conduction cooled SBC in 6U-VPX [1] form factor, dissipating up to 130 W (2 high performance CPUs) and presenting a high density of components (ca 4500 on 640cm2). In order to achieve high reliability (low MTBF), all components must be operated at least 5°C below their maximum rating, while the board's thermal interface, i.e. the upper and lower board edges, are kept at 85°C. Any “active” cooling (including heat pipes) is prohibited. This puts tight constraints on the allowable temperature gradients between the board edges and any of the thermally critical components. It turns out that a heat frame design based on advanced composite materials (aluminium, copper and graphite) can meet these constraints even in the presence of layout constraints that impose a less-than-optimal placement of thermally critical components.

Flexible electronics in mobile environments such as those encountered in wearable devices also require energy sources. Ideally the energy source, typically batteries and supercapacitors, should also be flexible and have the same form factor as the electronic system. This has given rise to a new paradigm of flexible energy storage devices.

The trends for smartphone and other mobile devices are more than ever for integration and lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in these devices. The implications of these market drivers on the packaging content of mobile devices including internet of things (IoT) and wearable electronics (WE) are; higher performance designs, lower power consumption, lower cost, smaller form factor, thinner profile and higher level of integration.

In the context of the Internet of Things (IoT), sound sensing applications are required to run on embedded platforms where notions of product pricing and form factor impose hard constraints on the available computing power. Whereas Automatic Environmental Sound Recognition (AESR) algorithms are most often developed with limited consideration for computational cost, this article seeks which AESR algorithm can make the most of a limited amount of computing power by comparing the sound classification performance em as a function of its computational cost. Results suggest that Deep Neural Networks yield the best ratio of sound classification accuracy across a range of computational costs, while Gaussian Mixture Models offer a reasonable accuracy at a consistently small cost, and Support Vector Machines stand between both in terms of compromise between accuracy and computational cost.