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Abstract: Model surgery is one of the most important steps in the preoperative workup for orthognathic surgery. In cases of complicated two-jaw surgery, manual model surgery requires many laboratory based steps that are time-consuming and may contain potential errors. Recently, a three-dimensional virtual model surgery (3D-VMS) program (3Txer version 2, Orapix, Seoul, Korea) was introduced. The purpose of this article is to present a 3D-VMS case using combined data from 3D computed tomography and 3D virtual dental casts. [Copyright &y& Elsevier]

The present paper proposes a dynamic fuzzy-neural fluctuation smoothing rule to improve the performance of scheduling jobs in a wafer fabrication factory. The rule is modified from the well-known fluctuation smoothing rules with some innovative treatments. First, two non-linear forms of the fluctuation smoothing rule are obtained. To consider two performance measures (the average cycle time and cycle time variation) simultaneously, the two non-linear fluctuation smoothing rules are merged into a bi-criteria rule. Second, to tailor the content of the bi-criteria rule for a specific wafer fabrication factory, a dynamic factor is designed which facilitates the gradual transition between rules. Third, the remaining cycle time of a job to be scheduled is estimated by applying the fuzzy c-means (FCM)-back-propagation network (BPN) approach to improve the estimation accuracy. To evaluate the effectiveness of the proposed methodology, production simulation is also applied in this study. According to experimental results, the proposed methodology outperforms some existing approaches in reducing the average cycle time and cycle time variation at the same time. Moreover, experimental results also reveal that with the dynamic rule it is possible to improve one performance measure without raising the expense of another performance measure. [ABSTRACT FROM AUTHOR]

The semiconductor industry constantly drives for high yield and low cycle time (CT), while most current manufacturing practices consider them separately. This research investigates and exhibits the relationship between CT and yield as affected by in-line metrology inspections of production lots. Among the various factors that impact the tradeoff between CT and yield, we focus on single operation monitors and investigate their measure rate and scheduling. The research assumes a simplified Production Cell consisting of three operation steps that represent a typical segment in a production line. We compose and apply dynamic policies for metrology inspections via simulation and analytical methods. The aim is to concurrently reduce the CT accumulated and increase the yield achieved due to inspections. Ten inspection policies are compared under nine different operation scenarios. The results of most of the policies present a concave curve of yield versus CT. The curve illustrates that growing inspection rate increases both yield and CT until the yield reaches a maximum and then starts to decline. The cause for the yield decline is longer delay in corrective feedback to an out-of-control production tool due to longer waiting time for inspection. A cost-benefit CT-yield objective function is defined and demonstrates that the newly composed dynamic inspection policies are superior to the commonly used fixed measure rate policy. Future research could relax part of the simplified Production Cell assumptions in order to consider more realistic model structure and scenarios. [ABSTRACT FROM AUTHOR]

Abstract: The rate of on-time delivery, namely hit rate, is a very significant performance measurement index for semiconductor wafer fabrication. This study proposes an efficient simple constructive heuristic (SCH), called slack multiplied uncompleted ratio (SMUR), for raising the hit rate in wafer fabs. Effectiveness of the proposed SMUR heuristic is verified by conducting simulation experiments based on a well known model from the relevant literature. The results indicate that the proposed SMUR heuristic is a state-of-the-art SCH for the current problem by comparing the obtained results to the best available SCHs in the relevant literature. Since the proposed SMUR heuristic is easy to implement and decreases the computational burden, this study successfully develops a practical approach which will hopefully encourage practitioners to apply it to real world problems. [Copyright &y& Elsevier]

Abstract: Due-date performance is one of the most important production indexes for success utilized by wafer fabrication factories. Traditionally, the industry sets a specific due-date tightness level and a dispatching rule based on the total processing time, the production capacity, pre-defined order release criteria and historical data, to ensure deliveries are made on-time. However, such policies typically do not solve the due-date performance problem at wafer fabrication factories, since the processes are highly complex. This investigation explores the due-date performance problem using the concept of the aggregated time buffer in critical chain project management (CCPM), which was developed by Dr. Goldratt. A simulation model was constructed and the performance of the proposed method is evaluated based on four dispatching rules at a wafer fabrication factory. The findings reveal that applying aggregated time buffer control system improved the overall due-date control, in terms of on-time delivery rate, average tardiness, and variances in average tardiness and lateness. [Copyright &y& Elsevier]

Abstract: Wafer fabrication is a capital-intensive high-tech sector with highly complex manufacturing processes. Therefore, most of the fabs resort to production dispatching as a means to enhancing production efficiency. The commonly seen methods of production dispatching at the present time are devised to meet single performance indicators. Few methods take into account multiple, or even conflicting performance indicators. Therefore, different production control managers adopt different criteria. Also, as performance indicators change with the variances of production lines and actual demands, it is necessary to clarify the rules of varying dispatching methods and their impacts on all the production performance indicators so that it is possible to explore an architecture for multiple-rule or multiple-target production dispatching in order to meet dynamic performance targets. This paper uses analytical network process (ANP) method to construct a dispatching model based on the characteristics of all the production facilities on-site (such as the utilization of bottleneck machines), in order to explore the relationship among various performance indicators and correlation between performance indicators and the dispatching rules. The aim of this paper is to analyze the production dispatching issues of wafer fabs in an effective and systematic approach, so as to provide an on-site dispatching analysis model that takes into consideration production characteristics and indicator adjustments. This paper finds that the most optimal dispatching method for ANP dispatch model is EDD dispatching method, followed by LS dispatching method. FIFO dispatching method yields the worst performance. The ANP dispatching assess model proposed in this paper can surely serves as an analytical architecture for decision makes to evaluate production dispatching models of multiple production indicators in the future. [Copyright &y& Elsevier]

In wafer fabrication processes, batch processing accounts for over 30% of the overall processing time. And it’s a trade-off between machine utilization and wafer waiting time. Therefore, batch machines have become one of the constraint resources during wafer fabrication. How to maintain the utilization and reduce the waiting time are important tasks for production control. Plenty of research in the past several years focused on the dispatching rules of batch processing. According to many researchers, look-ahead batch dispatching rules outperform MBS on waiting times and machine utilization. The look-ahead batching rules that have been developed are DBH, NACH, MCR, and DJAH. However, these rules do not take the due-date information of wafers into consideration, and can’t accelerate the wafer’s fabrication that will not be completed before the due-date. This study will develop a due-date oriented look-ahead batching rule, namely LBCR, that considers the due-date and expects to raise delivery rates and reduce the average tardiness. Firstly, this study will modify those batching rules to fit the manufacturing environment of wafer fabrication. There are serial simulation tests on those batching rules under various kinds of factors in terms of environment, including traffic intensity, product numbers and product mix rate. Finally, this study will compare the five batching rules on different performance indicators. After the simulation and statistic analysis undertaken, LBCR does outperform other batch dispatching rules on due-date related performance indicators, such as tardy rate and average tardiness. [ABSTRACT FROM AUTHOR]

Estimating lot flow (cycle) time is a critical task for a wafer fabrication plant (wafer fab). Many recent studies have shown that pre-classifying wafer lots before estimating the flow times is beneficial to estimation accuracy. In this aspect, various classification approaches, e.g. k-means (kM), fuzzy c-means (FCM), and self-organization map (SOM), have been applied. After pre-classification, to estimate the flow times for lots belonging to different categories, different approaches (that are in fact the same approaches but with different parameter settings) are applied. However, these applications of classification approaches considered only the data of wafer lots, but ignored whether the classification approaches combined with the subsequent estimation techniques were suitable for the data. To tackle this problem, instead of trying many possible classification and forecasting approaches to find out the most suitable combination, a FCM and back propagation network (BPN) combination is chosen in the current study. In the proposed methodology, the classification results by FCM will be adjusted with forecasting error fed back from the BPN. In this way, if the FCM-BPN combination is not good enough for the data, then a forecasting error will be generated and fed back to the FCM classifier to adjust the classification results. After some replications, the FCM-BPN combination will become more suitable for the data. To evaluate the effectiveness, production simulation is applied in the present study to generate test data. According to experimental results, the forecasting accuracy of the proposed methodology is significantly better than those of many existing approaches. The effects of adjusting classification results with prediction error are also revealed. [ABSTRACT FROM AUTHOR]

Constructing an effective production control policy is the most important issue in wafer fabrication factories. Most of researches focus on the input regulations of wafer fabrication. Although many of these policies have been proven to be effective for wafer fabrication manufacturing, in practical, there is a need to help operators decide which lots should be pulled in the right time and to develop a systematic way to alleviate the long queues at the bottleneck workstation. The purpose of this study is to construct a photolithography workstation dispatching rule (PADR). This dispatching rule considers several characteristics of wafer fabrication and influential factors. Then utilize the weights and threshold values to design a hierarchical priority rule. A simulation model is also constructed to demonstrate the effect of the PADR dispatching rule. The PADR performs better in throughput, yield rate, and mean cycle time than FIFO (First-In-First-Out) and SPT (Shortest Process Time). [ABSTRACT FROM AUTHOR]

In the semiconductor industry, dynamic changes in demand force companies to change the product mix frequently and periodically. Assigning tight but attainable due dates is a great challenge under the circumstances that the product mix changes periodically. In this paper, we consider the due-date assignment problem for wafer fabrication and present a due-date assignment model to set manufacturing due dates satisfying the target on-time-delivery rate. The contamination model is applied to tackle the effect of that product mix varies periodically. We demonstrate the effectiveness and accuracy of the proposed model by solving a real-world example taken from a wafer fabrication shop floor in an IC manufacturing factory. [ABSTRACT FROM AUTHOR]

Commercial hard-drive products utilizing perpendicular magnetic recording technology have recently been announced and introduced. In this paper, we review key magnetic materials characteristics and wafer process attributes in fabricating perpendicular write heads. It becomes increasingly important for write-head materials to possess not only high magnetic moment, but also optimal coercivity, remanence, anisotropy Hk, magnetostriction, and stress in order to meet head performance and reliability requirements. Advanced materials and film architectures discussed in this paper resulted in a significantly improved performance margin, including reduced pole erasure; hence enabling higher recording densities. Novel wafer-processing techniques are required for fabrication of 3-D pole features with controlled shape, and with critical dimensions of less than 150 nm. The advance in wafer process has been driven by rapidly decreasing trackwidth, as well as by the evolving head architecture from unshielded rectangular pole to shielded trapezoidal pole. [ABSTRACT FROM AUTHOR]

Commercial hard-drive products utilizing perpendicular magnetic recording technology have recently been announced and introduced. In this paper, we review key magnetic materials characteristics and wafer process attributes in fabricating perpendicular write heads. It becomes increasingly important for write-head materials to possess not only high magnetic moment, but also optimal coercivity, remanence, anisotropy Hk, magnetostriction, and stress in order to meet head performance and reliability requirements. Advanced materials and film architectures discussed in this paper resulted in a significantly improved performance margin, including reduced pole erasure; hence enabling higher recording densities. Novel wafer-processing techniques are required for fabrication of 3-D pole features with controlled shape, and with critical dimensions of less than 150 nm. The advance in wafer process has been driven by rapidly decreasing trackwidth, as well as by the evolving head architecture from unshielded rectangular pole to shielded trapezoidal pole. [ABSTRACT FROM AUTHOR]

In the semiconductor industry, dynamic changes in demand force companies changing the product mix makes the production planning challenging. This paper aims at an environment where product mix changes periodically and presents a production scheduling system to plan the wafer lot release and throughput. The proposed system is designed on the make-to-stock basis with the objective of meeting demand forecast while maintaining production smoothness. Two modules are included in the system. Preliminary analysis module analyzes throughput and cycle time distributions for different product mixes so as to determine relative parameters to be used as the inputs to the job releasing plan. In the production scheduling module, with the considerations of the attainment of demand forecast, production smoothness, and commitment of the due dates of the released job orders, the job release schedule and completion time table are prepared. A simulation model of a semiconductor fab is used as the base case to demonstrate the effectiveness and efficiency of the proposed system. [ABSTRACT FROM AUTHOR]

As semiconductor process technology progresses, a more rigid process requirement emerges. Process window, also known as process capability, means that a wafer needs to be processed on the machines that can satisfy its process specification. Machine dedication, means that after the first critical layer of a wafer lot is processed on a certain machine, the subsequent critical layers of this lot must be processed on the same machine, to ensure final products of a good quality. The interaction of the two characteristics makes the production plan, based on the overall capacity of workstations, very hard to implement in the real production environment. This paper, therefore, proposes an integer programming model to solve the capacity allocation problem. With the objective of load levelling, the proposed model will assign the load of each layer, of each order, to each machine, with considerations of process window and machine dedication constraints. The model can be used in practice, and the loading allocation results can be a reference for controlling load levelling and setting the release time, in a fab. [ABSTRACT FROM AUTHOR]

We describe a simulation study of a production planning model for multistage production inventory systems that reflects the nonlinear relationship between resource utilization and lead time. The model is based on the use of clearing functions that capture the nonlinear relationship between workload and throughput. We show how these clearing functions can be estimated from empirical data using a simulation model as a surrogate for observation of the production system under study. We then examine the sensitivity of the estimated clearing function to different dispatching algorithms, different demand patterns, and production planning techniques. Computational experiments based on a scaled-down model of a semiconductor wafer fabrication facility illustrate the potential benefits of the clearing function model relative to conventional linear programming models. [ABSTRACT FROM AUTHOR]

High accuracy radio-frequency (RF) measurements typically require a calibration to remove the undesired effects of the measurement apparatus. The calibration consists of measuring some combination of known standards such as short, open, load, through, and delay. When measurements are performed on-wafer for silicon RF integrated circuits (RFICs), a two-step calibration/de-embedding technique is typically used. First, the measurement system is calibrated to a reference plane located at the probe tips through measurement of calibration standards fabricated on an impedance-standard substrate. Second, on-wafer de-embedding standards are measured in an attempt to shift the reference plane to the terminals of the device under test (DUT). While significant effort has gone into the development of improved on-wafer de-embedding schemes, discrepancies between actual and de-embedded data still exist. In this article, we first discuss a specific case (a spiral inductor on silicon) for which there was a significant discrepancy between measurement and analysis. The problem is found to be with the measurement. This problem is detailed, and a technique we call "synthetic calibration" is described that can be used with any electromagnetic (EM) analysis to quantify calibration error for any proposed set of calibration standards. Due to the high expense and time required for wafer fabrication, it is important to successfully complete such a calibration validation prior to tape-out. [ABSTRACT FROM PUBLISHER]

The standard unit of transfer in new semiconductor wafer fabrication facilities is the front opening unified pod (FOUP). Due to automated material handling system concerns, the number of FOUPs in a wafer fab is kept limited. Moreover, a certain number of new and larger 300-mm wafers will be placed in these FOUPs and this makes grouping orders from multiple customers into a job a necessity. Thereby, efficient utilization of the FOUP capacity while attaining good system performance is a challenge. We previously investigated optimization-based solution approaches for minimizing total weighted completion time and maximizing on-time delivery performance for the single machine multiple orders per job scheduling problem. We present two metaheuristic solution approaches for this scheduling problem under two different typical wafer fab machine environments: single unit processing and single lot processing. Experimental results demonstrate that the metaheuristic approaches can find near-optimal solutions for realistic-sized 300-mm scheduling problems in an acceptable amount of computation time. [ABSTRACT FROM AUTHOR]

Due-date assignment (DDA) is the first important task of shop floor control in wafer fabrication. Due-date related performance is impacted by the quality of the DDA rules. Assigning order due dates and timely delivering the goods to the customer will enhance customer service and competitive advantage. A new methodology for lead-time prediction, artificial neural network (ANN) prediction is considered in this work. An ANN-based DDA rule combined with simulation technology and statistical analysis is developed. Besides, regression-based DDA rules for wafer fabrication are modelled as benchmarking. Whether neural networks can outperform conventional and regression-based DDA rules taken from the literature is examined. From the simulation and statistical results, ANN-based DDA rules perform a better job in due-date prediction. ANN-based DDA rules have a lower tardiness rate than the other rules. ANN-based DDA rules have better sensitivity and variance than the other rules. Therefore, if the wafer fab information is not difficult to obtain, the ANN-based DDA rule can perform better due-date prediction. The SFM_sep and JIQ in regression-based and conventional rules are better than the others. [ABSTRACT FROM AUTHOR]

Wet-etching is a key step in wafer fabrication. A wet-etch station is a chemical batch process involving a complex interplay of mixed intermediate storage (MIS) policies and a shared robot for wafer transfers. Its operation poses a challenging resource-constrained scheduling problem that is crucial for enhancing productivity, improving yield and minimizing contamination. In this paper, we develop three new algorithms for scheduling wafer jobs for a given sequence, which comfortably outperform a literature algorithm in terms of solution quality without requiring excessive effort. Furthermore, we propose a simulated annealing (SA) algorithm for sequencing the wafer jobs. Using this SA algorithm, an existing sequencing algorithm based on tabu search (TS), two job-scheduling algorithms and two algorithms for initial job sequence, we identify eight complete algorithms for scheduling operations in an automated wet-etch station (AWS). After a thorough numerical evaluation, we conclude that the TS sequencing strategy combined with two of our three job-scheduling algorithms is the best option that yields up to 25–30% lower makespans than a literature algorithm, and requires acceptable computing times for industrial-scale problems. [Copyright &y& Elsevier]

Energy-dispersive x-ray microanalysis (EDX) techniques have been widely used for elemental analysis of thin film layers in wafer fabrication. However, during EDX analysis of thin film samples, sometimes it is difficult for us to identify elemental information of the surface layer from the underneath layers. Therefore, it is necessary for us to estimate the electron beam accelerating voltage used, and the penetration depth of the electron beam under this accelerating voltage before performing EDX analysis. In this particle, we will introduce a simple method/formula (Vi = kEi, where the value of k is a constant, the unit of Vi is in kV, and Ei is in keV) to estimate the electron beam accelerating voltage, which should be used for determining the element of interest, and discuss the penetration depth of the electron beam under different beam accelerating voltages. The actual beam accelerating voltage used for a characteristic x-ray line in EDX should be more than the theoretical value. In general, it is about 1.5–2.0 times that of the theoretical critical excitation energy. In this study, we have determined the over-voltages of the characterization x-ray lines of Al Ka, Si Ka, Ti Ka, W Ma, and W La, using TiN and TiW thin films and microchip Al bondpad (with Al/TiW/Ti metallization) samples. We have determined an experimental value of the over-voltage constant, k, which was about 1.42, and it is near to the low side of 1.5–2.0 times. Moreover, we will also discuss an application case in failure analysis of wafer fabrication on nonstick bondpads. [ABSTRACT FROM AUTHOR]

The complex process and high variation in wafer fabrication make its production management very difficult. Problems such as planned target achievement and line balancing are not unusual in the industry. Such problems reveal the importance of developing a daily production policy for wafer fabrication. Planned target achievement and line balancing are the major concerns of this investigation in developing a daily production model. This investigation divides the process of wafer fabrication into two sections, i.e., the front and the rear, according to the last sputtering operation step. In the rear section, the objective is attaining the planned output target. In the front section, the major focus is to satisfy the demand of the rear section so that the production line is balanced. Release and dispatch policies are incorporated in this study to achieve both objectives. A real-world numerical example is used as simulation data. Results show that the proposed daily production model gives a better performance in the achievement of monthly planned output but suffers a little in the performance of line balancing. [ABSTRACT FROM AUTHOR]

In this paper, a non-destructive nano-precision measurement method for diamond tool cutting edge radius is presented. The basis of the method is that the profile of a tool cutting edge can be copied by indenting the tool cutting edge into the surface of a selected material, and that the copy of the profile can be measured at nano-precision level using AFM. The selected material elastic error compensation coefficient has to be determined to cancel out the effect of elastic spring-back. Copper was selected as the indentation piece material due to its (1) high rigidity and high density, (2) large Young’s modulus and (3) low yield strength. The elastic error compensation coefficient for the copper material is determined through the indentation of a tungsten carbide tool edge on the copper surface. By comparing the actual tool edge radius measured using scanning electron microscope (SEM) on the sectional view of the tungsten carbide tool with the one measured from the copied profile of the tool edge on the copper surface, the coefficient is obtained. Three diamond tool edge radii were obtained using the proposed method. Analysis is given for the accuracy of the proposed method, showing that as far as the error elastic compensation coefficient is consistent with the copper material used, the only source of errors with the measurement will come from the device for measuring the indented profile on the surface. [Copyright &y& Elsevier]

The semiconductor manufacturing industry is one of the most important industries in Taiwan. Wafer fabrication is an essential process in semiconductor manufacturing. However, controlling the production system on the shop floor is extremely difficult owing to the complicated manufacturing process and reentrant characteristics. In this paper, the shop floor control (SFC) integration strategies (order review/release, dispatching, and rework strategies) in wafer fabrication are considered with using several performances. We reviewed the literature on SFC strategies in wafer fabrication. The proposed combination simulation and simulated annealing (SA) algorithm is presented for SFC strategies in wafer fabrication. The objective was to seek the near global optimum solution for the combination of SFC strategies for a specific performance indicator. From the results, the proposed methodology was found to perform well for combinations of SFC strategies using different performance indicators in wafer fabrication. However, no single combination of SFC strategies could satisfy all performance indicators. Hence, considering the trade-off among these production control strategies, a suitable strategy should be chosen based on the system control tactics. Considerable computational time was saved in this research. [ABSTRACT FROM AUTHOR]

Wafer fabrication industries encounter challenging tasks to justify their performance among conflicting measures when making dispatch policy decisions. A state-dependent dispatch rule is developed to improve overall system performance, which consists of cycle time, work in process, throughput and due date performance. The theory of constraints is adopted as guiding principle to derive the state-dependent dispatch rule. Three state variables (machine utilization, machine queue length, and contention factor) and three dispatch rules (two boundary, shortest time to next visit, and fastest time for next visit) are considered to construct the dispatch rule. Response surface methodology is also applied to this study. A near-realworld fab model is developed to test the performance of the new rule. The simulation results show that the TOC-based state dependent dispatch rule improves four performance measures simultaneously. [ABSTRACT FROM AUTHOR]

The crosstalk performance of an arrayed-waveguide grating (AWG) multiplexer or demultiplexer is primarily caused by random optical phase errors introduced in the arrayed waveguides. Because the layout of waveguides on a wafer is patterned via photomask through the photolithography process, the resolution of a photomask has a direct influence on the phase errors of an AWG. The paper presents a theoretical analysis on the phase error caused by photomask resolution and other basic design parameters. Both calculation and measurement results show that a high-resolution photomask (better than 25 nm) is a critical requirement to produce low-crosstalk (less than -30 dB) AWG demultiplexers. We also investigate the effect of nonideal power distribution in the arrayed waveguides because it contributes considerable phase errors when material impurity is not well controlled during wafer fabrication. Basic criteria of power profile truncation, number of grating waveguides, and material index variation are also summarized [ABSTRACT FROM PUBLISHER]