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The American Heart Association (AHA) has advocated that women and men not consume more than 100 and 150 kcal/day, respectively, from added sugars. These levels are currently exceeded by over 90% of the adult population in the United States. Few data exist on longer-term metabolic effects when sucrose and High Fructose Corn Syrup (HFCS), the principal sources of added dietary sugars, are consumed at levels typical of the general population. Sixty five overweight and obese individuals were placed on a eucaloric (weight stable) diet for 10-weeks, which incorporated sucrose- or HFCS-sweetened, low-fat milk at 10% or 20% of calories in a randomized, double-blinded study. All groups responded similarly (interaction p > 0.05). There was no change in body weight in any of the groups over the 10-week study, or in systolic or diastolic blood pressure. Likewise, there were no changes in total cholesterol, triglycerides, low-density lipoprotein (LDL), or apolipoprotein B (Apo B). We conclude that (1) when consumed as part of a eucaloric diet fructose—when given with glucose (as normally consumed) does not promote weight gain or an atherogenic lipid profile even when consumed at two to four times the level recently recommended by the AHA. (2) There were no differences between HFCS and sucrose on these parameters.

Based on the carrier distribution in three-dimensional semi-classical and twodimensional quantum mechanical cases, the concept of surface layer effective density-of-states (SLEDOS) is proposed. Then a simplified method of calculating the band bending and subband energies is employed to investigate quantum mechanical effects (QMEs) in MOS structure inversion layer. The method is unique compared with published methods in its reversed nature of the iteration procedure. It has high efficiency and good convergence characteristics and gives satisfactorily coincident results with rigorous but more complicated selfconsistent calculations. The method is applicable in both quantum mechanical and semi-classical cases. The subband occupation of inversion layer carrier and the two-dimensional density-of-states in semi-classical and quantum mechanical cases are then calculated. QMEs on inversion layer carrier density and surface potential are analysed on the basis of the method. Gate capacitance in the MOS structure in...

A new analytical charge model in quantized inversion layer in MOS structure is developed by comprehensively considering the quantum mechanical effects. The model is based on the newly proposed concept of space charge capacitance. Explicit expressions of surface potential and inversion layer carrier density are given which have smooth transition characteristics from depletion to weak to strong inversion regions. Threshold voltage shift, finite inversion layer thickness and the increment of depletion charge after strong inversion are properly modeled. Model results are compared with numerical data by self-consistent solution of Schrodinger and Poisson equation and the high accuracy of the model is demonstrated.

A rigorous model for metal-insulator-semiconductor (MIS) interconnects is presented based on device level simulation results. At the device level, the motion equations of charged carriers and Maxwell's equations are simultaneously solved using a finite element scheme and Newton's method. Simulations provide detailed information regarding field-carrier interactions, semiconductor substrate loss and nonlinearity, as well as the slow-wave effect, external bias effect, and screening effect of the charged carriers. An equivalent circuit model of MIS interconnects is established using an energy-based approach. The model consists of an equivalent transmission line that mimics the energy transport characteristics of the actual MIS interconnect, and provides a generalized nonlinear and electronic tunable circuit model suitable for both small-signal and large-signal analysis. Examples are presented to illustrate capabilities and efficiency of the method as well as properties of the equivalent circuit model.

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm/spl les/t/sub ox/spl les//1.5 nm, L/sub g/=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V/sub dd/ static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices.

Threshold voltage shift due to quantum mechanical effects (QMEs) are studied for both n- and p-MOS structure in the paper. Subband structure and carrier distribution are formulated for both type of MOS structure in effective mass approximation. QMEs on threshold voltage shift are thoroughly analyzed based on the model. Carrier distribution in subbands for both n-MOS and p-MOS are calculated and analyzed from density-of-states point of view. Model results for n- and p-MOS structure are compared with experimental and full-band self-consistent calculation results and show good coincidence. It is proved that at least in threshold region, effective mass approximation has similar accuracy as the full-band self-consistent method to predict the influence of QMEs MOS structure characteristics.

Degree of degeneracy of quantized inversion layer in metal-oxide semiconductor structure are investigated by a fully quantum mechanical approach via self-consistent solution of Schrodinger and Poisson equations. The relative error of carrier sheet density induced by Boltzmann statistics is used as a measurement of the degeneracy. It is shown that the degree of degeneracy of inversion layer is much weaker due to the quantization of carrier energy compared with the semi-classical one.

Based on the analysis of the distribution of inversion layer carriers in MOS structure, the concept of surface layer effective density-of-states (SLEDOS) is proposed. Then a new charge control model suitable for both semi-classical and quantum mechanical theory is established in which the effects of inversion layer carrier distribution on surface potential are included. In this model, a newly developed efficient iteration method is introduced, which has high efficiency and satisfied stability. Based on the model, the effects of quantum mechanical effects (QMEs) on inversion layer charge density both in weak and strong inversion regions and the surface potential are studied. Model results are compared with the self-consistent solutions of Schrodinger and Poisson equations, which proves the high accuracy of the new model.

The threshold voltage shift due to quantum mechanical effects (QMEs) has substantial influences on modern pMOSFET characteristics. Investigations of QMEs in a pMOSFET are classified into two approaches: full-band calculation and effective mass approximation. In this paper, formulation of carrier distribution in the pMOSFET inversion layer in the threshold region based on the effective mass approximation is presented, and a new method to calculate the threshold voltage shift due to QMEs is developed. The results with the effective mass approximation are compared with the full-band calculation and show satisfactory coincidence. Based on the present model, the subband structure of the hole inversion layer and the carrier distribution characteristics are investigated. The quantum mechanical and semi-classical two-dimensional density of states (2D DOS) are calculated and compared. The dependence of the threshold voltage shift due to QMEs on substrate doping concentration is then analyzed from the DOS point of view.

This paper describes how device simulation may be used for the modeling, analysis, and design of radio-frequency (RF) laterally diffused metal-oxide-semiconductor (LDMOS) transistors. Improvements to device analysis needed to meet the requirements of RF devices are discussed. Key modeling regions of the LDMOS device are explored and important physical effects are characterized. The LDMOS model is compared to dc and small-signal ac measurements for calibration purposes. Using the calibrated model, large-signal accuracy is verified using harmonic distortion simulation, and intermodulation analysis. Predictive analysis and a study of the structure's parasitic components are also presented. Load-pull simulation is used to analyze matching network effects to determine the best choices for device impedance matching.

MOS structure threshold voltage shift due to quantum mechanical effects (QMEs) has a substantial influence on deep-submicron MOSFET characteristics. However, its physical nature has not been thoroughly investigated and an analytical model is absent. In this paper, a numerical solution of the Schrodinger equation with parabolic potential well and an analytical solution with triangular well are compared, and the validity of the triangular well approximation is verified. Based on the calculation of the subband structure in the quantized region in a weak inversion regime, the concepts of surface layer effective density-of-states (SLEDOS) is proposed. Carrier distribution in subbands is then analyzed and physical base of MOSFETs Vth shift due to QMEs are discussed. The single subband occupation approximation used in earlier works is proved to be invalid and a new analytical threshold voltage (Vth) shift model due to QMEs including multisubband occupation is derived based on the concept of SLEDOS. The model reveals the physical nature of QMEs on Vth shift and gives consistent results with experiments and self-consistent calculation.

Accurate external resistance extraction for shallow source/drain extension (SDE) MOSFET's is demonstrated using a unified mobility model for inversion and accumulation layers. The parasitic resistance in the accumulation layer (R/sub acc/) is highly dependent both on the SDE junction depth (X/sub j/) and the gate overlap length (L/sub ou/). Due to the laterally finite doping gradient, R/sub acc/ becomes dominant among other external resistance components in sub-0.1 /spl mu/m MOSFETs. Hence, device optimization to minimize R/sub acc/ is necessary in order to improve on-current and SDE to the gate coupling. A NMOS transistor with L/sub eff/ of 0.08 /spl mu/m shows a maximum on-current while maintaining a lower off-leakage current for a L/sub ou/ of 20 nm and X/sub j/ of 40 nm.

Two critical aspects of the MOS scaling towards sub-100 nm gate length are addressed: the gate tunneling and capacitance modeling, and optimization of shallow source/drain (S/D) extension junction to minimize the series resistance. Both advanced physics (quantum mechanics or QM) and practical solution (circuit simulation) are used to tackle the modeling approach. Good results have been obtained compared to available experimental data, validating the hierarchical methodology used in this paper. A hybrid, semi-analytical QM model for channel carrier profile and an accurate direct tunneling model have been developed. An nMOS transistor with effective channel length of 0.08 micron has been analyzed to demonstrate the methodology proposed.

The density-gradient description of quantum transport is applied to the analysis of tunneling phenomena in ultrathin (

A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC network is used to accommodate the distributed nature of MOSFETs and an optimization technique is applied to extract the intrinsic gate capacitance. Applicability of the method is demonstrated for ultra-thin nitride/oxide (N/O /spl sim/1.4 nm/0.7 nm) composite dielectric MOSFETs.

Two methods are presented to calculate the carrier distribution in MOS inversion and accumulation layer by self-consistent solution of Schrodinger and Poisson equations. One is the fully numerical solution of Schrodinger equation by finite difference method and the other is the analytical solution of Schrodinger equation under triangular potential well approximation. The effective electric field used in the analytical solution is properly determined. Results show that both carrier sheet density and surface potential in inversion layer and accumulation layer can be determined by analytical solution under triangular potential well approximation with sufficiently high accuracy. However, the carrier distribution profile and centroid of mobile charge layer, as well as the behavior at the flat-band region, have a large deviation from the numerical results.

Harmonic balance is a popular technique for simulating large-signal harmonic and intermodulation distortion in RF and microwave circuits. In this paper, we present algorithms which extend the applicability of harmonic balance to physics-based semiconductor device analysis. The algorithms presented here have been implemented in the PISCES-II device simulator, and have been used to simulate a wide variety of RF and microwave transistors embedded in realistic circuit networks containing biasing and parasitic elements. The simulator employs Krylov subspace solution techniques to solve the extremely large systems of equations arising in the context of two-dimensional device simulation. In the important case of multi-tone distortion problems, the size and density of the device Jacobian necessitate the introduction of novel preconditioning techniques (dubbed sectioned preconditioning) which exploit the special structure of the device simulation problem.

Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters (/spl gamma/, /spl delta/, and c) for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data.

The virtual-cathode approach to modeling short-channel effects in deep-nanoscaled MOSFETs (with gate length of less than 25 nm) is increasingly viewed as a vital means in MOS compact modeling. To achieve analytical solution to the 2-D Poisson's equation, the voltage-doping transformation is adopted to map 2-D electrostatics, including drain-induced barrier lowering, into an equivalent 1-D form at the point of virtual cathode. To accommodate both full-depletion and partial-depletion operation modes, contributions to space charge from electrons and holes are all considered. Models for subthreshold swing and threshold-voltage rolloff are further developed, and the accuracy of the overall model is verified through numerical device simulation.

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

A fully self-consistent 3-D device simulator which combines nonequilibrium Green's function and atomistic tight-binding Hamiltonian for carrier transport is developed to characterize the performance of double-gate carbon nanoribbon (CNR) MOSFETs. Our simulation indicates a strong dependence of device performance on ribbon width and a conventional dependence on channel length. A novel tapered-channel geometry is proposed to counter these effects caused by inevitable process variation. An intuitive explanation is provided for this design approach, followed by detailed numerical simulation results. It is concluded that quantum-based atomistic device simulators provide both - characteristics and internal physical properties of CNR MOSFETs, thus playing a critical role in the design and optimization of nanoscale devices.

A physical model for hole mobility under either biaxial or uniaxial stress has been developed. The six-band k ⋅ p theory is used to obtain the bandstructure through stress-dependent Hamiltonian. The hole mobility in the silicon inversion layer is studied in details using Monte Carlo method. A numerically robust method has been applied to achieve self-consistent solution of Poisson’s and Schrodinger equations.

The contact resistance (R(c)) between graphene and metal electrodes is of crucial importance for achieving potentially high performances for graphene devices. However, previous analytical models based on Landauer's approach have failed to include the Fermi velocity difference between the graphene under the metal and the pure graphene channel. Hereby we report a theoretical model to estimate the R(c) using density-functional theory and non-equilibrium Green's function methods. Our model not only presents a clear physical picture of the metal-graphene contacts, but also generates R(c) values which are in good agreement with the experimental results: 210 Ω μm for double-sided Pd contacts compared with 403 Ω μm for single-sided Pd contact.

A unified model is developed for the first time to explain the metallic filament growth from either anode or cathode for conductive-bridge random access memory (CBRAM). Both electrochemical reactions and ion/electron transport are considered. Simulation results reveal that diffusion coefficient and mobility of cations in the electrolyte are responsible for determining the growth direction of the conductive metallic-filament. The simulation results for the forming process of CBRAM are compared to experimental data and good agreement is achieved.

Analytical solutions (i.e., compact model) to differential equations governing the surface movement of conductive filament (CF) in CBRAM have been developed. Time needed for forming and switching of memory cell can readily be evaluated based on the device structure and the applied bias. The accuracy of the model has been verified by comparison to both experimental and numerical simulation results for Ag-GeS2-W CBRAM cells.

Metal (M) /grapheme (Gr) contact has attracted much attention since the contact resistance (Rc) between Gr and metal electrode is crucially important for achieving high performance of grapheme-based devices [[1]-[15]]. Published experimental works on metal/graphene contacts generally adopted Gr/Ti/Metal structure to enhance the interfacial adhesion [[1]-[8]]. However, how the presence of Ti wetting layer can influence the global response of Gr-based device remains unclear. To present a clear physical understanding and optimizing transport between metal electrodes and graphene with Ti wetting layer, the binding energy, band structure, interface potential profile and contact resistance of the Gr/Ti/Metal (Al, Cu, Au, Pt, Pd) systems were studied for the first time by first-principle and NEGF methods in this paper. The results provide insights into contact resistance optimization and the ultimate scalability of graphene-based devices.

We present in this paper a basic compact model incorporating several key physical mechanisms in nanowire tunneling field-effect transistors (NW-tFETs), such as non-constant subthreshold swing (SS), definition of an on voltage, ballistic transport for carriers in the channel, and quantum capacitance limit (QCL). Using experimental data from [1], the validity of this model is verified. Further, to project the performance of ultra-scaled silicon NW-tFETs, we compare the state-of-the-art gate-all-around (GAA) NW MOSFETs [2] with modeling results for the same NW diameter and EOT (effective oxide thickness). It is concluded that ultra-scaled NW-tFETs can achieve high performance with low subthreshold swing (SS) and nearly the same on current as in MOSFETs.

In this paper, a wide-band inductor-less LNA for low voltage operation is presented. The input matching is implemented by using a feedback transistor with a resistor terminated to the source to enhance linearity and to reduce noise. Current reuse technique is employed to increase the total transconductance. Under 1V supply voltage and a DC of 5.6 mA, the LNA achieves an average noise figure of 3.2 dB, a maximum voltage gain of 18.6 dB, and 3 dB bandwidth ranges from 0.2-4.5 GHz.

Intake of high-fructose corn syrup (HFCS) has been suggested to contribute to the increased prevalence of obesity, whereas a number of studies and organizations have reported metabolic equivalence between HFCS and sucrose. We hypothesized that HFCS and sucrose would have similar effects on energy-regulating hormones and metabolic substrates at normal levels of human consumption and that these values would not change over a 10-week, free-living period at these consumption levels. This was a randomized, prospective, double-blind, parallel group study in which 138 adult men and women consumed 10 weeks of low-fat milk sweetened with either HFCS or sucrose at levels of the 25th, 50th, and 90th percentile population consumption of fructose (the equivalent of 40, 90, or 150 g of sugar per day in a 2000-kcal diet). Before and after the 10-week intervention, 24-hour blood samples were collected. The area under the curve (AUC) for glucose, insulin, leptin, active ghrelin, triglyceride, and uric acid was measured. There were no group differences at baseline or posttesting for all outcomes (interaction, P > .05). The AUC response of glucose, active ghrelin, and uric acid did not change between baseline and posttesting (P > .05), whereas the AUC response of insulin (P < .05), leptin (P < .001), and triglyceride (P < .01) increased over the course of the intervention when the 6 groups were averaged.We conclude that there are no differences in the metabolic effects of HFCS and sucrose when compared at low, medium, and high levels of consumption.

Weight loss improves cardiovascular disease (CVD) risk profile, and strong evidence demonstrates that consuming smaller portions leads to weight loss. When prepared portion-controlled meals are compared to conventional meals as part of an overall weight-loss diet, results of clinical trials of up to one year in duration show greater and more sustained weight loss in those participants who consumed prepared single-serving meals. However, little is known about the effect of replacing just one conventional meal per day with a portion-controlled single-serving meal and no other dietary intervention. We assessed the hypothesis that replacing a typical cafeteria or restaurant hot lunch with a commercially available, frozen, single-serving meal would result in improved cardiovascular profiles. Thirty-five otherwise healthy overweight and obese participants (mean BMI 31.4 ± 3.1) ages 20-55 years were recruited from the community. They consumed and recorded, via duplicate plate method, their usual cafeteria or restaurant lunch for three days. For 30 days thereafter, participants replaced their typical lunches with commercially prepared single-serving meals (Healthy Choice®). They were asked to otherwise maintain their usual eating and exercise habits. Body weight, blood pressure, total cholesterol and LDL-cholesterol were measured at baseline and after completion of the 30-day intervention. In conjunction with weight loss (200.5 ± 32.0 lb. at baseline vs. 197.7 ± 31.1 lb. post intervention, p < 0.01), reductions in systolic and diastolic blood pressure (113.8 ± 12.8 vs. 109.3 ± 10.9 mmHg systolic, p < 0.05, and 76.0 ± 8.7 vs. 74.6 ± 8.0 mmHg diastolic, NS), serum total cholesterol (188.9 ± 29.1 vs. 176.1 ± 25.6 mg/dl, p < 0.01), and LDL-cholesterol (115.5 ± 26.7 vs. 108.8 ± 22.9 mg/dl, p < 0.001) resulted. These preliminary findings from a short-term study support the conclusion that consuming frozen single-serving meals at lunch provides a potential strategy for overweight and obese adults to reduce body weight, systolic blood pressure and LDL-cholesterol, primary risk factors for CVD.

Purpose: Evaluate the effect of addition of commonly consumed fructose containing sugars to the usual diet on liver fat content. Background: Fructose induced triglyceride synthesis has been argued to be augmented when accompanied by glucose. As the most common sources of fructose, high fructose corn syrup HFCS) and sucrose, also contain glucose such a response would be particularly detrimental to metabolic health due to the known role of excess fat in the liver in the induction of abnormalities in glucose homeostasis, insulin resistance and the subsequent development of type II diabetes. Methods: For ten weeks, sixty-eight individuals (42.16 ± 11.66 years) consumed low-fat milk sweetened with either HFCS or sucrose such that the added sugar matched the 25th, 50th and 90th percentile population consumption levels of fructose. Fat content of the liver was obtained before and after the ten week intervention. Imaging was performed on a Philips 64-slice CT scanner. Region of interest measurements in the four sectors of the liver delineated by the hepatic veins were obtained in all patients, and converted to hepatocellular fat content percentages. Fat content of the liver remained unchanged (13.32 ±10.49 vs 13.32 ± 10.75%, p > 0.05). Group assignment did not affect the result interaction p > 0.05). Conclusions: These data suggest that ectopic fat storage in the liver is not promoted when fructose is consumed as part of a normal diet, even in amounts as high as the 90th percentile consumption level.

The density-gradient approach to quantum transport theory is used to model the inversion layer profiles, threshold voltages and C-V characteristics of MOS capacitors with ultra-thin oxides and polysilicon gates. The results (without fitting parameters) are found to compare quite well with experimental data and with calculations made using quantum mechanics. Comparisons are also made with results obtained using previous phenomenological methods and these favor density-gradient theory as well, especially in its being physically meaningful and predictive. Overall, the results of this work show that density-gradient theory provides a physics-based approach to device modeling problems in which quantum confinement effects are significant that is simple enough for engineering applications.

Noise exposure at low levels or low doses can damage hair cell afferent ribbon synapses without causing permanent threshold shifts. In contrast to reports in the mouse cochleae, initial damage to ribbon synapses in the cochleae of guinea pigs is largely repairable. In the present study, we further investigated the repair process in ribbon synapses in guinea pigs after similar noise exposure. In the control samples, a small portion of afferent synapses lacked synaptic ribbons, suggesting the co-existence of conventional no-ribbon and ribbon synapses. The loss and recovery of hair cell ribbons and post-synaptic densities (PSDs) occurred in parallel, but the recovery was not complete, resulting in a permanent loss of less than 10% synapses. During the repair process, ribbons were temporally separated from the PSDs. A plastic interaction between ribbons and postsynaptic terminals may be involved in the reestablishment of synaptic contact between ribbons and PSDs, as shown by location changes in both structures. Synapse repair was associated with a breakdown in temporal processing, as reflected by poorer responses in the compound action potential (CAP) of auditory nerves to time-stress signals. Thus, deterioration in temporal processing originated from the cochlea. This deterioration developed with the recovery in hearing threshold and ribbon synapse counts, suggesting that the repaired synapses had deficits in temporal processing.

This paper presents an analytical drain current model considering the impact ionization and parasitic BJT effects, an energy balance equation, and lattice thermal effect for short-channel fully-depleted ultrathin silicon-on-insulator NMOS devices. Supported by the experimental data, the analytical model shows a good prediction of the drain current characteristics. According to the model, in the saturation region at small V G , the impact ionization and parasitic BJT effects are important. At large V G , the lattice thermal effect is important.

Evidence of whether nutrition students are free from food-related issues or at higher risk for eating disorders is inconsistent. This study aimed to assess disordered eating behaviors and food addiction among nutrition and non-nutrition major college students. Students (n = 967, ages 18–25, female 72.7%, white 74.8%) enrolled at a public university completed online demographic characteristics surveys and validated questionnaires measuring specific disordered eating behaviors. Academic major category differences were compared. Additionally, high risk participants were assessed by weight status and academic year. Overall, 10% of respondents were a high level of concern for developing eating disorders. About 10.3% of respondents met criteria for food addiction. In addition, 4.5% of respondents had co-occurrence of eating disorder risk and food addiction risk out of total respondents. There were no significant differences in level of concern for developing an eating disorder, eating subscales, or food addiction among academic majors. The percentage of high risk participants was lower in the underweight/normal weight group than in the overweight/obese group in health-related non-nutrition major students but not in nutrition students. Early screening, increasing awareness, and promoting healthy eating habits could be potential strategies to help treat and prevent the development of disorders or associated health conditions in nutrition as well as non-nutrition students.

This paper reports a closed-form analytical drain current model considering both electron and lattice temperatures simultaneously using a quasi-two-dimensional approach for deep submicron ultrathin SOI NMOS devices. As verified by the experimental data, the closed-form analytical model shows a good predication of the negative differential resistance behavior. Based on the analytical model, with a channel length of >

Gate tunneling current in fully depleted, double-gate (DG) silicon-on-insulator (SOI) MOSFETs is characterized based on quantum-mechanical principles. The gate tunneling current for symmetrical DG SOI with ground-plane (t/sub ox/ = 1.5 nm and T/sub SI/ = 5 nm) is shown to be higher relative to single-gate (bulk) MOS structure. The tunneling is enhanced as the silicon layer becomes thinner since the thinner silicon layer acts a deep quantum well. The simulated I/sub G/-V/sub G/ of DG SOI has negative differential resistance like that of the resonant tunnel diodes at the gate bias /spl sim/ 1.4 V.

The distortion behavior for thin oxide MOS transistors can be degraded due to polysilicon-gate depletion effects. The nonlinear, bias-dependent gate capacitance for thin oxide MOSFET's results in significant 2nd-order derivatives in gate capacitance, (/spl part//sup 2/C(V/sub gs/)//spl part/V/sub gs//sup 2/), which in turn results in substantial 3rd-order derivative contributions to drain current, (/spl part//sup 3/I/sub ds///spl part/V/sub gs//sup 3/). This may restrict the use of very-thin oxide MOSFET's in RF applications.

We have simulated the forming process and erase operation of Ag/GeS 2 -based CBRAM in a fully 3D environment using cylindrical coordinates. Through numerical simulations, we demonstrate the combined effect of ion migration and electrochemical reaction on the filament evolution under electric field. Experimental results of forming/erase time vs. applied voltage and electrolyte thickness confirm the accuracy of the model.

A compact model for gate-all-around (GAA) nanowire tunneling FETs (NW-tFETs) is developed based on ballistic transport and charge balancing approaches. To account for the carrier injection to the channel from source/drain (S/D) regions for NW FETs, the density-of-states (DOS) charge, which results in the so-called quantum capacitance, is introduced and augmented to include tunneling phenomenon. A complete large-signal equivalent circuit is proposed for the first time, including the doping effects in S/D regions. Preliminary results from comparison of model prediction and numerical device simulation show the correctness of the modeling methodology.

A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is fabricated in 90-nm CMOS technology. The measurement results show that the PLL achieves a phase noise of −85dBc/Hz in band and −112dBc/Hz at 10-MHz offset from the carrier frequency of 24GHz. The whole chip occupies an area of 1.3 × 0.8mm2 and consumes 36-mW from a 1.2-V supply voltage (a 0.8-V supply voltage for VCO) excluding output driving buffers.

A complementary injection technique is proposed to enhance the overall performance of current mode logic (CML) dividers in this paper. With injection currents introduced by pMOSFETs, the equivalent injection efficiency of CML dividers are improved and thus CML dividers achieve a better performance. Extensive simulation results show that the proposed technique improves the division bandwidth of 24-GHz divide-by-2 CML divider by 5GHz, which is from 12GHz to 30GHz. The designed divide-by-2 CML frequency divider draws only 2-mA current from 1.2-V supply.

A novel injection-locked frequency divider for V-Band frequency synthesis is proposed in this paper. Thanks to the nMOS realized in triple-well technology with N-well floating, the source and its body can be connected together to get rid of the body effect and thus reduce the nMOS threshold voltage, which helps enhance the injection efficiency in the direct injection-locked frequency dividers. The proposed divider is implemented in 90-nm CMOS technology and draws only 1-mA from 0.9-V low voltage supply. The simulation results show that the proposed frequency divider can work from 52-GHz to 65-GHz with 0-dBm input power. The division bandwidth is improved by 5-GHz comparing to the conventional structures.

Background The replacement of sucrose with HFCS in food products has been suggested as playing a role in the development of obesity as a public health issue. The objective of this study was to examine the effects of four equally hypocaloric diets containing different levels of sucrose or high fructose corn syrup (HFCS). Methods This was a randomized, prospective, double blind trial, with overweight/obese participants measured for body composition and blood chemistry before and after the completion of 12 weeks following a hypocaloric diet. The average caloric deficit achieved on the hypocaloric diets was 309 kcal. Results Reductions were observed in all measures of adiposity including body mass, BMI,% body fat, waist circumference and fat mass for all four hypocaloric groups, as well as reductions in the exercise only group for body mass, BMI and waist circumference. Conclusions Similar decreases in weight and indices of adiposity are observed when overweight or obese individuals are fed hypocaloric diets containing levels of sucrose or high fructose corn syrup typically consumed by adults in the United States.

A novel compact model using pole-residue method for ultra-broadband on-chip transformer is presented. This model possesses several paralleled branches for high-order effects of transformers, and it can be easily extracted using the procedure of vector fitting (VF) written in MATLAB. Meanwhile, the key features of the existing equivalent circuit models have been analyzed. The proposed model reaches high accuracy and fits well with 100 GHz measured S-parameters of an on-chip transformer.

Phase noise of oscillators can be improved through noise filtering. This paper presents a transformer-based harmonic filtering technique to improve the phase noise performance of the fully differential CMOS LC oscillators. The primary and secondary of the transformer are placed at the sources of NMOS and PMOS differential pairs, respectively. Due to the extra degree of freedom introduced by the transformer, the filter can resonate at two different frequencies, which are designed to be the second and fourth harmonics. The analysis of the filtering method is presented and principles of operation are discussed in details. The performance is compared with other filtering techniques, and the simulation results show improved FoM compared to published literature.

A compact model for 1:1 stacked transformers fabricated in silicon IC technology has been developed. The skin and substrate effects are taken into account in the model. The model parameters are extracted from the layout and the process technology specifications. The proposed model is verified by measured S-parameters up to 40 GHz. The simulated S-parameters, quality factor Q, coil inductance and magnetic coupling coefficient, all show excellent agreement with measured data over the entire frequency range.

Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs.