565 results on '"Platzner, Marco"'
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252. Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation
253. Compact Buffered Routing Architecture
254. Simultaneous Timing Driven Clustering and Placement for FPGAs
255. Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
256. A Dual-V DD Low Power FPGA Architecture
257. Improving FPGA Performance and Area Using an Adaptive Logic Module
258. Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine
259. Stochastic Simulation for Biochemical Reactions on FPGA
260. Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures
261. Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer
262. Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs
263. Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes
264. FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines
265. Power Analysis Attacks Against FPGA Implementations of the DES
266. Flow Monitoring in High-Speed Networks with 2D Hash Tables
267. AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits
268. Processing Repetitive Sequence Structures with Mismatches at Streaming Rate
269. FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation
270. Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion
271. FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
272. Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory
273. The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead
274. Secure Logic Synthesis
275. Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems
276. A Structured Methodology for System-on-an-FPGA Design
277. A Dynamic NoC Approach for Communication in Reconfigurable Devices
278. Multithreading in a Hyper-programmable Platform for Networked Systems
279. A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses
280. FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T
281. An Environment for Exploring Data-Driven Architectures
282. A Low Power FPAA for Wide Band Applications
283. Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design
284. Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
285. Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic
286. Minimum Sum of Absolute Differences Implementation in a Single FPGA Device
287. High Throughput Serpent Encryption Implementation
288. Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V
289. Implementation of Elliptic Curve Cryptosystems over GF(2) in Optimal Normal Basis on a Reconfigurable Computer
290. Real-Time Computation of the Generalized Hough Transform
291. FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems
292. FPGA Custom DSP for ECG Signal Analysis and Compression
293. A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays
294. Design and Implementation of a CFAR Processor for Target Detection
295. Exploring Potential Benefits of 3D FPGA Integration
296. A Parallel FFT Architecture for FPGAs
297. FPGA-Efficient Hybrid LUT/CORDIC Architecture
298. Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path
299. Deploying Hardware Platforms for SoC Validation: An Industrial Case Study
300. SoftSONIC: A Customisable Modular Platform for Video Applications
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