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Independently-controlled double-gate devices using asymmetrical (n+/p+) gates are applied to the design of a novel VT-controlled voltage controlled oscillator (VCO). The VCO supports high operating frequencies and a wide tuning range. The back gates of the asymmetrical double-gate devices are used to modulate the threshold voltages of the front gate devices. A two-fold frequency tuning range is observed without the complexity of additional devices, resulting in improved performance, noise immunity, and power efficiency over conventional well/body bias techniques. These results are validated through mixed-mode MEDICI simulations

In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when technology features are judiciously utilized in the design of dynamic circuits.

Wide circuit implementation of limited switch dynamic logic (LSDL), a high performance logic circuit, with a modified pseudo-nMOS style load has been studied in this paper. A conventional two levels of 8-way mux implementation and a wide 64-way mux implementation of the 64-bit rotator circuit were used in the analysis. The resultant wide circuit implementation consumes less power, maintains robustness to noise and power rail bounce and reduces the pipeline depth to a single stage. The effect of process variation on circuit performance is evaluated. Based on the analysis, a new circuit style known as hybrid LSDL has been proposed.

In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of the two VDD supplies, thereby lowering static power dissipation. When actively transitioning, the inverters in the bus system are temporarily boosted to the higher VDD supply to provide the needed drive strength for performance. Since the VDD boosting is done in a pulsed manner, the bus system is in a high VDD state only when required, ensuring lower power operation without sacrificing performance. This technique yields up to a 50% reduction in total power over traditional static buses and up to a 35% reduction in total power over standard static pulsed buses, with a 12-15% delay improvement.

"In diesem Aufsatz wird das theoretische Problem fokussiert, inwieweit sich in Marktwirtschaften nachhaltiger Konsum endogen stabilisiert und inwieweit staatliche Regulierungen notwendig sind. Dazu werden ökonomische Nachhaltigkeitsdiskurse skizzierte, spezifische Marktprobleme benannt sowie die endogenen Lösungen, die sich über einen institutionellen Wettbewerb ergeben. Diese Zusammenhänge werden am Beispiel von Fair-Trade-Handelsorganisationen exemplarisch aufgezeigt. Ein wesentliches Ergebnis ist, dass Reputati-on für die Qualität der Güter hinsichtlich Produkteigenschaften und Produktionsbedingungen nicht allein strategischer Maßnahmen der Glaubhaftmachung im spieltheoretischen Sinne bedürfen, sondern dass auch psychologische Selbstbindungsmechanismen wirken. Dies wiederum, so wird argumentiert, erfordert auch eine Revision der üblichen Verhaltensannahmen der Ökonomik bei der Analyse von Nachhaltigkeitsfragen."[Autorenreferat] "This paper focusses on the theoretical problem of the extent to which sustainable consumption is endogeneously stabilised or recourse to state regulation is necessary in market economies. For this purpose economic discourse on sustainability is sketched and specific market problems outlined as well as the endogeneous solutions arising from insitutional competition. These interrelations are demonstrated drawing on the example of fair trade retailers. An important finding is that reputation for quality of goods, in terms of the properties and conditions of the product, is not alone understandable as a strategic measure of credibility in terms of game theory, rather psychological mechanisms of commitment also play a role. It is argued that these, in turn, require a revision of the usual assumptions regarding economic behaviour in the analysis of questions of sustainability."[author´s abstract]

Introduction of sub-90nm technology has made a profound impact on circuit designs. Thus, it requires understanding of existing design styles for desired energy-efficiency. We compare adder designs in the energy-delay space, implemented with Limited Switch Dynamic Logic (LSDL) and Compound Domino Logic (CD) in a 65nm SOI technology. Evaluation results show that LSDL can provide more than 35% energy savings than CD with 25% switching activity at relaxed cycle times greater than 10.5 FO4.

Migration of designs into a smaller technology node, that traditionally resulted in an increase in performance, is yielding reduced returns as we scale into the sub-90 nm domain. This has made it imperative to explore alternative methods like improvements in circuit design to sustain growth in performance of Integrated Circuits. The Limited switching dynamic logic (LSDL) circuit family has been suggested as an efficient and high performance circuit design technique to overcome the problem of stagnating performance. In this paper, we present case studies in design of arithmetic units using LSDL selector circuits. The first unit we present is a shifter, with the added novelty that it can provide the shifted data in complemented or non-complemented form without requiring an additional module for performing the negate operation. The second unit is a permute unit, used to line up data in media units using a single instruction, so that the media unit can operate on the data. However, existing permute units have a severe limitation in that they can move only discrete immutable bytes. Our module overcomes this by enabling extraction of any set of eight consecutive bits in a data stream, thus providing bit-level granularity in the permute operation, without altering the format of the existing permute instruction.

Deviations in leakage and delay due to process variation have increased greatly with technology scaling. This paper presents two adaptive MTCMOS schemes to address the growing leakage and delay spreads found in modem high-performance designs. Variable-gate voltage MTCMOS adjusts the applied gate voltage on footer devices while variable-width MTCMOS adaptively turns on or off footers in a circuit block. Both techniques compensate for the spread in leakage and delay. Our results show a 21%-61% decrease in runtime leakage with a worst-case delay penalty of 9%.

A 32 b PowerPC/spl trade/ system-on-a-chip supporting dynamic voltage supply and dynamic frequency scaling operates from 366 MHz at 1.8 V and 600 mW down to 150 MHz at 1.0 V and 53 mW in a 0.18 /spl mu/m CMOS process. Maximum supply change without PLL relock is 10 mV//spl mu/s. Processor state save/restore enables a deep-sleep state.

Phase-locked loops (PLLs) have not been the bottleneck in processor frequency performance. However, new digital circuit families, architectural improvements, and deeper pipelines have challenged this trend. In this paper, we present two novel interpolative oscillators and a phase-locked loop which is capable of clocking even the most demanding logic families. Experimental results, from a TSMC 0.18/spl mu/m process, show oscillator frequencies as high as 4.6GHz and rms jitter values of less then 1.25ps. Additionally, the PLL was able to lock to form a 4GHz output signal. These results are among the best published to date in this process.

Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

Parametric yield loss has become a serious concern in leakage dominated technologies. We discuss the impact of leakage on parametric yield and show that leakage can cause yield windows to shrink by imposing a two-sided constraint on the window. We present a mathematical framework for yield estimation under device process variation for given power and frequency constraints. The model is validated against Monte Carlo simulations for an industry process and is shown to have typical error of less than 5%. We then demonstrate the importance of optimal supply voltage selection for yield maximization. We also investigate the sensitivity of parametric yield to applied frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.

Increased buffer insertion along on-chip global lines and the increasing contribution of leakage power have resulted in buffer leakage emerging as one of the chief contributors to system leakage power. We present a novel power-gating scheme for repeaters on global bus lines that address the pressing problem of runtime leakage while simultaneously eliminating worst-case capacitive coupling between adjacent bus lines. We propose using a pulsed MTCMOS (multiple threshold CMOS) scheme that dynamically activates the bus system only when transmitting a signal. Additionally, a bus encoding scheme is used to eliminate worst-case coupling and thereby negate the power-gating and pulse generation performance penalty. We consider all sources of delay and leakage power, including that of the MTCMOS control circuitry. This technique can result in nearly a 30% reduction in total bus system power for low switching activities and up to 2.3 times reduction in standby mode leakage with no reactivation delay penalty.

As oxide thicknesses begin to scale below 1.5 nm, gate tunneling currents are expected to become significant as compared to the drain current. In this paper, the impacts of parasitic gate currents on analog designs are explored. Specifically, current mirror topologies are considered because of their sensitivity to gate tunneling current and their ubiquitous use. A new current mirror topology, which relies on partially-depleted (PD) SOI devices, is developed to reduce the effects of gate tunneling current. These circuits were verified through simulation in a 90 nm IBM SOI technology.

This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit family. Adders are a crucial portion of all floating-point units, since they form the base element of all arithmetic functions. The 4-to-2 circuits reported previously do not meet the requirements of the next generation of processors. The adder presented here is built using a dynamic circuit style that improves performance significantly. Further a latching element after each dynamic evaluation node controls the power of the dynamic circuits. In this paper we project some of the salient features of the LSDL circuit family by comparing this 4-2 circuit with the most similar static implementation. Use of the LSDL circuit family displays significant improvement not only in terms of performance but also with respect to power dissipation, leakage and area.

In this paper, we present various design approaches to leakage minimization in global repeaters. We demonstrate the applicability of the MTCMOS scheme to global repeaters for leakage reduction. We then analyze two design approaches called Duplicated Skewed Buses and Skewed Pulsed Buses. We show that significant reduction in standby leakage power can be obtained using these approaches while providing significant improvements in performance. We also illustrate the use of these proposed techniques with the MTCMOS approach to obtain further savings in leakage power. Simulations results in a 90nm process show that skewed pulsed buses with MTCMOS can provide 20% improvement in performance with over 25% reduction in active mode leakage and nearly 100X reduction in standby mode leakage.

High-speed communications link cores must consume low-power, feature, low bit-error-rates (BER), and address many applications. We pFsent a methodology to design adaptive link architectures, whereby the link's intemal logic complexity, frequency, and supply are simultaneously adapted to application requirements. The requirement space is mapped to the design space using requirements measurement circuits and configurable logic blocks. CMOS results indicatk that power savings of 60% versus the worst case arc Dossible. while the area overhead is keot under 5%.

The TRIPS project proposes and evaluates technology for scalable and adaptive computer systems. The TRIPS processor and on-chip memory architectures are designed to handle both the increasing wire delays and power constraints of near-future integrated circuit fabrication technology. Combined with the new TRIPS compiler, the results of detailed architectural models show that the TRIPS system can achieve performance improvements by up to an order of magnitude over that of conventional architectures (at comparable clock rates) on applications ranging from signal processing to threaded server workloads. TRIPS innovations also include low-power circuits, such as latches and digital phase-locked loops, that will be required for future high-performance polymorphous chips such as TRIPS. Static power analysis tools were also developed to better estimate and balance power consumption in multiple modes of operation. The results of the proof-of-concept phase of TRIPS have shown substantial scientific promise, justifying

This presentation reports on ongoing work at the IBM Austin Research Laboratory following the development of the 1 GHz microprocessor prototype. We discuss how to realize larger microprocessor designs without sacrificing cycle time, and we discuss some of the challenges we face in achieving frequencies that are significantly higher than 1 GHz.

In this paper, we analysis the impact of gate-body signal phase on DTMOS inverters in 0.13/spl mu/m PD-SOI.

Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has developed a one gigahertz microprocessor. This paper describes the custom datapath circuit technology employed in this design. Particular attention was paid in the design process to the trade-off between performance and noise-margins. To achieve the low circuit latencies, highly-optimized and noise-characterized delayed-reset domino circuits were employed in the datapath elements of the gigahertz design.

This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM's Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.

As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.

IBM founded the Austin Research Laboratory to investigate high-performance microprocessor-based systems. Initial efforts have focused on design for high frequency. This resulted in the completion prototype for a 64-bit PowerPC processor core early in 1997. The prototype is expected to run at 800 MHz in 0.25 micron CMOS technology. We discuss clocking strategy, circuit design, microarchitecture, methodology, and the testing strategy needed to achieve this frequency.

Wave-pipelining, or maximum rate pipelining, is a circuit design technique which allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques by relying on the predictable finite delay through combinational logic for virtual data storage. Digital system design with ubiquitous use of wave-pipelining faces significant obstacles, including: synthesis and optimization of large wave-pipelined logic structures, synchronization of multiple wave-pipelines with feedback, designing for variation in IC fabrication characteristics, and register and wave-based logic codesign. We have developed analytical models, circuit techniques, and a CMOS wave-pipelining design environment to address these obstacles. These techniques and tools were employed in the design of a CMOS vector processor unit. Wave-pipelining is used in its vector registers and multiplier and adder functional units. This VLSI design is being fabricated in a 1 micron CMOS process and has been simulated at greater than 300 MHz.

SNAP-the Stanford subnanosecond arithmetic processor-is an interdisciplinary effort to develop theory, tools, and technology for realizing an arithmetic processor with execution rates under 1 ns. Specific improvements in clocking methods, floating-point addition algorithms, floating-point multiplication algorithms, division and higher-level function algorithms, design tools, and packaging technology were studied. These improvements have been demonstrated in the implementation of several VLSI designs. >

Design of the leading zero anticipator (LZA) or detector (LZD) is pivotal to the normalization of results for addition and fused multiplication-addition in high-performance floating point processors. This paper formalizes the analysis and describes some alternative organizations and implementations from the known art. It shows how choices made in the design are often dependent on the overall design of the addition unit, on how subtraction is handled when the exponents are the same, and on how it detects and corrects for the possible one-bit error of the LZA.

This 64 b single-issue PowerPC processor contains 19M transistors and is fabricated in 0.12 /spl mu/m L/sub eff/ six-layer copper interconnect CMOS. Nominal processor clock frequency is 1.0 GHz. At the fast end of the process distribution the processor reaches 1.15 GHz (1.87 V, 101/spl deg/C, 112 W). As in a previous design, nearly the entire processor is implemented using delayed-reset and self-resetting dynamic circuit macros. New contributions include: (1) a fully pipelined, four execution-stage IEEE double-precision floating-point unit (FPU) with fused multiply-add. 2) Sum-addressed memory management units (MMUs) and 64 kB 2-cycle caches. (3) Support for the full 64 b PowerPC instruction set. (4) Dynamic PLA-based control. (5) A microarchitecture and floorplan that balances critical paths. (6) Delayed-reset dynamic circuits that support stress testing (burn-in). 7) Improved clock generation and distribution.

The architecture and design methodology of a leading zero anticipator (LZA) using built-in sign-bit determination logic are described. The LZA was implemented in the 1 GHz floating point unit using a 1.8 V, 0.12/0.15(n/p)/spl mu/m L/sub eff/ IBM CMOS technology. The design shows 730 ps of latency and operates at 1 GHz with 5 levels of delayed reset dynamic circuit logic. With the LZA the sign-bit is determined in 446 ps with an area overhead of 8%, whereas a conventional adder generates the sign-bit in 770 ps.

3:2 counters and/or 4:2 compressors have been widely used for multiplier implementations. In this paper, a new logical decomposition is derived for fast 5:2 compressor and is proposed to be used for 16-bit/spl times/16-bit MAC designs. In addition, when the accumulator output is in carry-save form, one row in partial product matrix can be eliminated prior to the partial product reduction process. These new methods are combined and explained with 16-bit/spl times/16-bit 2's complement MAC (multiply and accumulate) designs. The use of the new 5:2 compressor leads to 14% speed improvement in the MAC design over the conventional designs using 4:2 compressors and 3:2 counters.

Atomic absorption spectrometry is generally accepted as a standard method in determining the presence of metals in variety of samples in low-concentration range. Standardization procedures describing water analysis deal mostly with flame atomic absorption spectrometry. The reasons lay in detection limits, which are one order of magnitude lower as compared with maximum allowed concentrations of metals. This technique is also widely applied in other analytical laboratories. Performances of flame and graphite furnace atomic absorption spectrometry in water analysis were examined in this work. Samples from the delta of Neretva River were analysed regarding to metals of geochemical importance (Fe, Mn), and those of anthropogenic origin (Zn, Cu, Pb, Cd, Ni). Analytical procedure for preconcentration of metals included evaporation of water samples by infrared lamps, followed by dissolution of dry residue in nitric acid. The metal content in prepared samples was determined by the flame atomic absorption technique. Graphite furnace atomic absorption technique was applied in determining of metal content from previously filtrated water samples that were acidified with HCl. The results obtained by both techniques show different values. Significant disturbance was examined after preconcentration procedure was applied, which indicates additional contaminations. Lower concentrations of elements were found with graphite furnace technique, which shows excellent detection limits. This fact exceeds the necessity for previous treatment of samples.

This paper presents a design methodology emphasizing early and quick timing closure for high frequency microprocessor designs. This methodology was used to design a Gigahertz class PowerPC microprocessor with 19 million transistors. Characteristics of “Timing Closure by Design are 1) logic partitioned on timing boundaries, 2) predictable control structures (PLAs), 3) static interfaces for dynamic circuits, 4) low skew clock distribution, 5) deterministic method of macro placement, 6) simplified timing analysis, and 7) refinement method of chip integration with early timing analysis.

Summary form only as given. This paper describes a structured trade-off approach that was used to make a series of product design decisions. The decision scope ranged from those that required broad stakeholder involvement to decisions that could be made by an individual engineer. The methodology allows for the assessment of risk and facilitates updating the intuition of all stakeholders.