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In this paper we present an improved neural network training algorithm and architecture for reliability analysis of a simplex system and a TMR system which includes the effects of permanent fault and intermittent fault. A fully-connected three-layer neural network represents a discrete-time n-state reliability Markov model of a fault-tolerant system. The desired reliability of the system is fed into the neural network, and when the neural network converges, the design parameters are retrieved from the weights of the neural network. Finally, the simulation results show that the proposed method converges faster than other methods, especially in the case of the state number of the Markov model, which increases. This technique is also suitable for any system.

Faults in combinational circuits are either permanent or intermittent. Intermittent faults tend to be environment-dependent; hence altering the environment might rectify these faults. These faults can be detected by applying random input-vectors (IV). The existence of random intermittent faults might require applying more random IV before detection. The detection of permanent faults requires fewer random IV but correction demands location and replacement of the faulty device, if repair is not feasible. Thus correction of a permanent fault costs more than that of an intermittent fault. The correction cost can be reduced by detecting the type of fault. Since most operational failures in a circuit are due to intermittent faults, it is very important to detect the type of fault in order to find a cheaper solution. This paper discusses the behavior of permanent and intermittent faults in combinational circuits, and introduces a test-detection model (TDM) for these faults. The error latency for an intermittent fault is derived. Two test-strategies are intermixed in the model: random testing for fault-detection, and deterministic testing for deciding on the type of fault. The activity of intermittent faults that requires the minimum number of IV for detection is emphasized. Simulation is used to demonstrate the validity of TDM. Although the variables required in TDM can be difficult to evaluate, estimation of their values is not impossible. A worst-case analysis can always be adopted, where variables are easily evaluated, to find an upper bound on the error latency; thus detection of an intermittent fault is assured with a very high probability. The cost-saving offered by intermittent-fault corrections shows the practical aspect of TDM.

Intermittent faults (IF) in chips are becoming commonplace with the current technology trend and the process scaling. In this paper, we first modify the well known birth-death Markov model so that availability can be calculated. We then show that the standard birth-death Markov model does not capture IF correctly, and create a novel Markov model for intermittent faults that is derived from the specific nature of such faults. The proposed model, for the first time, differentiates risky and normal components and therefore does not waste processing time for unnecessary testing procedures. Consequently, the availability of processors with the proposed model increases significantly compared to the traditional model (from 0.90 to 0.99 with a typical parameter set). In addition, the proposed model facilitates parameter space exploration. Positive effects were observed with varying parameters such as error rate, recovery time and test program length. It was concluded that choice of right testing parameters are vital for gaining optimal system availability and the new model supports achieving the same.

The reduction of transistor size dimensions in new technologies has provoked the apparition of new fault types. In this way, intermittent faults present a great challenge, as they are expected to be more and more common. In this work, the effects of intermittent faults in the behavior of a Fault-Tolerant microprocessor are studied. To carry out this analysis, a VHDL-based fault injection technique based on saboteurs, which allows the injection of complex fault models, has been used. Microprocessor buses have been perturbed as they are critical locations, sensitive to intermittent faults. Thus, a representative and low cost intermittent fault model set is proposed by comparing the impact and the feasibility of different intermittent fault models.

This paper presents a corrective control scheme that automatically counteracts the adverse effect of intermittent faults in the logic of asynchronous sequential machines. When an intermittent fault occurs to the machine, a set of state transitions defined in the machine suspends the normal behavior for a finite interval. The objective is to design a corrective controller that makes the closed-loop system show the normal input/state behavior despite the occurrence of an intermittent fault. We show that realization of fault tolerance depends on a certain reachability property of the asynchronous machine. For validating the applicability of the proposed control scheme, we implement the closed-loop system on VHDL code.

Current integration scales are increasing the number and types of faults that embedded systems must face. Traditional approaches focus on dealing with those transient and permanent faults that impact the state or output of systems, whereas little research has targeted those faults being logically, electrically or temporally masked -which we have named fugacious. A fast detection and precise diagnosis of faults occurrence, even if the provided service is unaffected, could be of invaluable help to determine, for instance, that systems are currently under the influence of environmental disturbances like radiation, suffering from wear-out, or being affected by an intermittent fault. Upon detection, systems may react to adapt the deployed fault tolerance mechanisms to the diagnosed problem. This paper explores these ideas evaluating challenges and requirements involved, and provides an outline of potential techniques to be applied., This work has been funded by Spanish Ministry of Economy ARENES project (TIN2012-38308-C02-01)

This paper presents a new diagnosis approach for quantitative rotor faults evaluation in three-phase wound rotor induction machines. In the considered application, the rotor windings are supplied by a static converter for the control of active and reactive power flows exchanged between the machine and the electrical grid. Under speed or fault-varying conditions, the typical rotor fault frequency components, which appear in rotor voltages, are spread in a bandwidth proportional to the speed which complicates its detectability. The proposed diagnosis approach is based on the use of wavelet analysis improved by a pre-processing of the rotor voltage commands. Thus, the time evolution of fault components can be effectively analyzed. Experimental results show the validity of the proposed method under speed and intermittent fault varying conditions, leading to an effective diagnosis procedure for rotor electrical faults in wound rotor induction machines.

As CMOS technology scales to the nanometer range, designers have to deal with a growing number and variety of fault types. Particularly, intermittent faults are expected to be an important issue in modern VLSI circuits. The complexity of manufacturing processes, producing residues and parameter variations, together with special aging mechanisms, may increase the presence of such faults. This work presents a case study of the impact of intermittent faults on the behavior of a commercial microcontroller. In order to carry out an exhaustive reliability assessment, the methodology used lies in VHDL-based fault injection technique. In this way, a set of intermittent fault models at logic and register transfer abstraction levels have been generated and injected in the VHDL model of the system. From the simulation traces, the occurrences of failures and latent errors have been logged. The impact of intermittent faults has been also compared to that got when injecting transient and permanent faults. Finally, some injection experiments have been reproduced in a RISC microprocessor and compared with those of the microcontroller. © 2012 Elsevier Ltd. All rights reserved., This work has been funded by the Spanish Government under the Research Project TIN2009-13825.

Intermittent wire faults can be caused by harsh environments, handling or simply aging of the sheathing. These types of faults are difficult to isolate due to the intermittent nature. Recent advances in intermittent fault detection have provided the aerospace and defense industry new methods to test aging aircraft wiring. In particular the use of Low Energy High Voltage (LEHV) methods and Spread Spectrum Time Domain Reflectometry (SSTDR) has shown promise in locating intermittent faults in a variety of situations. These technologies have distinct advantages which best serve the industry in a combined package. This paper presents a novel method of combining these technologies in a portable fashion to solve the growing need for intermittent fault detection.

Running with single-phase earth fault improves reliability of power supply in neutral point non-effectively grounded system, but arc-grounding and intermittent fault caused over-voltage is most likely to damage insulating security. In view of developing line-selection techniques, the increasingly success ratio of that has met the requirement on site, a new method is proposed for adaptive earth fault protection in neutral non-effectively grounded system, to be specific, the reliability of online monitoring fault line selection, the condition of over-voltage and insulation of line, severity of fault, line types and power supply reliability demand to the loads, adaptive fault line-selecting whether or when to trip, all above factors are taken comprehensively into consideration. The adaptive protection technology has been applied with well effect in enterprise grid of Shandong province of China.

Intermittent wiring faults may happen in aircraft power systems in an unpredictable manner when degraded wires are wet, vibrating against metal structures, or under mechanical stress, etc. They could evolve into serious faults that may cause catastrophic incidents and thus have raised much concern. In this paper, the AB CD method is introduced to derive normal and faulty wire models with reduced complexity compared to conventional differential equation approaches. An intermittent fault detection method is proposed based on estimation of the load circuit model coefficients and parameters utilizing the spectrum information of the high-frequency signals associated with intermittent wiring faults. Furthermore, based on the faulty wiring model, a genetic algorithm is proposed to estimate the fault related wiring parameters such as fault location and resistance. The feasibility of the proposed methods has been verified by simulations.

This paper addresses the distributed self-diagnosis of a multiprocessor/multicomputer system based on fault syndromes formed by comparison testing. The authors show that by using multiple fault syndromes, it is possible to achieve significantly better diagnosis than by using a single fault syndrome, even when the amount of time devoted to testing is the same. They derive a multiple syndrome diagnosis algorithm that in terms of the level of diagnostic accuracy achieved, is globally suboptimal, but optimal among all diagnosis algorithms of a certain type to be defined. The diagnosis algorithm produces good results, even with sparse interconnection networks and interprocessor tests with low fault coverage. It is also proven that the diagnosis algorithm produces 100% correct diagnosis as N, the number of nodes in the system, approaches /spl infin/, provided that the interconnection network has connectivity greater than or equal to 2 and that the number of syndromes produced grows faster than log N. This solution and another multiple syndrome diagnosis solution by Fussell and Rangarajan (1989) are comparatively evaluated, both analytically and with simulations. >

Algorithm-based fault tolerance has been proposed as a technique to detect incorrect computations in multiprocessor systems. In algorithm-based fault tolerance, processors produce data elements that are checked by concurrent error detection mechanisms. We investigate the efficacy of this approach for diagnosis of processor faults. Because checks are performed on data elements, the problem of location of data errors must first be solved. We propose a probabilistic model for the faults and errors in a multiprocessor system and use it to evaluate the probabilities of correct error location and fault diagnosis. We investigate the number of checks that are necessary to guarantee error location with high probability. We also give specific check assignments that accomplish this goal. We then consider the problem of fault diagnosis when the locations of erroneous data elements are known. Previous work on fault diagnosis required that the data sets produced by different processors be disjoint. We show, for the first time, that fault diagnosis is possible with high probability, even in systems where processors combine to produce individual data elements. >

Intermittent faults in electronic system will cause lots of uncertainty in maintenance, lead to a waste of time and money. There are a lot of factors that may cause intermittent faults. This paper has analyzed the causes of intermittent faults, and shows that we can reduce this negative affect by using three status Markov model. Compare to the traditional model, this new method will also reduce false alarms and improve detection rate.

With VLSI technology advances and the increasing popularity of COTS components and multi-core processor in space, aviation, and military harsh environment, dependability becomes more attractive to overcome the increasing susceptibility to transient, permanent, and wear-out induced intermittent fault. Fault injection is widely used in dependability evaluation and fault emulation. As compared to physical- and software based fault-injection tool, this paper presents a simulation based Fault Injection tool, namely FSFI, to study high-level propagations of faults and system-level manifestations, especially the underlying causes of fault manifestations, namely Symptoms in this paper. The primary contributions of this paper are as follows. First and foremost, FSFI - A Full System simulator based Fault Injection tool is designed and described in great details. FSFI is based on an open source full system simulator (SAM) and it is heavily modified to support different processor component such as ALU, decoder, integer register files, and AGEN (Address Generation Unit). Additional four modules are added to the FSFI-simulator: Fault Injector, Monitor, Analyzer, and Controller. Second, transient faults are injected into different SPARC processor components, such as ALU, decoder, integer register files, and AGEN to deliberately study fault high level manifestations and propagations from processor component, through SPARC architecture level, hyper visor, OS, to application. Third, the underlying causes of fault manifestations, namely Symptoms, such as fatal trap, high OS, high hyper, and hangs, are captured by FSFI Monitor. The distributions of Symptoms for different components against typical benchmarks are investigated, and the underlying reasons are analyzed in detail. Preliminary experiment results show that FSFI is effective for fault high level propagation and Symptom research, and some of our future work is prospected.

The practical implementation of a high voltage/low energy portable tool is discussed to address the need for intermittent fault diagnostic solutions. Recent results from aircraft testing are reported, safety validation is discussed and future system upgrades are addressed to support ease of use as a field diagnostic tool.

Intermittent failures are failures that do not manifest themselves all the time. The fact that they are sometimes there and sometimes aren't can make them very difficult to analyze.1 Some of the most difficult to diagnose faults are intermittent. It is very difficult to isolate intermittent faults which occur with low frequency.2 Intermittent electrical faults, as a rule, are notoriously difficult to detect. Sometimes an intermittent short or open circuit may leave visible signs of overheating or micro-arcing on a printed circuit board or a connector, but at other times damage may be on such a microscopic scale that it is likely to go undetected.3 The inability to find anything wrong by trying to reproduce the incident is no guarantee of the detection of an intermittent fault. This paper will discuss various ways to detect intermittent failures. The paper will discuss the root causes of intermittent failures. Also, a discussion will take place that addresses why we must pursue new techniques, methods and technologies to detect elusive failures.

Wavelets are attractive for applications that require analysis of electrical signals. In contrast to classical methodologies used to determine the spectrum of a signal in steady-state or not, and thanks to the STFT (Short Time Fourier Transform), wavelets are an interesting approach which is efficient to localize temporal peculiarities. This work presents a methodology to identify and diagnose a furtive or intermittent fault in three-phase inverter converter using a function wavelet mother type Mexican Hat. Such monitoring is based on the stator current analysis of an induction motor. Simulation and experimental results validate this study considering only the fault in the converter supplying the machine in open loop.

The trends of shrinking device geometries, lower voltages and higher frequencies in modern processors are expected to increase the rate of intermittent faults. This requires the design of software that are resilient to intermittent faults. There has been substantial research on software systems that are resilient to transient faults. However, it is unclear whether the impact of intermittent faults on programs is similar to that of transient faults. This is important for deciding if we need novel techniques for tolerating intermittent faults in software. In this study, we attempt to answer this question by comparing the effects of intermittent and transient hardware faults on programs through fault-injection experiments performed in a micro-architectural simulator for a simple five-stage pipelined processor. We also investigate whether the differences (if any) vary with the length (i.e., duration in cycles) of the fault and with the micro-architectural unit in which the fault originates. The result show that intermittent faults' impact on programs are significantly different from those of transient faults, and that the difference depends both on the length of the fault and the fault's origin. Therefore, existing software techniques for ensuring resilience from transient faults may not be sufficient for intermittent faults, and new techniques are needed.

This paper deals with an on-line fault detection and isolation method for three-phase AC drives. Small magnitude fault is considered as well as complete current sensor outage. A way to deal with intermittent fault is also provided. The method is based on hardware redundancy with additional current sensors. This approach allows the fault isolation to be performed on the whole speed range including zero speed. It is inherently insensitive to the drive parameter uncertainties and variations. Moreover, the monitoring is executed while the machine is driven with a closed-loop controller and the full dynamic performances are continuously available. A decision system based on the “CUSUM” algorithm is described, which manages the post-fault operation by taking advantage of the system redundancy.

A new time-domain approach of locating transitory, sub-cycle faults is introduced with a detailed formula derivation of the fault distance calculation for a single line-to-ground fault in the circuit of a substation, utilizing only the discrete voltage and current samples obtained at the substation. The formula is obtained from an equivalent circuit of the faulted circuit with voltage injection and the superposition principle using the parameters of net fault voltage and current. In addition to the fault distance, the approach also derives an equation which can produce the source reactance of the substation bus by the same parameters. The steps for implementing the derived formula in a practical application are illustrated, and then a preliminary test result with the actual substation measured data is discussed.

Excessive test mode power-ground noise in nanometer scale chips causes large delay uncertainties in scan chains, resulting in a highly elevated rate of timing failures. The hybrid timing violation types in scan chains, plus their possibly intermittent manifestations, invalidate the traditional assumptions in scan chain fault behavior, significantly increasing the ambiguity and difficulty in diagnosis. In this paper, we propose a novel methodology to resolve the challenge of diagnosing multiple permanent or intermittent timing faults in scan chains. Instead of relying on fault simulation that is incapable of approximating the intermittent fault manifestation, the proposed technique characterizes the impact of timing faults by analyzing the phase movement of scan patterns. Extracting fault-sensitive statistical features of phase movement information provides strong signals for the precise identification of fault locations and types. The manifestation probability of each fault is furthermore computed through a mathematical transformation framework which accurately models the behavior of multiple faults as a Markov chain. The fault model utilized in the proposed scheme considers the effect of possibly asymmetric fault manifestation, thus maximally approximating the realistic failure behavior. Simulations on large benchmark circuits and two industrial designs have confirmed that the proposed methodology can yield highly accurate diagnosis results even for complicated fault manifestations such as multiple intermittent faults with mixed fault types.

Intermittent hardware faults are bursts of errors that last from a few CPU cycles to a few seconds. Recent studies have shown that intermittent fault rates are increasing due to technology scaling and are likely to be a significant concern in future systems. We study the impact of intermittent hardware faults in programs. A simulation-based fault-injection campaign shows that the majority of the intermittent faults lead to program crashes. We build a crash model and a program model that represents the data dependencies in a fault-free execution of the program. We then use this model to glean information about when the program crashes and the extent of fault propagation. Empirical validation of our model using fault-injection experiment shows that it predicts almost all actual crash-causing intermittent faults, and in 93% of the considered faults the prediction is accurate within 100 instructions. Further, the model is found to be more than two orders of magnitude faster than equivalent fault-injection experiments performed with a microprocessor simulator.

Intermittent faults are expected to be a great challenge in VLSI circuits. The complexity of manufacturing processes, provoking residues and process variations, and special wear out mechanisms, may increase the presence of such faults. This work presents a case study of the effects of intermittent faults on the behavior of a commercial micro controller. By using VHDL-based fault injection, particularly saboteurs, we have injected different intermittent fault models in the micro controller buses, as they are critical locations, potentially sensitive to intermittent faults. We have compared the impact and the feasibility of implementation of the fault models, in order to select a representative and low cost intermittent fault load. The applied methodology can be generalized to inject intermittent faults in other locations, such as registers and memory, and to validate the dependability of critical systems.

FlexRay has been widely accepted as the next generation bus protocol for automotive networks. This has led to tremendous research interest in techniques for scheduling messages on the FlexRay bus, in order to meet the hard real-time deadlines of the automotive applications. However, these techniques do not generate reliable schedules in the sense that they do not provide any performance guarantees in the presence of faults. In this work, we will present a framework for generating fault-tolerant message schedules on the time-triggered (static) segment of the FlexRay bus. We provide formal guarantees that the generated fault-tolerant schedules achieve the reliability goal even in the presence of transient and intermittent faults. Moreover, our technique minimizes the required number of re-transmissions of the messages in order to achieve such fault tolerant schedules, thereby, optimizing the bandwidth utilization. Towards this, we formulate the optimization problem in Constraint Logic Programming (CLP), which returns optimal results. However, this procedure is computationally intensive and hence, we also propose an efficient heuristic. The heuristic guarantees the reliability of the constructed schedules but might be sub-optimal with respect to bandwidth utilization. Extensive experiments run on synthetic test cases and real-life case studies illustrate that the heuristic performs extremely well. The experiments also establish that our heuristic scales significantly better than the CLP formulation.

Wireless sensor networks (WSNs) are an important tool for monitoring distributed remote environments. Faults occurring to sensor nodes are common due to the sensor device itself and the harsh environment where the sensor nodes are deployed. It is well known that the distributed fault detection (DFD)scheme checks out the failed nodes by exchanging data and mutually testing among neighbor nodes in this network. But the fault detection accuracy of aDFD scheme would decrease rapidly when the number of neighbor nodes to be diagnosed is small and the node’s failure ratio is high. In this paper, aDFD scheme using clustering is proposed which satisfies three important diagnosis properties such as consistency, completeness and accuracy. These properties have been also proved. Simulation results demonstrate that the proposed DFD scheme increases the fault detection accuracy in comparison with a DFD scheme without clustering.

Wireless sensor network (WSN) has become monitoring solution of variety of applications. As one of the key technologies involved in WSNs, node fault detection is indispensable in most WSN applications. Faults occurring to sensor nodes are common due to the sensor device itself and the harsh environment where the sensor nodes are deployed. The goal of this paper is to locate the faulty sensors in the wireless sensor network. In this paper, a distributed fault diagnosis (DFD) scheme using clustering is proposed which satisfies three important diagnosis properties such as consistency, completeness and accuracy. To evaluate the performance of the proposed algorithm a comparative analysis and implementation is presented in this paper using an existing diagnosis algorithm i.e. distributed fault diagnosis algorithm (DFD).

Intermittent hardware faults are bursts of errors that last from a few CPU cycles to a few seconds. They are caused by process variations, circuit wear-out, and temperature, clock or voltage fluctuations. Recent studies show that intermittent fault rates are increasing due to technology scaling and are likely to be a significant concern in future systems. We study the propagation of intermittent faults to programs; in particular, we are interested in the crash behaviour of programs. We use a model of a program that represents the data dependencies in a fault-free trace of the program and we analyze this model to glean some information about the length of intermittent faults and their effect on the program under specific fault and crash models. The results of our study can aid fault detection, diagnosis and recovery techniques.

In the Armored Vechiles Electrical System BIT, transient and intermittent faults are the important causes of false alarm. Setting up false alarm probability model of the four states system, which is compared with two states model, the study shows that recognising transient and intermittent faults can reducing false alarm rate of system BIT effectively.

As CMOS technology is reaching the nanometer scale, transient and intermittent faults occurrence in logic circuits, which implies a reliability degradation, can no longer be neglected. This paper deals with reliability evaluation which is a critical parameter in circuit design. The proposed method is scalable, iterative and accelerates the reliability analysis.

The performability of a gracefully degrading process-control microcomputer is evaluated. Two Markov models, fault/error handling and fault occurrence and repair, are used to describe the microcomputer. They are solved separately using the behavioral decomposition/aggregation method. A numerical algorithm, based on Laplace and Laplace-Stieltjes transforms, it used to derive system performability. The influence of the permanent, intermittent, and transient faults underline the importance of the detection, isolation, and reconfiguration mechanisms. The effect of the parallelization algorithms is analyzed. The performability increases appreciably when global repair actions are undertaken. Local repair also has a beneficial influence, but only for large amount of required work. Adding spare processing elements improves performability. Their influence becomes visible for large amounts of work. >

The authors present and analyze a probabilistic model for the self-diagnosis capabilities of a multiprocessor system. In this model an individual processor fails with probability p and a nonfaulty processor testing a faulty processor detects a fault with probability q. This models the situation where processors can be intermittently faulty or the situation where tests are not capable of detecting all possible faults within a processor. An efficient algorithm that can achieve correct diagnosis with high probability in systems of O(n log n) connections, where n is the number of processors, is presented. It is the first algorithm to be able to diagnose a large number of intermittently faulty processors in a class of systems that includes hypercubes. It is shown that, under this model, no algorithm can achieve correct diagnosis with high probability in regular systems which conduct a number of tests dominated by n log n. Examples of systems which perform a modest number of tests are given in which the probability of correct diagnosis for the algorithm is very nearly one. >

In this paper we will apply a SEC-DED code to the cache level of a memory hierarchy. From the category of SEC-DED (Single Error Correction Double Error Detection) codes we select the Hsiao code. The Hsiao code is a odd-weight-column SEC-DED code. For correction of single-bit error we use a syndrome decoder, a syndrome generator and the check bits generator circuit.

Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Scan chain defects constitute a significant fraction of the overall digital defect universe, and hence it is well justified that scan chain diagnosis has received increasing research attention in recent years. In this paper, we address the problem of scan chain diagnosis for intermittent faults. We show that the conventional scan chain test pattern is likely to miss an intermittent fault, or inaccurately diagnose it. We propose an improved scan chain test pattern which we show to be effective. Subsequently, we demonstrate that the conventional bound calculation algorithm is likely to produce wrong results in the case of an intermittent fault. We propose a new lowerbound calculation method which does generate correct and tight bounds, even for an intermittence probability as low as 10%.

In wireless sensor networks (WSN), faults occurring to sensor nodes are common due to the sensor device itself and the harsh deployment environment. In order to avoid degradation of service due to faults, it is necessary for the WSN to be able to detect faults early. In this paper we propose a localized fault diagnosis algorithm which executes in tree-like networks effectively. It is based on local comparisons of sensed data and dissemination of the test results to the remaining sensors. Furthermore, Times redundancy is used to diagnose the intermittent fault in sensing and communication. Simulation results show the proposed algorithm has high detection accuracy and low false alarm rate.

This paper presents a new methodology for permanent and intermittent fault diagnosis, named faults latent nestling method (FLNM), using coloured Petri nets (CPNs). CPNs and FLNM method allow for an enhanced capability for synthesis and modelling of complex systems in contrast to the classical phenomena of combinational state explosion when using finite state machine based methods.

This article describes the No Fault Found (NFF) phenomenon that occurs when a system is tested after a failure is reported but no failure is found during the test. This basic phenomenon is known by a large number of terms, which are often abbreviated to three letter acronyms, and are described in this article. The level of occurrence of such false positive faults in various technical fields is described and a number of possible reasons for the incidence are discussed. Finally a discussion of the management of such faults within the context of quantitative risk assessment is included. Keywords: No Fault Found; NFF; intermittent fault

Diagnosis of intermittent faults is relevant for productive processes with a high level of maintenance caused by such failures. A characterization of diagnosed faults may save unnecessary repairs and enable better maintenance planning. This paper introduces the concept of diagnosis of intermittent fault dynamics. Moreover, a methodology for modelling intermittent faults and generating information for maintenance planning in discrete event systems is thoroughly covered.

Aging aircraft electronic boxes often pose a maintenance challenge in that often after malfunctioning during flight in the aircraft, they test good, or ldquoNo Fault Foundrdquo (NFF) during ground test. The reason many of these boxes behave in this manner is that they have intermittent faults, which are momentary opens in one or more circuits due to a cracked solder joint, corroded contact, sprung connector receptacle, or any number of other reasons. These NFF boxes often account for a substantial number of boxes processed through a maintenance facility, where no repair can be performed, because no problem can be detected. Conventional test equipment is designed to test the electronic box for nominal operation, and usually ldquoaverages out,rdquo and hence hides, any short term anomalous event. This paper describes a tester that was specifically designed to detect and isolate the intermittent circuits in an electronic box chassis. This new and innovative tester has been designated the intermittent fault detection and isolation system (IFDIS). The IFDIS very effectively compliments conventional testers. The IFDIS includes an environmental chamber and shake table to subject the box to simulated operational conditions, which greatly enhances the probability the intermittent circuit will manifest itself. The IFDIS also includes an intermittent fault detector which continuously and simultaneously monitors every electrical path in the chassis under test, while the box is exposed to a simulated operational environment. To determine the effectiveness of this new tester in detecting and isolating intermittent circuits, several dozen electronic boxes, identified by serial number, that had been to the repair facility and tested NFF multiple times were selected for IFDIS testing. One or more intermittent faults were detected, isolated and repaired in nearly every box. These boxes were then tested on the conventional tester and returned to service. We are currently monitoring their performance to determine their increased service life and reduced number of NFF incidents.

This chapter summarizes concisely optimum maintenance policies for reliability models without detailed mathematical explanations: First, standard replacement models such as age, block, and periodic replacements are taken up, and are converted to modified models with finite operating times and random replacement times. Furthermore, replacement policies for inspection models, cumulative damage models, and a parallel system are proposed. Secondly, preventive maintenances (PMs) of one-unit and two-unit systems are discussed. Modified models with periodic PM times, imperfect PM, and repair limit are proposed. Optimum policies that minimize the expected costs or maximize availabilities are summarized. Finally, as applications of maintenance models, optimum policies for computer systems with intermittent faults, imperfect maintenance, and restart are discussed. These results should be very helpful in applications of maintenance models and studies of reliability theory.

Wiring onboard of legacy aircraft is becoming a liability due to a prolonged use of aircraft. Testing as well as repairs and maintenance require extensive number of man-hours bringing up the costs and reducing flight time of the aircraft. There is a number of conventional electric testing methods for wire testing, yet we propose and evaluate an acoustic (mechanical) testing method. Acoustic testing can be used online while the wire is in operation, and has the capability for intermittent fault detection.We report modelling and experimental results of an insulated wire that indicate this technique can be used to detect mechanical faults in insulation and conducting wire core. We used two different methods to detect and locate insulation defects of only 0.2mm wide. Transmission mode allowed a clear detection of the defect while reflection mode yielded the defect position.

This paper presents a new methodology for permanent and intermittent fault diagnosis, named Faults Latent Nestling Method (FLNM), using Coloured Petri Nets (CPNs). CPNs and FLNM method allow for an enhanced capability for synthesis and modelling in contrast to the classical phenomena of combinational state explosion when using Finite State Machine based methods.

Many studies have confirmed that electronic failure is not a static or random event, but a process of material changes. These changes may not cause loss of operation for the electronic system, even when the components are technically out of specification. This self- compensating aspect of electronics makes diagnostics of failures particularly difficult and contributes to the ubiquitous problem of cannot duplicate (CND) failures. In addition to self-compensation, degraded failure modes of components manifest in different operating conditions and may offset one another depending on circuit configuration.12 With these considerations, VEXTEC is developing an intermittent fault reduction methodology which considers the material changes in the electronic components on the circuit board and provides a probability of true fault when a fault is detected by built in test (BIT). By modeling the electronics as a system rather than focusing on individual components, VEXTEC can model an entire circuit board with a standard library of models as part of the OEM's normal design cycle. The model is then used with the off board PHM (Prognostics and Health Management) system within a vehicle or other high reliability electronic system to predict the probabilities of intermittent failure. This modeling capability has far reaching effects on the diagnostics and prognostics of an electronic system. The operators can manage the fleet by risk rather than by guessing the level of degradation or when intermittent failures will occur. Organizations responsible for quality, maintenance and repair can minimize the impact of CND faults on the supply chain and on troubleshooting. The order of components replaced during a fault event can even be prioritized according to the probabilities provided by this algorithm.

This paper suggests a stochastic model how to determine a fault margin in a computer system, who fails when the total number of hidden faults exceeds a threshold level N of tolerance: A fault occurs at a non-homogeneous Poisson process, and (i) becomes system failure with probability p1, (ii) becomes hidden fault with probability p2 and is accumulated, or (iii) is removed with probability p3. The expected cost rate to system failure is derived, and an optimal number N∗ to minimize it is discussed. A numerical example is finally given.

This paper proposes a probabilistic approach to diagnose intermittent faults in a wireless sensor network (WSN). Though system level diagnosis has become an important technique to diagnose faults in wired networks, its applicability to wireless network has not been well studied. Though, intermittent faults are most probable in WSN, diagnosis of such faults has not been well explored. The algorithm proposed in this paper has been evaluated through analytical means and is simulated assuming a 512 sensor nodes interconnected to form an arbitrary network topology. The results show that accurate diagnosis of intermittent faults in WSN is feasible.

This paper deals with an approach for the detection and localization of intermittent faults in discrete events systems with partial observability. The proposed methods are based on a discrete events model representing the normal functioning of the observable behavior of the monitored system. This model based on the Petri net formalism is built from the design data. The detection mechanism consists of a comparison between the flow of observable events emitted by the monitored system and the flow foreseen by the model. A localization step complete the detection mechanism and points out the set of events potentially responsible for the faults. These two mechanisms are designed in order to operate on-board, in real time. An example from the automotive domain is presented. Copyright ©2006 IFAC

Reducing false alarm have important signification for accurate diagnosis of equipments' faults. The classification of built in test is introduced in the paper. Then the equipments status is redefined to three kinds of state (namely as fault state, quasi fault state, health state). Among them, the intermittent fault, transient fault, and the critical fault are included in the quasi fault. The 3-state Markov model is contrasted and analyzed with 2-state Markov model on theory. The advantage to divide the equipments status as new three kinds of states is pointed out. Joining together the method of fuzzy clustering theories, running fault condition of rotor system are classified and identified. The intermittence fault and transient fault of rotor are successfully separated on the verifying platform. It is show by computation and analysis that the method of judging the threshold value of the equipments status is viable by choosing the F-statistic. The method introduced in the paper has important reference value for reducing false alarm of the equipment.

In this paper we introduce a technique for runtime fault detection and localization in component-oriented software systems. Our approach allows for the definition of arbitrary properties at the component level. By monitoring the software system at runtime we can detect violations of these properties and, most notably, also locate possible causes for specific property violation(s). Relying on the model-based diagnosis paradigm, our fault localization technique is able to deal with intermittent fault symptoms and it allows for measurement selection. Finally, we discuss results obtained from our most recent case studies.

The goal of this chapter is to present BOND, a Software Fault Injection tool able to simulate abnormal behavior of a computer system running Windows NT 4.0/2000 Operating System. The Fault Injector is based on interposition techniques, which guarantees a low impact on the execution of the target program, and allows the injection of Commercial off-the-Shelf software programs. BOND allows performing both statistical and deterministic Fault Injection experiments, trading-off between overhead and precision of the obtained results. Moreover, the tool is capable of injecting faults into different locations, at any level of the application context (code and data sections, stack, heap, processor’s registers, system calls...). A complete set of experimental results on different application programs demonstrates the effectiveness and the flexibility of the tool.