1,495 results on '"Huazhong Yang"'
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252. An Auto Loss Compensation System for Non-contact Capacitive Coupled Body Channel Communication.
253. Energy Efficient ApproxSIFT Implementation for Image Mosaic with Approximate Computing Technologies.
254. CMOS Image Sensor Data-Readout Method for Convolutional Operations with Processing Near Sensor Architecture.
255. Bidirectional Recurrent Neural Network And Convolutional Neural Network (BiRCNN) For ECG Beat Classification.
256. Real-Time ECG Delineation with Randomly Selected Wavelet Transform Feature and Random Walk Estimation.
257. Channel Loss in Contactless Human Body Communication.
258. Region Aggregation Network: Improving Convolutional Neural Network for ECG Characteristic Detection.
259. Approximate On-chip Memory Optimization Method For Deep Residual Networks.
260. An Efficient Reconfigurable Framework for General Purpose CNN-RNN Models on FPGAs.
261. Scene-Adaptive Image Acquisition for Focus Stacking.
262. MINTIN: Maxout-Based and Input-Normalized Transformation Invariant Neural Network.
263. Training low bitwidth convolutional neural network on RRAM.
264. Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array.
265. An Investigation on Inter-degeneration Effect in Body Channel Based Multi-node Wireless Power Transfer.
266. Rescuing memristor-based computing with non-linear resistance levels.
267. HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing.
268. Real-time object detection towards high power efficiency.
269. Spatial-Temporal Attention Res-TCN for Skeleton-Based Dynamic Hand Gesture Recognition.
270. Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support.
271. Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks.
272. RRAM Based Buffer Design for Energy Efficient CNN Accelerator.
273. Energy-Efficient SRAM Design with Data-Aware Dual-Modes L0T Storage Cell for CNN Processors.
274. Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processors.
275. Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification.
276. Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices.
277. A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture.
278. Ensemble-in-One: Learning Ensemble within Random Gated Networks for Enhanced Adversarial Robustness.
279. Multi-Agent Vulnerability Discovery for Autonomous Driving with Hazard Arbitration Reward.
280. Learning Efficient Multi-Agent Cooperative Visual Exploration.
281. A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization.
282. A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation.
283. Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs.
284. Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs.
285. A global and updatable ECG beat classification system based on recurrent neural networks and active learning.
286. An Auto Loss Co Jian Zhaompensation System for Capacitive-Coupled Body Channel Communication.
287. Dynamic Channel Modeling and OFDM System Analysis for Capacitive Coupling Body Channel Communication.
288. TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks.
289. GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.
290. Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.
291. A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System.
292. A Task Failure Rate Aware Dual-Channel Solar Power System for Nonvolatile Sensor Nodes.
293. A single clock cycle approximate adder with hybrid prediction and error compensation methods.
294. [DL] A Survey of FPGA-based Neural Network Inference Accelerators.
295. HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing.
296. Streaming sorting network based BWT acceleration on FPGA for lossless compression.
297. Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA.
298. CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks.
299. CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper).
300. Evaluating Data Resilience in CNNs from an Approximate Memory Perspective.
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