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A novel odd-even column-level passive sample and column-shared active readout structure is proposed to realise a high speed, low power and low noise readout integrated circuit (ROIC). This structure reduces the number of operational amplifiers (OPAs) in each column and decreases the power consumption of the column capacitive transimpedance amplifier (CTIA) and output buffer. Compared to the traditional design for medium-scale array ROIC, power consumption of a single column is reduced by 80%. A 320 × 320 array ROIC has been designed for indium antimonide (InSb) cooled infrared detector using the novel structure. The chip is fabricated in the 0.35 μm CMOS process. The total power consumption is

The current study was conducted to investigate the effects of dietary zinc oxide (ZnO) on the antioxidant capacity, small intestine development, and jejunal gene expression in weaned piglets. Ninety-six 21-day-old piglets were randomly assigned to three dietary treatments. Each treatment had eight replicates with four piglets per replicate. The piglets were fed either control diet (control) or control diet supplemented with in-feed antibiotics (300 mg/kg chlortetracycline and 60 mg/kg colistin sulfate) or pharmacological doses of ZnO (3000 mg/kg). The experiment lasted 4 weeks. Blood samples were collected at days 14 and 28, while intestinal samples were harvested at day 28 of the experiment. Dietary high doses of ZnO supplementation significantly increased the body weight (BW) at day 14 and average daily gain (ADG) of days 1 to 14 in weaned piglets, when compared to control group (P

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35µm CMOS technology. It occupies an area of 2.113i?0.81mm2. Measurement results show that the proposed channel can process up to 1MHz counting rate and provide a conversion gain of about 170mV/fC at a power dissipation of 330µW with a 3.3V power supply. Ac-coupled to a silicon PIN detector, it successfully detects s-rays.

Tight junctions (TJs) play an important role in maintaining the mucosal barrier function and gastrointestinal health of animals. Lactobacillus plantarum (L. plantarum) was reported to protect the intestinal barrier function of early-weaned piglets against enterotoxigenic Escherichia coli (ETEC) K88 challenge; however, the underlying cellular mechanism of this protection was unclear. Here, an established intestinal porcine epithelia cell (IPEC-J2) model was used to investigate the protective effects and related mechanisms of L. plantarum on epithelial barrier damages induced by ETEC K88. Epithelial permeability, expression of inflammatory cytokines, and abundance of TJ proteins, were determined. Pre-treatment with L. plantarum for 6h prevented the reduction in transepithelial electrical resistance (TEER) (P

A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

An all-digital comparator with full input range is presented. It outperforms the nowaday all-digital comparators with its large rail-to-rail input range. This is achieved by the proposed Yin-yang balance mechanism between the two logic gates: NAND3 and OAI (Or-And-Invert). The important design considerations to achieve this balance are presented, such as the driving strength manipulation and the use of pre-distortion technique. Constructed only by commercially available digital standard cells, the layout of the proposed comparator is generated automatically by standard digital Place & Route routine within several minutes. The Verilog code for the proposed circuit is given, and the circuit is successfully implemented in 130nm CMOS technology with the power consumption of 0.176mW at the clock of 330MHz., This paper has been withdrawn by the author due to the imperfection of the circuit, i.e., the long reset time of hundreds ns to several us

A two-stage charge sensitive amplifier architecture suitable for semiconductor radiation detector with large capacitance is proposed. The integration capacitor of the first stage can be made large to reduce gain sensibility to detector capacitance without any stability problem. Each stage uses a self-biased MOS transistor to discharge the integration capacitor. The self-bias circuit tracks process, temperature and supply voltage variations to make a relatively constant feedback resistor. This improves the gain linearity of the charge sensitive amplifier and the uniformity of multi-channel front-end electronics. The feasibility of the proposed circuit is verified by comparing the simulation results with the conventional one-stage charge sensitive amplifier and a two-stage structure with fixed-gate-voltage reset transistor. A prototype of 16-channel front-end circuit for electron collection designed in a 0.35μm CMOS technology has been measured. The area is 2.5×1.54mm2 with 42 pads and the power dissipation is 60mW with power supplies of 2V and 5V.

MEMS sensors often suffer from distance mismatch that the proof mass does not lie in the right middle of the two fixed plates. The mathematical formulae presented in this paper show that this asymmetry of MEMS sensor does not influence the linearity of accelerometer as a whole, and only introduces an offset. This is true not only for continuous time closed loop, but also for time divided architecture. For this kind of asymmetric sensors, Matlab/Simulink models are established. Simulation results confirm theoretical formulae. To testify this theory, a readout circuit of time divided architecture is designed and fabricated using 0.35µm HV CMOS process. Test results show that the nonlinearity of the tested accelerometer with the asymmetric sensor is within 0.3%.

Matlab/Simulink tool has been widely used in system modeling of circuit design. However, its application in the discrete-time circuit is not enough mature. Based on the continuous-time circuit simulation results by Matlab/Simulink, an s-z transformation method for the discrete-time accelerometer system design is proposed in this paper. In this method, a switched-capacitor readout circuit for closed-loop micromechanical capacitive accelerometer is designed and fabricated in a 0.35µm 15V CMOS process. The accelerometer operates under ±6.5V supply with a full scale of ±50g and the equivalent noise acceleration (ENA) is tested to be 54µg/√Hz at 60Hz.

Linearity which determines the system precision is one of the main performance parameters of accelerometers especially the wide-range ones. The design parameters of the interface circuit have a great effect on the linearity of the accelerometer system utilizing time-division force feedback (TDFF). In this paper, the nonlinearity resulting from time-division force feedback is discussed and the formulae reflecting the relationship between the system linearity and the design parameters are derived, which can help the designers to adjust timing parameters according to the linearity demand. The theory is verified by Matlab/Simulink numerical simulation. Based on the design formulae presented, a ±30g closed-loop TDFF capacitive micro-accelerometer is implemented in 0.35µm high-voltage CMOS process, which operates under ±6.5V supply and achieves linearity of 99.72%in the self-test mode.

A 14-bit Column-level ADC for Infrared Focal Plane Array (IRFPA) is proposed in this paper. Correlated switch structure is designed, which helps to cancel the offset generated by injected charge and then achieves accurate sampling and holding. Odd-even structure is realized to make longer converting time after sampling. Comparators with two-stage pre amplifiers use low power supply voltages, which ensures low power operation, as well as low noise. Conversion accuracy of the ADC circuit can reach 14-bit. The structure is used for a 640×512 array.