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Novel l ow-voltage first-order and second-order square-root-domain all-pass filters derived systematically by means of transfer function decomposition and state -space synthesis techniques are proposed. The employment of only a few geometric-mean cells and grounded capacitors permits the circuits to absorb shunt parasitic capacitances, which is desirable for production in monolithic form . The circuits enjoy the features of electronic adjustment of frequency characteristics, wider dynamic range and low-voltage environment operation. The filters are employed to design high-order all-pass filters using cascade approach. First-order low-pass and second-order band-pass filters, being the inherited building blocks of the proposed low-order all-pass filters are also discussed. The behaviour of the filters is evaluated through simulations using Taiwan semiconductor manufacturing company 0.25 μm level-3 complementary metal oxide semiconductor process parameters, where the most important performance factors are considered.

This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used to transmit the measurement results to a base station. As the harvested solar energy varies considerably in different lighting conditions, in order to guarantee autonomous operation of the sensor, the proposed area- and energy-efficient circuit scales the power consumption and performance of the sensor. The power management circuit dynamically decreases the operating frequency of digital circuits and bias currents of analog circuits in the sensor interface circuit and increases the idle time of the transceiver under reduced light intensity. The proposed microsystem has been implemented in a 0.18 µm complementary metal-oxide-semiconductor (CMOS) process and occupies a core area of only 0.25 mm2. This circuit features a low power consumption of 2.1 µW when operating at its highest performance. It operates with low power supply voltage in the 0.8V to 1.6 V range.

A low-power voltage reference cell for system-on-a-chip applications is presented in this paper. The proposed cell uses a combination of standard transistors and thick-oxide transistors to generate a voltage above 1 V. A design procedure is also presented for minimizing the temperature coefficient (TC) of the reference voltage. This circuit was fabricated in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. It generates a 1.52 V output with a TC of 42 ppm/∘C from −70 ∘C to 85 ∘C while consuming only 1.11 μW.

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Data converters play a key role in modern analog/mixed-signal systems. Accordingly, it is important to investigate their performance and yield under uncertain parameters over the design process. An efficient approach for automatic design and yield enhancement of data converters is presented. The proposed algorithm generates a general netlist for each data converter and improves transistor sizing to reach acceptable values for performance parameters with an evolutionary process, and finds the best yield simultaneously. The applied framework on two data converter structures demonstrates a reliable circuit with optimum performance, power consumption, and area overhead over a single evolutionary process in 0.18m technology. [ABSTRACT FROM AUTHOR]

Deadtimes are required to avoid simultaneous conduction of high-side and low-side power transistors in half-bridge power converters. During these secure times, free-wheeling current flow generates extra power losses. Very short deadtimes are desired but they cannot be safely set in conventional isolated power converters because of a digital input propagation delay mismatch. A specific deadtime management is introduced in this paper to ensure proper operation of a high-voltage synchronous power converter. A controller integrated in each isolated gate driver secures synchronous switching by detecting the opposite switch turn-off before turn-on. With such a selfswitching technique, very short but safe nonoverlap times can be set. A gate driver has been implemented in a 0.35 μm 20-V CMOS process. The monolithically integrated controller consumes only 140 μA and 0.22 mm2 of silicon area. The proposed local deadtime management has been validated in two synchronous buck converters without external free-wheeling diodes: a 500-W 250-V to 55-V converter based on SiC JFETs and a 30-W 45-V to 10-V converter based on eGaN FETs. In either case, the proposed controller allows a higher efficiency from 10% of the rated load with resulting deadtimes as short as 15 ns. [ABSTRACT FROM AUTHOR]

This paper presents a new methodology to extract spectral information of radiated THz signals to enable a fully integrated broadband THz spectroscope in silicon. A classical down-conversion spectrum analysis architecture requires on-chip generation of LO signals covering GHz-THz frequencies to analyze an incident spectrum covering that range. This paper presents a method to exploit the interaction between the front-end antenna and the incident signal to extract spectral information eliminating the need for extremely wideband LO generation and the entire receiver architecture following the antenna. The central premise is that the incident THz signal excites a spectrum-dependent current distribution on the antenna surface and this work presents a method to measure and then estimate the incident spectrum from the impressed current distribution on an on-chip antenna. The chip is implemented in 0.13~\mu \text m SiGe BiCMOS technology and measures 2.6 mm $\times 1.9$ mm. Measurement results are presented for various incident spectra between 40–330 GHz. In addition, the paper presents a method for extracting time-domain information by exploiting the variable nonlinearities of the integrated detectors. By modifying a classical single-port antenna into a 2D multi-port scatterer, the paper presents a synthesizer-free THz spectroscope which consists of an integrated scatterer and multitude of low-power sensors capable of sub-wavelength measurement of near-field interactions which are exploited for spectral estimation. [ABSTRACT FROM AUTHOR]

In this brief, a 28.8-MHz −3-dB frequency low-pass analog filter is presented. The filter synthesizes a fourth-order Butterworth transfer function, exploiting the well-known Sallen-Key (SK) biquadratic cell. The out-of-band zeros typically present in SK implementations are hereby completely canceled by using a low-power auxiliary path. This leads to a significant improvement of the stop-band rejection, at the cost of a small power for the same auxiliary path biasing. The design exhibits very large in-band IIP3 over the entire filter bandwidth (20 dBm at 10 MHz and 11 MHz), at 3.2-mW power consumption. The filter prototype has been designed in CMOS 0.18- \mu \textm technological node. The total area occupancy is 0.12 mm ^ 2 and the in-band integrated noise is 101~ \mu \mathrmV\mathrm{RMS} . [ABSTRACT FROM PUBLISHER]

This paper presents ring modulator driver and receiver circuits designed for three-dimensional photonic–electronic integration using interwafer connections, whose parasitic capacitance is expected to be in the order of 15 fF. Both transmitter and receiver can operate with binary and PAM-4 modulation at 10 Gb/s. To the authors knowledge, it is the first PAM-4 ring modulator driver being presented. The circuits are designed in AMS 0.35-μm SiGe BiCMOS technology with total power consumptions of 160 and 180 mW for transmitter and receiver, respectively. The receiver's sensitivity is –27 dBm for binary and –22 dBm for 4-PAM signals both at a photodiode responsivity of R = 0.9 A/W. A monitor transimpedance amplifier with sensitivity –32 dBm was also designed in order to control the operating point of the ring modulator. [ABSTRACT FROM PUBLISHER]

CMOS ADC-based serial link receivers enable powerful digital equalization and symbol detection techniques for high data rate operation over electrical and optical wireline channels. Common ADC architectures and equalization techniques that allow 10 Gb/s and higher operation are surveyed in this article. As time-interleaving is most often employed to achieve these high sampling rates, the associated errors and calibration techniques are presented. The impact of ADC quantization noise on receiver performance and how this can be improved via embedded partial analog equalization are detailed. A description of a 65 nm CMOS hybrid ADC-based receiver architecture that employs a 3-tap analog FFE embedded inside a 6-bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer operating at 10 Gb/s concludes the discussion. [ABSTRACT FROM PUBLISHER]

This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC elements, each modeling a finite length increment of the line. Inductors are then emulated by a gyrator-capacitor combination, yielding a classical transconductor-capacitor (gm-C) circuit, suitable for integration. The validity of this approximation is discussed in the context of fault location in power networks, an application based on the electromagnetic time-reversal method. Design constraints on gm-C circuits are derived and non-ideal effects such as finite open-loop gain and component mismatches are evaluated. It is shown that a simple analog implementation can locate the fault within 1 % accuracy with a significant speed advantage over classical computational methods, reducing the processing time to <100 ms. [ABSTRACT FROM AUTHOR]

This paper shows that an important part of the power consumption of a biquad band-pass filter is associated with the feedback loop that fixes the high-pass frequency and blocks the direct current (dc) input signals. The dc input amplitude that can be blocked is related to the maximum output current that one of the transconductors can provide, hence impacting on the required consumption through this effect. Then, a technique that efficiently blocks the dc input signal and fixes the high-pass frequency is introduced and analyzed in depth. Moreover, an architecture for ultra-low-power differential-input biquads is fully presented. The proposed architecture enables lowering the power consumption or blocking higher levels of dc input without jeopardizing the power consumption. Results show that the proposed architecture, compared with a traditional one, presents a 30% reduction in power consumption and more than doubles the dc input that can be blocked. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents a method to address the automatic testing of analog ICs for catastrophic defects. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automatically by a workflow based on DC simulations and optimization algorithms. Adopting a defect-oriented methodology, this approach maximizes the fault coverage while minimizing the silicon area overhead and test time. The proposed method is applied to two industrial circuits in order to generate optimal test infrastructures combining controllability and observability. These case studies show that, with a silicon area overhead of less than 10%, a fault coverage of 94.1% can be reached. [ABSTRACT FROM AUTHOR]

This paper focuses on the implementation of different techniques for the integration of yield estimation in the synthesis loop of analog integrated circuits (ICs). MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is considered to be a very powerful multi-objective optimization algorithm. For the consideration of yield, several techniques are discussed and three different yield-aware Pareto front (PF) generation techniques have been implemented on the MOEA/D optimizer. The implemented yield-aware PF techniques are compared by designing a fully-differential folded-cascode amplifier with different number of objectives. In order to embed the variation effects into the optimization loop, the statistical analysis of the circuit has been carried out by using a Quasi Monte Carlo (QMC) technique. The results suggest that especially two of these techniques look promising for high dimensional robust optimization of analog circuits. [ABSTRACT FROM AUTHOR]

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity. Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive. This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations. [ABSTRACT FROM AUTHOR]

In this paper, the concept of hierarchical multi-objective optimization is applied to analog integrated circuit placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce post-layout routing-induced parasitics of the circuit. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration-aware optimization of the optimal wiring topology for all nets of the circuit. The problem׳s complexity is reduced using the hierarchy in the circuit׳s partitions, combining, bottom-up, Pareto fronts of placements that explore the tradeoffs between the design objectives. The approach is demonstrated in analog circuit structures for the United Microelectronics Corporation 130 nm design process. Post-layout simulations show the importance of considering both current-flow and current-density considerations for an effective fully-automatic placement. [ABSTRACT FROM AUTHOR]

This paper presents a knowledge-based fuzzy approach to symbolic circuit simplification in an effort to imitate human reasoning and knowledge of circuit designer experts. The fuzzy approach differs from the conventional simplification techniques in that it can efficiently combine different input variables to obtain optimal simplified expressions. Additionally, this method was chosen due to its adjustability and interpretability, as well as its ability to manage very complex symbolic expressions. The proposed algorithm uses fuzzy logic to simplify the symbolic circuit transfer functions in two stages. In the first stage, a fuzzy system is applied to directly eliminate nonessential circuit components, resulting simplified circuit topology which also yields simpler transfer function. In the second stage, another fuzzy system is used to further simplify the symbolic transfer function from the already simplified circuit, such that deeper insight into the circuit behavior can be obtained. Symbolic and numerical results show that the fuzzy approach outperforms the conventional techniques in terms of accuracy, expression complexity, and CPU running time. [ABSTRACT FROM AUTHOR]

This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO® or CALIBRE®. [ABSTRACT FROM AUTHOR]

In this study, a low-voltage low-power design of previously introduced analog signal processing element called as Voltage Differencing Inverting Buffered Amplifier (VDIBA) is presented. Level shifter current mirrors are used in the circuit design in order to accomplish the low-voltage low-power operation. The configuration operates only with ±0.4 V supply voltages and consumes power 569 µW at the bias current 50 µA. Also, low-voltage transconductor which has highly linear gm is executed with the use of bulk-driven quasi-floating gate (BD-QFG) and source degeneration techniques. The simulations of the introduced circuit have been performed with 0.18 µm TSMC CMOS technology by SPICE. The theoretical approaches have been confirmed by the simulation results. [ABSTRACT FROM AUTHOR]

This paper proposes a diode-free Operational Transresistance Amplifier (OTRA) based Time Marker Generator (TMG). It comprises of three stages. The first stage uses OTRA in open loop configuration, behaving as a comparator. A RC differentiator is used in the second stage to achieve voltage spikes. The third stage employs a MOS transistor to obtain the desired output. The proposed time marker generates spikes at positive or negative cross points depending upon the type of MOS transistor used. To illustrate the operation of the proposed TMG, SPICE simulations are performed using CMOS based OTRA implementation that uses 0.18 μm CMOS technology parameters. Simulations corroborate with the theoretical predictions. [ABSTRACT FROM AUTHOR]

Layout-dependent effects (LDEs) have become a critical issue in modern analog and mixed-signal circuit designs. The three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, significantly affect the threshold voltage and mobility of devices in advanced technology nodes. In this paper, we propose the first work to consider the three major sources of LDEs during analog placement. We first transform the three LDE models into nonlinear analytical placement models. Then an LDE-aware analytical analog placement algorithm is presented to mitigate the influence of the LDEs while improving circuit performance. Experimental results show that our placement algorithm can effectively and efficiently reduce the LDE-induced variations and improve circuit performance. [ABSTRACT FROM AUTHOR]

The transconductance of current differencing transconductance amplifier (CDTA) has been enhanced by combining the two methods. The first method is reported recently in Rai and Gupta (2015) while the second method is a novel one. These methods can also be merged together to enhance the transconductance of other analog building blocks (ABBs). In the first method, MOSFETs used in the differential pair of transconductance amplifier (TA) has been replaced by the networks N1 and N2 which contains the ‘n’ symmetrical MOSFETs in parallel; where n is the number of MOSFETs. Thus, the voltage which was applied earlier to the differential pairs has now been applied to these networks (N1 and N2) which inject equal currents in all the MOSFETs used. The total current (I T ) coming out of the networks (N1 and N2) will be the sum of currents drawn by all the MOSFETs used in these networks. In the second method, the total current (I T ) copied by various current mirrors are added at the output node (X+ and X−) of CDTA in order to enhance the transconductance effectively. The advantage of this method is that the transconductance has been boosted while the power dissipation of CDTA remains unaffected for a particular biasing current. [ABSTRACT FROM AUTHOR]

This paper presents a new technique to improve the power efficiency for high-voltage non-isolated DC-DC converters running at high switching frequencies. A passive-saving two-phase quasi-square-wave zero-voltage-switching (PS-TPZVS) cell that consists of an auxiliary inductor and a capacitor sharing between two phases of sub-converters is proposed to realize ZVS operation for all power FETs under different conditions. Compared to the traditional two-phase ZVS topology, the proposed design saves 1 auxiliary inductor and 1 auxiliary capacitor for establishing ZVS of power FETs, and thus reduces both the volume and power losses of the auxiliary circuitry. To verify the performances of the proposed PS-TPZVS cell, a 140-W 4-MHz two-phase QSW-ZVS converter is designed and verified by simulations to achieve peak efficiencies of 97 % with enhancement-mode GaN FETs and 95 % with power MOSFETs. The proposed PS-TPZVS cell can also be applied to various topologies of non-isolated DC-DC converters and extended into a 2 N-phase topology with only N additional branches of the proposed cell. [ABSTRACT FROM AUTHOR]

This paper describes a gain enhancement method and also a slew-rate enhancement scheme for folded-cascode amplifiers which uses positive feedback + transconductance increaser method for the sake of gain increment that gives rise to approximately 21 db of increment in the amount of the gain. An approach for increasing the slew-rate has also been employed which has increased the slew-rate of the amplifier approximately 5 times the conventional folded-cascode one as well as the triple folded-cascode one. Also the settling time and consequently the speed of the circuit is improved remarkably i.e. over 6 times the conventional folded-cascode and triple folded cascode ones. The amplifier has been designed in TSMC RF 0.18 μm and consumes 920 µw of power meanwhile provides 67 db for gain, 581 MHz for UGBW, 69° for phase margin, 793 V/µS for slew-rate and 3.2 nS for large-signal settling time as well as the gain-error of the amplifier for large-signal is approximately 0.5 %. The layout of the circuit has also been carried out in Cadence and demonstrates that the op amp occupies 41 µm × 61 µm (0.002 $$\text{mil}^{2}$$ ) of the die area. The post-layout-simulation of the op amp was also fulfilled and the results are displayed. [ABSTRACT FROM AUTHOR]

In this paper, we present a new planar inductor model with magnetic layer. This equivalent circuit model takes into account the variation of the magnetic core permeability and the core losses versus frequency, the capacitive coupling between winding turns, the capacitive coupling between the external turn and the ground plane. In this model, we also consider the skin and the proximity effects. HFSS software is used for the simulation. In order to extract the different parameters of the equivalent circuit model, we have developed an optimization program. Inductors with one and two magnetic layers have been fabricated with thicknesses varying between 100 and 500 µm. A very good agreement between simulation results, experimental values and extracted parameters has been observed. The use of two magnetic layers allows to significantly increase the inductance value even with thin layers. [ABSTRACT FROM AUTHOR]

The piezoelectric excited millimetric sized cantilevers (PEMCs) have excellent advantages to be used in liquid environments for sensory applications since their quality factor decreases less, compared to micro and nano-sized ones. This makes PEMCs very useful for measuring density and viscosity of liquids. The principle is based on the fact that any environmental and/or structural changes lead to a shift in resonant frequency determined by measuring the electro-mechanical impedance of piezoelectric layer attached to cantilever. In this study, a novel measurement method instead of conventional chirp method is proposed, developed and implemented to measure, record and process the impedance signal of piezoelectric patches attached to PEMC using a data acquisition card. In this method, a discrete frequency sinusoidal signal is used to excite PEMC for density measurement in liquid for a wide range of frequency (<100 kHz). The conventional chirp method has disadvantages such as inaccuracy in measurements and underestimation of sensor sensitivity at low frequencies (<10 kHz) and needing a large amount of memory to store the measured data. Applying this novel measurement method, a high resolution of 0.01 Hz is achieved which allows detecting a liquid density change as small as 0.0072 kg/m. [ABSTRACT FROM AUTHOR]

In this paper, a nonlinear current-output digital to analog converter (DAC) employing a pseudo-exponential transconductance amplifier is presented. The proposed transconductance amplifier makes use of the code-dependent body-biasing to realize the exponential relationship of the output current to the input digital signal in the CMOS technology. A digital control unit is designed to provide a linearly code-dependent voltage to feed into the transconductance amplifier by charging a capacitor for a period determined by a counter which is loaded by the input digital code. The proposed DAC is simulated in a 180 nm standard CMOS technology. The accuracy of the exponential input-output characteristic is verified by the curve fitting of the simulation results where R-squared value of the fitted functions is greater than 0.999 in all process and temperature corners. The presented DAC consumed 79 μW in the worst-case. [ABSTRACT FROM AUTHOR]

In this paper a slew rate enhancement method using some extra paths in recycling folded cascode (RFC) amplifier is presented. The added transistors are in cut-off region in the small-signal operation and will be automatically turned on during slewing phase. Therefore, negative and positive slew rates are improved without increasing power dissipation in the small-signal operation. Simulation results in 90 nm CMOS technology show a 2.4 times enhancement in the average slew rate and a 69 % reduction in the settling time without affecting the gain bandwidth and power dissipation compared to the conventional RFC structure. [ABSTRACT FROM AUTHOR]

This paper is devoted to local multiple soft fault diagnosis of nonlinear DC analog CMOS circuits designed in nanometer technology. An algorithm is developed that allows estimating the values of a set of potentially faulty process parameters. It exploits two tests with the input nodes accessible for excitation and the output node accessible for measurement. One of the tests is used to find the parameter values. It leads to a system of nonlinear algebraic type equations that are not given in explicit analytical form and may be satisfied by several sets of the parameter values. To solve the system of the equations the Nelder-Mead optimization method is applied with the objective function properly modified during the computation process. Next the obtained solution, being a set of the parameter values, is validated using the other test. If the solution passes this test it is considered as the actual one. Otherwise, another solution is calculated and verified using the same approach. The developed diagnostic procedure has been implemented in DELPHI, whereas the required by the algorithm circuit analyses are performed using IsSPICE 4 and both environments have been joined together. For illustration three numerical examples are given. [ABSTRACT FROM AUTHOR]

Satisfiability modulo theories (SMT) is an area concerned with checking the satisfiability of logical formulas over one or more theories. SMT can be well tuned to solve several of the most intriguing problems in electronic design automation (EDA). Analog placers use physical constraints to automatically generate small sections of layout. The work presented in this paper shows that SMT solvers can be used for the automation of analog placement, given some physical constraints. We propose a tool that uses Microsoft Z3 SMT solver to find valid placement solutions for the given analog blocks. Accordingly, it generates multiple layouts that fulfill some given constraints and provides a variety of alternative layouts. The user has the option to choose one of the feasible solutions. The proposed system uses the quantifier-free linear real arithmetic (QFLRA), which makes the problem decidable. The proposed system is able to generate valid placement solutions for benchmarks. For benchmarks that have many constraints and few geometries, the proposed system achieves a speedup that is 10 times faster than other recently used approaches. [ABSTRACT FROM AUTHOR]

A low-voltage, low-power, low-area, wide-temperature-range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (−60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high-order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade-off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18-µm standard CMOS technology and occupies an area of 0.039 mm2. The proposed reference circuit is suitable for high-precision, low-energy-budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper presents an evolutionary approach to design CMOS Two-Stage Comparator (TSC) and CMOS Folded Cascode Operational Trans-conductance Amplifier (FCOTA) using simplex particle swarm optimization (Simplex-PSO) method. The simplex particle swarm optimization (Simplex-PSO) is a swarm intelligent based evolutionary computation method. Simplex-PSO is the hybridization of Nelder–Mead Simplex method (NMSM) and Particle Swarm Optimization (PSO) without the velocity term. The Simplex-PSO has fast optimizing capability and high computational precision for high-dimensionality functions. This work has focused on the optimization of the area, power and has improved all other performance parameters of the CMOS TSC and CMOS FCOTA with minimum computational time. The proposed Simplex-PSO based circuit optimization technique is relieved from the inherent drawbacks of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS). The simulation results prove that Simplex-PSO yields the optimized result with improved functionality. Simulation results obtained for CMOS TSC and CMOS FCOTA prove the effectiveness of the proposed Simplex-PSO method based approach over the reported DE, HS, and PSO in terms of convergence speed, design specifications and design objectives. The optimally designed TSC and FCOTA circuits, individually, occupy the least MOS areas and dissipate the least powers. The simulation plots and results are shown to have the improved performance parameters compared with those of other reported literature. Validation of the design is carried out by Cadence version 5 (IC 5.10.41) of TSMC 0.35 μm technology. [ABSTRACT FROM AUTHOR]

Due to the compl ex growth in very large scale integration circuits, the task of optimal analog integrated circuit design by hand is very difficult. Optimization is a time consuming process having many conflicting criteria and a wide range of design parameters. Characterization of complex tradeoffs between nonlinear objectives while assuring required specifications makes analog circuit design a tedious process. The design and optimization processes have to be automated with high accuracy. Evolutionary technique may be a proficient implement for automatic design of analog integrated circuits that has been one of the most challenging topics in VLSI design process. This paper presents a competent approach for optimal designs of two analog circuits, namely, complementary metal oxide semiconductor two-stage comparator with P-type metal oxide semiconductor input driver and n-channel input, folded-cascode operational amplifier. The evolutionary technique used is particle swarm optimization (PSO) with an aging leader and challenger (ALC-PSO). The main aim is to optimize the MOS transistors' sizes using ALC-PSO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. To exhibit the performance parameters of the circuits, simulation program with integrated circuit emphasis simulation has been carried out by using the optimal values of MOS transistor sizes and other design parameters. Simulation results demonstrate that design specifications are closely met and required functionalities are accommodated. The simulation results also show that the ALC-PSO is superior to the other algorithms in terms of MOS area, and performance parameters like gain, power dissipation, etc. for the examples considered. [ABSTRACT FROM AUTHOR]

This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1-bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885m2, which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument. [ABSTRACT FROM AUTHOR]

In applications for indoor illumination, light-emitting diode (LED) is widely used. The requirements for small volume, low cost and high reliability LED driver makes additional challenges. Conventional single stage flyback LED driver requires additional feedback components such as opto-coupler or auxiliary winding. These components take space on printed circuit board, reduce the reliability and may introduce interference into the feedback loop. A 2.7 W LED driver without opto-coupler or auxiliary winding is proposed. With novel demagnetizing time sampling method, the feedback circuit is fully integrated into the controller, leaving few off-chip components. The controller integrated circuit (IC) is fabricated in CSMC 0.8 μm 500 V BCD process to verify the proposed sampling method. A power MOS is also integrated into the controller IC to simplify the off-chip circuit further. A prototype of the driver is also built and optimized to reduce the volume into 1.6 × 2.4 × 1.4 cm. The experimental results show that the efficiency is above 72.75 % and the average output current variation is less than 5 % under universal input voltage. [ABSTRACT FROM AUTHOR]

This paper presents a current stimulator circuit that its output can be configured to generate the three most efficient current waveforms used in neural stimulation; rising exponential, falling exponential and rectangular. The stimulation amplitude range can be varied from 0 to 1 mA in a manner that each range can be divided into 16 steps by a 4 bit binary weighted digital to analog converter (DAC). The DAC features the maximum DNL and INL of 0.008 and 0.096 LSB respectively. Rising and falling exponential time constants are tunable from 13 to 106 $$\upmu$$ s. The approach for producing both rising and falling exponential currents is to apply a controllable rising and falling ramp voltage to the gate of the NMOS transistors which are biased to work in the subthreshold region while for the rectangular pulse, a constant subthreshold voltage is needed instead. The ramp generator used in exponential mode, employs a proposed low power 5 nA current source followed by a 3-bit current steering DAC. In the output stage, the stimuli current is buffered through the gain boosting technique which needs the maximum headroom voltage of 0.15 V. The DC output impedance is increased up to at least 24 M $$\Omega$$ . A simple electrode shortening is used for the charge balancing purpose at the end of the stimulation phases. The presented stimulator is designed and simulated in a 180nm CMOS technology and for the output driver, a HV 180 nm CMOS is used with the supply voltage equal to 3.3 V. The simulated power consumption of the proposed stimulator for one channel is 23.2 $$\upmu W$$ and the maximum achieved power efficiency is 94.7 $$\%$$ . [ABSTRACT FROM AUTHOR]

This paper aims to design a low-power and high-frequency divider in an integrated CMOS phase-locked loop. The proposed frequency divider is a two-step divider composed of an injection-locked frequency divider (ILFD) and a current-mode logic (CML) frequency divider. The ILFD has a structure similar to an LC cross-coupled oscillator to adjust the frequency alignment between the oscillator and the ILFD. The LC cross-coupled oscillator operates at 50 GHz, and the ILFD is supposed to provide a divide-by-2 (/2) operation. The CML frequency divider, which is used as the second-stage divider, is applied with an inductive peaking structure for a wide band with low power consumption. The proposed two-step frequency divider is designed with a 0.18 µm CMOS process. By varying the numbers of the ILFD and the CML divider, the characteristics of power consumption are also studied. Post-layout simulation shows that the /2 ILFD and the /128 CML frequency divider operate at an input frequency of 50 GHz, with power consumption of 37.8 mW, and results indicate a low-power two-step divider at high frequency. [ABSTRACT FROM AUTHOR]

This paper describes a compact transimpedance amplifier (TIA). Based on the principle of negative impedance (NI) circuit, the proposed TIA provides wide bandwidth and low noise. The schematics and characteristics of NI circuit have been explained. The inductor behavior is synthesized by gyrator-C circuit. The TIA is implemented in 180 nm RF MOS transistors in a HV CMOS technology with 1.8 V supply voltage technology. It reaches −3 dB bandwidth of 7 GHz and transimpedance gain of 54.3 dBΩ in the presence of a 50 fF photodiode capacitance. The simulated input referred noise current spectral density is $$5.9\;{\text{pA/}}\sqrt {\text{Hz}}$$ . The power consumption is 29 mW. The TIA occupies $$230\;\upmu {\text{m}} \times 45\;\upmu {\text{m}}$$ of area. [ABSTRACT FROM AUTHOR]