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Neuromorphic computing has emerged as a better alternative for developing next-generation artificial intelligent systems. Resistive Random Access Memory (RRAM) have been widely explored to represent the synaptic weights in artificial neural networks. Despite significant advances in device technology, precise modulation of conductance required for maintaining high accuracy remains a challenge. These devices suffer mainly from Cycle-to-Cycle and Device-to-Device variations, which make it even more difficult to implement reliable neuromorphic systems. To address these issues, we propose an RRAM-based synaptic architecture with continuous sensing and feedback scheme to stop RRAM programming when the required conductance is achieved. The weight change mechanism is incorporated in the proposed architecture enabling it to be used for on-chip training. Unlike contemporary architectures, which require a precise gap between different resistive states, the proposed feedback scheme to stop RESET operation provides flexibility in choosing resistive states. Thus, employing the proposed architecture, 4-bits/cell can be programmed simultaneously, which is at par with the existing start-of-the-art designs. The proposed architecture is tolerant to 22% variation in RRAM resistance. The minimal resistance margin between two resistive states is $4\ K\Omega$ , with an average energy consumption of $0.1\ pJ/cell$ and an average latency of $1.07\, \mu s$. [ABSTRACT FROM AUTHOR]

This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current ($I_{d}$) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current ($I_{BL}$) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks. [ABSTRACT FROM AUTHOR]

The amount of data processed in the cloud, the development of Internet-of-Things (IoT) applications, and growing data privacy concerns force the transition from cloud-based to edge-based processing. Limited energy and computational resources on edge push the transition from traditional von Neumann architectures to In-memory Computing (IMC), especially for machine learning and neural network applications. Network compression techniques are applied to implement a neural network on limited hardware resources. Quantization is one of the most efficient network compression techniques allowing to reduce the memory footprint, latency, and energy consumption. This article provides a comprehensive review of IMC-based Quantized Neural Networks (QNN) and links software-based quantization approaches to IMC hardware implementation. Moreover, open challenges, QNN design requirements, recommendations, and perspectives along with an IMC-based QNN hardware roadmap are provided. [ABSTRACT FROM AUTHOR]

Big data applications involved with neural networks requires frequent data transfer between memory and processing elements and thus, take a significant portion of energy. One possible method is to realize logic operations inside the memory, often known as in-memory computing. The memristor employed in a crossbar can also conduct logic operations, making it a promising candidate for enabling such designs. In-memory computing can vastly improve speed efficiency by significantly reducing memory access time and energy. Therefore, efficient operations inside the memory are crucial for data-intensive applications. This article presents two high-speed adders in memristive technology, which are derived using IMPLY-based logic operations and can be implemented on a crossbar architecture for in-memory computing. One is a carry select adder, which uses efficient ripple carry adders and multiplexers. While the other is a conditional carry adder, designed using a modified half adder and multiplexers. An IMPLY-based multiplexer and modified half adder are proposed as part of these adders. A modified half adder calculates the sum of two inputs and two carry outputs for various carry inputs. Compared to conventional adder designs, the speed of these two adders has been significantly enhanced. In particular, the proposed 32-bit Carry Select Adder and Conditional Carry Adder take 123 and 90 computational steps, respectively. The proposed adders have improved the speed by 30% and 49%, respectively, compared to the best-existing adder in IMPLY. Further, this article presents computational steps and the number of memristors required for $n$ -bit adders. The proposed circuits were simulated using the VTEAM model, and energy consumed for each adder is calculated from the simulations. [ABSTRACT FROM AUTHOR]

This work proposes a 10T SRAM-based in-memory computation (IMC) architecture that can be configured to perform linear multiply-and-accumulate (MAC) operations and high-throughput XNOR-and-accumulate (XAC) operations. The IMC-MAC operation is performed by using the proposed scaled-voltage-based pulse count modulation (PCM) technique, which improves the linearity and signal margin of the MAC operation. The IMC-XAC operation is performed by using the proposed single capacitor discharge (SCD) approach with various advantages such as no deterministic error in XAC output, low latency, and less variation compared to the traditional charge sharing (TCS)-based XAC operation. The post-layout simulations of the proposed IMC architecture in a 65-nm CMOS process shows that the IMC architecture achieves a signal margin of 44.3 mV using the proposed scaled-voltage-based PCM approach in IMC-MAC mode whereas 37% less variation using the proposed SCD approach in IMC-XAC mode. In IMC-MAC mode, we achieve a 54.6 GOPS, 273 TOPS/W, and 98.67%/88.72% classification accuracy on MNIST/CIFAR-10 dataset using the convolution neural network (CNN)/ResNet20 algorithm. In IMC-XAC mode, we achieve a 3276.8 GOPS, 1092.2 TOPS/W, and 97.12% classification accuracy on the MNIST dataset using the binary neural network (BNN) algorithm. [ABSTRACT FROM AUTHOR]

Computer vision (CV) algorithms have been extensively used for a myriad of applications nowadays. As the multimedia data are generally well-formatted and regular, it is beneficial to leverage the massive parallel processing power of the underlying platform to improve the performances of CV algorithms. Single Instruction Multiple Data (SIMD) instructions, capable of conducting the same operation on multiple data items in a single instruction, are extensively employed to improve the efficiency of CV algorithms. In this paper, we evaluate the power and effectiveness of RISC-V vector extension (RV-V) on typical CV algorithms, such as Gray Scale, Mean Filter, and Edge Detection. By our examinations, we show that compared with the baseline OpenCV implementation using scalar instructions, the equivalent implementations using the RV-V (version 0.8) can reduce the instruction count of the same CV algorithm up to 24x, when processing the same input images. Whereas, the actual performances improvement measured by the cycle counts is highly related with the specific implementation of the underlying RV-V co-processor. In our evaluation, by using the vector co-processor (with eight execution lanes) of Xuantie C906, vector-version CV algorithms averagely exhibit up to 2.98x performances speedups compared with their scalar counterparts. [ABSTRACT FROM AUTHOR]

Space electronic system is the ＆quot;brain＆quot; of aerospace engineering models and the core fi eld of competitive development of major countries around the world.As the most core device in space electronic system, space processor directly aff ects the performance, reliability and safety of aerospace models.On the basis of brief introduced of space electronic systems, fi rstly, the development status of foreign space processors was analyzed, and then the development roadmap of space processors such as SPARC, PowerPC, ARM, RISC V, etc were combed and formed.The development process was summarized into three stages:initial stage, development stage and new stage, considered architecture and performance parameters.Finally, the development trend of space processors in the future was summarized as ＆quot;fi ve modernizations＆quot;: micro system, commercialization, intelligent, ecological and cloud enabled.

Belady’s algorithm is widely known as an optimal cache replacement policy. It has been the foundation of numerous recent studies on cache replacement policies, and most studies assume this as an upper limit. Despite its widespread adoption, we discovered opportunities to unleash the headroom by addressing cache access types and implementing cache bypass. In this study, we propose Stormbird, a cache replacement policy that synergistically integrates the extensions of Belady’s algorithm and the power of reinforcement learning. Reinforcement learning is well-suited for cache replacement policy problems owing to its ability to interact dynamically with the environment, adapt to changing access patterns, and optimize the maximum cumulative rewards. Stormbird utilizes several selected features from the reinforcement learning model to enhance the instructions per cycle efficiency while maintaining a low hardware area overhead. Furthermore, it considers cache access types and integrates dynamic set dueling techniques to improve the cache performance. For 2 MB last-level cache per core, Stormbird achieves an average instructions per cycle improvement of 0.13% over the previous state-of-the-art on a single-core system and 0.02% on a four-core system while simultaneously reducing hardware overhead by 62.5%. Stormbird incurs a low hardware overhead of only 10.5 KB for 2 MB last-level cache and can be implemented without using program counter values.

In this paper, we present the Prism Bridge, a soft IP core developed to bridge FPGA-MPSoC systems using high-speed serial links. Considering the current trend of ubiquitous serial transceivers with staggeringly increasing line rates, minimizing overhead and maximizing data throughput becomes paramount. Hence, our main design goal is to maximize bandwidth utilization for AXI data, which we realize through an advanced packetization mechanism. We give an overview of the Prism Bridge’s design and analyze its half-duplex bandwidth utilization. Additionally, we discuss the results of the experiments we conducted to assess its real-world performance, including measurements of throughput and latency of various combinations of line rates, link-layer cores, and bridge cores. Using a serial link with a 16.375 Gbit/s line rate, the Prism Bridge with an advanced packetizing mechanism achieved an AXI write throughput of 1368.81 MiB/s and an AXI read throughput of 1376.61 MiB/s, an increase of 46.19% and 45.85%, respectively, compared with the de-facto industry-standard core. The advanced packetization mechanism had negligible impact on latency but required 69.14%–73.91% more LUTs and 33.62%–36.19% more flip-flops. We conclude that for most designs that support inter-chip AXI transactions and will not be limited to short transaction lengths, the higher data throughput of the Prism Bridge with an advanced packetization mechanism is worth its cost in additional logic resource utilization.

Fast and resource-efficient inference in artificial neural networks (ANNs) is of utmost importance and drives many new developments in the area of new hardware architectures, e.g., by means of systolic arrays or algorithmic optimization such as pruning. In this paper, we present a novel method for lowering the computation effort for ANN inference utilizing ideas from information theory. Weight matrices are sliced into submatrices of logarithmic aspect ratios. These slices are then factorized. This reduces the number of required computations without compromising on fully parallel processing. We create a new hardware architecture for this dedicated purpose. We also provide a tool to map these sliced and factorized matrices efficiently to reconfigurable hardware. By comparing to the state of the art FPGA implementations, we can prove our claim by lowering hardware resources measured in look-up-tables (LUTs) by a factor of three to six. Our method does not rely on any particular property of the weight matrices of the ANN. It works for the general task of multiplying an input vector with a constant matrix and is also suitable for digital signal processing beyond ANNs.

Abstract This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics.

Through the research of MapReduce programming framework of cloud computing, the current MapReduce program only solves specific problems, and there is no design experience or design feature summary of MapReduce program, let alone formal description and experience inheritance and application of knowledge base. In order to solve the problem of intelligent cloud computing program, a general MapReduce program generation method is designed. This paper proposes the architecture of intelligent cloud computing by studying AORBCO model and combining cloud computing technology. According to the behavior control mechanism in AORBCO model, a program generation method of MapReduce in intelligent cloud computing is proposed. This method will extract entity information in input data set and entity information in knowledge base in intelligent cloud computing for similarity calculation, and extract the entity in the top order as key key-value pair information in intelligent cloud computing judgment data set. The data processing types are divided, and then aligned with each specific MapReduce capability, and the MapReduce program generation experiment is verified in the AORBCO model development platform. The experiment shows that the complexity of big data MapReduce program code is simplified, and the generated code execution efficiency is good. [ABSTRACT FROM AUTHOR]

Modern computer architectures are complex, containing numerous components that can unintentionally reveal system operating properties. Defensive security professionals seek to minimize this kind of exposure while adversaries can leverage the data to attain an advantage. This article presents a novel covert interrogator program technique using light-weight sensor programs to target integer, floating point, and memory units within a computer's architecture to collect data that can be used to match a running program to a known set of programs with up to 100% accuracy under simultaneous multithreading conditions. This technique is applicable to a broad spectrum of architectural components, does not rely on specific vulnerabilities, nor requires elevated privileges. Furthermore, this research demonstrates the technique in a system with operating system containers intended to provide isolation guarantees that limit a user's ability to observe the activity of other users. In essence, this research exploits observable noise that is present whenever a program executes on a modern computer. This article presents interrogator program design considerations, a machine learning approach to identify models with high classification accuracy, and measures the effectiveness of the approach under a variety of program execution scenarios. [ABSTRACT FROM AUTHOR]

For the last two decades, artificial neural networks (ANNs) of the third generation, also known as spiking neural networks (SNN), have remained a subject of interest for researchers. A significant difficulty for the practical application of SNNs is their poor suitability for von Neumann computer architecture, so many researchers are currently focusing on the development of alternative hardware. Nevertheless, today several experimental libraries implementing SNNs for conventional computers are available. In this paper, using the RCNet library, we compare the performance of reservoir computing architectures based on artificial and spiking neural networks. We explicitly show that, despite the higher execution time, SNNs can demonstrate outstanding classification accuracy in the case of complicated datasets, such as data from industrial sensors used for the fault detection of bearings and gears. For one of the test problems, namely, ball bearing diagnosis using an accelerometer, the accuracy of the classification using reservoir SNN almost reached 100%, while the reservoir ANN was able to achieve recognition accuracy up to only 61%. The results of the study clearly demonstrate the superiority and benefits of SNN classificators. [ABSTRACT FROM AUTHOR]

The past two decades have seen an increase in the deployment of photovoltaic installations as nations around the world try to play their part in dampening the impacts of global warming. The manufacturing of solar cells can be defined as a rigorous process starting with silicon extraction. The increase in demand has multiple implications for manual quality inspection. With automated inspection as the ultimate goal, researchers are actively experimenting with convolutional neural network architectures. This review presents an overview of the electroluminescence image-extraction process, conventional image-processing techniques deployed for solar cell defect detection, arising challenges, the present landscape shifting towards computer vision architectures, and emerging trends. [ABSTRACT FROM AUTHOR]

The object of research is the process of automatic control of the redundant structure of the vessel’s executive devices for extreme rotation in the yaw channel. Traditionally, redundant structures have been used to improve the reliability of automated control systems and the maneuverability of vessels. At the same time, control redundancy can also be used to optimize control processes, thereby reducing fuel consumption, increasing control forces and moments, and reducing the time required to perform operations. This allows gaining advantages in movement over vessels not equipped with optimization modules. The paper considers the optimal management of the redundant structure of an offshore vessel, which ensures the rotational movement of the vessel around the center of rotation with the maximum angular velocity. As well as simultaneous maintenance of a given position or movement in the longitudinal and lateral channel, taking into account control restrictions. This problem is reduced to a nonlinear optimization problem with nonlinear and linear control constraints. The method, algorithmic and software of the module of extreme rotation of the vessel with a redundant structure of executive devices have been developed. The workability and efficiency of the developed method, algorithmic and software are verified by mathematical modeling in the closed circuit «Control Object – Control System». The results of the conducted experiment showed that the use of optimal control allows, in comparison with traditional methods of splitting controls, to increase the control moment and angular speed of rotation by 1.5–2 times. The obtained opportunities are explained by the use of a mathematical model of the redundant control structure and the optimization procedure for calculating optimal controls in the on-board computer of the automated system. The developed method can be used on vessels, provided it is integrated into the existing automated system of the on-board computer with an open architecture, to increase the capabilities of automatic traffic control. [ABSTRACT FROM AUTHOR]

Due to the ever‐increasing computing requirements of modern applications, supercomputers are at the centre of attraction as a platform for high‐performance computing. Although various features and indicators for testing and evaluating supercomputers are proposed in the literature, a comprehensive feature set to guide designers in comparing supercomputers and selecting an appropriate choice is not provided. Here, an integrated feature‐based taxonomy comprised of seven indicator groups including passive infrastructure, hardware, software, support and maintenance, service, business, and security features is proposed. Also, a case study using our proposed framework is provided and a comparison between some commercial and research supercomputers including Fugaku's ideal supercomputer, Sharif supercomputer, Aramco supercomputer, and ITU supercomputer is presented. Moreover, here, the authors' proposed method is compared with the Top500 method, which shows that the authors' proposed method facilitates the ranking, comparison, and selection of the appropriate supercomputer in various fields by considering various aspects of design and implementation. The ranking results show that Aramco supercomputer, ITU supercomputer, and Sharif supercomputer have 65.9%, 57.6%, and 48.2% of ideal supercomputer points, respectively. [ABSTRACT FROM AUTHOR]

Transient execution attacks such as Spectre and Meltdown exploit speculative execution in modern microprocessors to leak information via cache side‐channels. Software solutions to defend against many transient execution attacks employ the lfence serialising instruction, which does not allow instructions that come after the lfence to execute out‐of‐order with respect to instructions that come before the lfence. However, errors and Trojans in the hardware implementation of lfence can be exploited to compromise the software mitigations that use lfence. The aforementioned security gap has not been identified and addressed previously. The authors provide a formal method solution that addresses the verification of lfence hardware implementation. The authors also show how hardware Trojans can be designed to circumvent lfence and demonstrate that their verification approach will flag such Trojans as well. The authors have demonstrated the efficacy of our approach using RSD, which is an open source RISC‐V based superscalar out‐of‐order processor. [ABSTRACT FROM AUTHOR]

Due to the continuous growth of hardware neuromorphic systems, the need for high-speed, low-power, and energy-efficient computer architectures is increasing. Memristors-based neural networks are a promising solution for low-power neuromorphic systems. Spiking neural networks (SNNs) have been considered the optimal hardware implementation of these systems. Previous studies of SNNs rely on complex circuit to implement in situ bio-plausible STDP learning using memristors, which is computationally challenging. In this paper, we propose an SNN that performs both in situ learning and inference using a new efficient programming technique. Our interest lies in applying the winner-takes-all (WTA) mechanism in the SNN architecture used with recurrently connected neurons, allowing real-time processing of patterns. We provide a programming circuit that enables better weight modulation with less power consumption and less space occupation, using a generalized enhanced memristor model (EGM). The proposed programming circuit is connected to leaky integrate-and-fire (LIF) neurons included in a crossbar architecture to perform recognition task. The simulation results not only prove the correctness of the design, but also offer an efficient implementation in terms of area, energy, accuracy, as well as the ability to classify 40,000 images per second. [ABSTRACT FROM AUTHOR]

Parallel computing has become a crucial topic in the concern of computer science and also it is revealed to be critical when researching in high performance. The evolution of computer architectures towards an improved number of nodes, where parallelism could be the approach to option for speeding up an algorithm within the last few decades. The combination of processing units build a model of computation (circuits) has gained an essential place in the area of high performance computing (HPC) due to its configuration and considerable processing supremacy that is parallel, series, etc.... In this paper, we study the idea of parallel computing, and its programming models and also explore some theoretical and technical concepts which can be often needed to understand the Interconnection network. In particular, we show how this technology is new in assisting the field of computational physics, especially when the issue is data parallel. In this paper firstly we convert the graphical model of perfect difference network into circuit diagram then convert circuit diagram into switching function, then simplify it and redraw the equivalent network. [ABSTRACT FROM AUTHOR]

Neural architecture search (NAS) has been widely studied to design high-performance network architectures automatically. However, existing approaches require more search time and substantial resource consumption due to their intensive architecture evaluations. Moreover, recently developed NAS algorithms are noncompetitive when combining multiple competing and conflicting objectives, e.g., the test accuracy and the number of parameters. In this paper, a low-cost NAS (LoNAS) method is proposed to address these problems. First, a variable-architecture encoding strategy based on a novel Reg Block is designed to construct high accuracy network architectures with few parameters. Second, a training-free proxy based on the neural tangent kernel (NTK) is proposed to accelerate the search process efficiently. Finally, a three-stage evolutionary algorithm (EA) based on multiple-criteria environmental selection and a set of block-based mutation operators are designed to balance exploration and exploitation better. The experimental results show that LoNAS finds network architectures with competitive performance compared to the state-of-the-art architectures in test accuracy and the number of parameters. Moreover, LoNAS uses less search time and fewer computational resources, consuming only 0.02 GPU Days with one GPU on CIFAR-10 and CIFAR-100. Furthermore, the architectures found by LoNAS on CIFAR-10 and CIFAR-100 exhibit good transferability to ImageNet-16-120, with the test accuracy surpassing that of the state-of-the-art network architectures. [ABSTRACT FROM AUTHOR]

The article presents an overview of several studies in the field of Brain–Computer Interfaces (BCIs), the requirements for the architecture of such promising devices, as well as multi-modal BCI for drone control in a smart-city environment. Distinctive features of the proposed solution are the simplicity of the architecture (the use of only one smartphone for both receiving and processing bio-signals from the headset and transmitting commands to the drone), an open-source software solution for signal processing, generating, and sending commands to the unmanned aerial vehicle (UAV), as well as multimodality of the BCI (the use of both electroencephalographic (EEG) and electrooculographic (EOG) signals of the operator). For bio-signal acquisition, we used the NeuroSky Mindwave Mobile 2 headset, which is connected to an Android-based smartphone via Bluetooth. The developed Android application (Tello NeuroSky) processes signals from the headset and generates and transmits commands to the DJI Tello UAV via Wi-Fi. The decrease (depression) and increase of α - and β -rhythms of the brain, as well as EOG signals that occur during blinking were the triggers for UAV commands. The developed software allows the manual setting of the minimum, maximum and threshold values for the processed bio-signals. The following commands for the UAV were implemented: take-off, landing, forward movement, and backwards movement. Two threads of the smartphone's central processing unit (CPU) were utilized when processing signals in the software to increase the performance: for signal processing (1-D Daubechies 2 (db2) wavelet transform) and updating data on the diagrams, and for generating and transmitting commands to the drone. [ABSTRACT FROM AUTHOR]

This article discusses an approach to the development of large-scale cognitive cyber-physical systems characterized by a high level of structural, functional and architectural dynamics. The main idea of the proposed approach is the use of several modern paradigms to build cyber-physical systems, such as continuous architecture, agile architecture, digital twins and digital threads. A three-level model of a cognitive cyber-physical system is proposed. In order to ensure the required level of flexibility of the system, such possibility should be laid at earlier stages of the life cycle, i.e., at the development stage. At the upper level, the system is described in terms of a continuous architecture; at the middle level, the system is represented as a system with agile architecture, which is described as a multi-level relatively finite automaton, and at the lower level, structural and functional models are used that illustrate the system in the process of functioning. This article provides examples of using the proposed approach. [ABSTRACT FROM AUTHOR]

The problem of resource-saving scheduling in a fog environment is considered in this paper. The objective function of the problem in question presupposes the fog nodes' reliability function maximizing. Therefore, to create a schedule, the following is required: the history of the fog devices' state changes and the search space, which consists of preselected nodes of the cloud-fog broker neighbourhood. The obvious approach to providing the scheduler with this information is to poll the fog nodes, yet this can consume the unacceptable time because of the QoS requirements. In this paper, the system architecture and general methods for efficient resource-saving scheduling is presented. The system is based on distributed ledger element usage, which provides the nodes with the proper awareness about the surroundings. The usage of the distributed ledger allows not only for the creation of the resource-saving schedule but also the reduction of the scheduling problem-solving time, which frees addition time that can be used for the solving of user tasks. The latter also affects the overall resource-saving via reliability. The novelty of this paper consists in the development of the hybrid ledger-based system, which integrates and arranges the elements of various ledger types to solve the newly formulated problem. [ABSTRACT FROM AUTHOR]

Given the need for efficient high-performance computing, computer architectures combining central processing units (CPUs), graphics processing units (GPUs), and field-programmable gate arrays (FPGAs) are currently prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with the potential of multitenancy, it is essential to understand and investigate how the security vulnerabilities of individual components may affect the system as a whole. In this work, we provide a survey on the electrical-level attacks on CPUs, FPGAs, and GPUs. Additionally, we discuss whether these attacks can extend to heterogeneous systems and highlight open research directions for ensuring the security of heterogeneous computing systems in the future. [ABSTRACT FROM AUTHOR]

It has been a long time that computer architecture and systems are optimized for efficient execution of machine learning (ML) models. Now, it is time to reconsider the relationship between ML and systems and let ML transform the way that computer architecture and systems are designed. This embraces a twofold meaning: improvement of designers' productivity and completion of the virtuous cycle. In this article, we present a comprehensive review of the work that applies ML for computer architecture and system design. First, we perform a high-level taxonomy by considering the typical role that ML techniques take in architecture/system design, i.e., either for fast predictive modeling or as the design methodology. Then, we summarize the common problems in computer architecture/system design that can be solved by ML techniques and the typical ML techniques employed to resolve each of them. In addition to emphasis on computer architecture in a narrow sense, we adopt the concept that data centers can be recognized as warehouse-scale computers; sketchy discussions are provided in adjacent computer systems, such as code generation and compiler; we also give attention to how ML techniques can aid and transform design automation. We further provide a future vision of opportunities and potential directions and envision that applying ML for computer architecture and systems would thrive in the community. [ABSTRACT FROM AUTHOR]

Ternary optical computer（TOC） is a new architecture computer with a large number of processor bits and the characteristics of easily scaling, reconfigurable bit functions, and groupable bits. It has great potential for fast processing of massive or complex data. However, it is still in the early stage of application development exploration. To expand its application, this paper proposed a TOCSim design scheme for a simulator based on a ternary optical computer architecture. It simulates the TOC operation process in the form of software and implements its prototype on an ordinary PC. These operation processes mainly include the TOC processor reconfiguration strategy, processor bit allocation strategy, intermediate result decoding, and computing effect simulation. A comparison of the simulation effect graphs derived from the simulator proposed in this paper between the light graphs of the operation results on the TOC prototype shows that the design scheme of the simulator is correct and feasible. [ABSTRACT FROM AUTHOR]

Using Artificial intelligence to solve semi- or ill-structured problems using an algorithm that deploys techno-scientific human experts' approach (Expert System) is a widely used solution. Expert system (ES) provides a programmable methodology solution through instructions provided by intelligence based on human experts. The expert system was used in this study to validate the decision process of the cloud-native architecture portability framework. The cloud-native architecture portability framework is developed to support decision-makers in organizations in making the right decision on porting or migrating either legacy or cloud-based data or applications to cloud-native architecture. The framework, designed and developed from research and expert contributions, was implemented in an expert system to examine its validity. The framework was evaluated through data collected from questionnaires, and the findings show that most respondents agreed with the importance of the framework. Then the evaluated framework was then developed into an expert system to provide a clear path for the stakeholders and the task and usercentred view of the framework. The usability of the designed expert system through the use of the ESBUILDER shell also shows the usefulness of artificial intelligence in decision-making and information presentation simplification through technology. [ABSTRACT FROM AUTHOR]

With the flourishing development of deep learning (DL) and the convolution neural network (CNN), electroencephalogram-based (EEG) emotion recognition is occupying an increasingly crucial part in the field of brain-computer interface (BCI). However, currently employed architectures have mostly been designed manually by human experts, which is a time-consuming and labor-intensive process. In this paper, we proposed a novel neural architecture search (NAS) framework based on reinforcement learning (RL) for EEG-based emotion recognition, which can automatically design network architectures. The proposed NAS mainly contains three parts: search strategy, search space, and evaluation strategy. During the search process, a recurrent network (RNN) controller is used to select the optimal network structure in the search space. We trained the controller with RL to maximize the expected reward of the generated models on a validation set and force parameter sharing among the models. We evaluated the performance of NAS on the DEAP and DREAMER dataset. On the DEAP dataset, the average accuracies reached 97.94%, 97.74%, and 97.82% on arousal, valence, and dominance respectively. On the DREAMER dataset, average accuracies reached 96.62%, 96.29% and 96.61% on arousal, valence, and dominance, respectively. The experimental results demonstrated that the proposed NAS outperforms the state-of-the-art CNN-based methods. [ABSTRACT FROM AUTHOR]

This article investigates classification of emotions from full-body movements by using a novel Convolutional Neural Network-based architecture. The model is composed of two shallow networks processing in parallel when the 8-bit RGB images obtained from time intervals of 3D-positional data are the inputs. One network performs a coarse-grained modelling in the time domain while the other one applies a fine-grained modelling. We show that combining different temporal scales into a single architecture improves the classification results of a dataset composed of short excerpts of the performances of professional dancers who interpreted four affective states: anger, happiness, sadness, and insecurity. Additionally, we investigate the effect of data chunk duration, overlapping, the size of the input images and the contribution of several data augmentation strategies for our proposed method. Better recognition results were obtained when the duration of a data chunk was longer, and this was further improved by applying balanced data augmentation. Moreover, we test our method on other existing motion capture datasets and compare the results with prior art. In all experiments, our results surpassed the state-of-the-art approaches, showing that this method generalizes across diverse settings and contexts. [ABSTRACT FROM AUTHOR]

With rapid development and application of artificial intelligence and block chain, the requirement of information and data security is also increased, in which the public-key cryptography, such as Rivest-Shamir-Adleman (RSA) cryptography, plays a significant role. Modular exponentiation is fundamental in computer arithmetic and is widely applied in cryptography, such as ElGamal cryptography, Diffie–Hellman key exchange protocol, and RSA cryptography. The implementation of modular exponentiation in a residue number system leads to high parallelism in computation and has been applied in many hardware architectures. While most residue number system (RNS)-based architectures utilize RNS Montgomery algorithm with two residue number systems, the recent modular multiplication algorithm with sum residues performs modular reduction in only one residue number system with about the same parallelism. In this work, it is shown that the high-performance modular exponentiation and RSA cryptography can be implemented in RNS. Both the algorithm and architecture are improved to achieve high performance with extra area overheads, where a 1024-bit modular exponentiation can be completed in 0.567 ms in Xilinx XC6VLX195t-3 platform, costing 26489 slices, 87357 LUTs, 363 dedicated multipilers of $18 \times 18$ bits, and 65 block RAMs. [ABSTRACT FROM AUTHOR]

Medical devices (MDs) have been designed for monitoring the parameters of patients in many sectors. Nonetheless, despite being high-performing and reliable, they often turn out to be expensive and intrusive. In addition, MDs are almost exclusively used in controlled, hospital-based environments. Paving a path of technological innovation in the clinical field, a very active line of research is currently dealing with the possibility to rely on non-medical-graded low-cost devices, to develop unattended telemedicine (TM) solutions aimed at non-invasively gathering data, signals, and images. In this article, a TM solution is proposed for monitoring the heart rate (HR) of patients during sleep. A remote patient monitoring system (RPMS) featuring a smart belt equipped with pressure sensors for ballistocardiogram (BCG) signals sampling was deployed. A field trial was then conducted over a 2-month period on 24 volunteers, who also agreed to wear a finger pulse oximeter capable of producing a photoplethysmography (PPG) signal as the gold standard, to examine the feasibility of the solution via the estimation of HR values from the collected BCG signals. For this purpose, two of the highest-performing approaches for HR estimation from BCG signals, one algorithmic and the other based on a convolutional neural network (CNN), were retrieved from the literature and updated for a TM-related use case. Finally, HR estimation performances were assessed in terms of patient-wise mean absolute error (MAE). Results retrieved from the literature (controlled environment) outperformed those achieved in the experimentation (TM environment) by 29% (MAE = 4.24 vs. 5.46, algorithmic approach) and 52% (MAE = 2.32 vs. 3.54, CNN-based approach), respectively. Nonetheless, a low packet loss ratio, restrained elaboration time of the collected biomedical big data, low-cost deployment, and positive feedback from the users, demonstrate the robustness, reliability, and applicability of the proposed TM solution. In light of this, further steps will be planned to fulfill new targets, such as evaluation of respiratory rate (RR), and pattern assessment of the movement of the participants overnight.