842 results on '"Yu, Shimeng"'
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202. Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning
203. Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator
204. A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure
205. First Experimental Demonstration of Robust HZO/β-Ga₂O₃ Ferroelectric Field-Effect Transistors as Synaptic Devices for Artificial Intelligence Applications in a High-Temperature Environment
206. A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source
207. A wearable sensor vest for social humanoid robots with GPGPU, IoT, and modular software architecture
208. Local Epitaxial Templating Effects in Ferroelectric and Antiferroelectric ZrO2.
209. Three-dimensional (3D) Non-volatile SRAM with IWO Transistor and HZO Ferroelectric Capacitor
210. Variability Analysis for Ferroelectric Field-Effect Transistors
211. Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security
212. Differential charge boost in hysteretic ferroelectric–dielectric heterostructure capacitors at steady state
213. Extraction of Preisach Model Parameters for Fluorite-Structure Ferroelectrics and Antiferroelectrics
214. Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing
215. Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine
216. Technological Design of 3D NAND-Based Compute-in-Memory Architecture for GB-Scale Deep Neural Network
217. A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator
218. Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM
219. A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training
220. Ferroelectric Tunnel Junction Based Crossbar Array Design for Neuro-Inspired Computing
221. A Ferroelectric-based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Accelerators
222. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
223. Variability Study of Ferroelectric Field-Effect Transistors Towards 7nm Technology Node
224. Metal Oxide Resistive Switching Memory
225. Characterizing HfO2-Based Ferroelectric Tunnel Junction in Cryogenic Temperature
226. Characterization and Modeling of the Conduction and Switching Mechanisms of HfOx Based RRAM
227. Benchmarking Monolithic 3D Integration for Compute-in-Memory Accelerators: Overcoming ADC Bottlenecks and Maintaining Scalability to 7nm or Beyond
228. Interplay of Switching Characteristics, Cycling Endurance and Multilevel Retention of Ferroelectric Capacitor
229. Thermal Modeling of 3D Polylithic Integration and Implications on BEOL RRAM Performance
230. Depolarization Field Induced Instability of Polarization States in HfO2 Based Ferroelectric FET
231. Cryogenic Benchmarks of Embedded Memory Technologies for Recurrent Neural Network based Quantum Error Correction
232. (Invited) Ferroelectric Transistors for Synaptic Devices: Challenges and Prospects
233. Ferroelectric Transistors for Synaptic Devices: Challenges and Prospects
234. XOR-CIM
235. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference
236. Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine
237. Direct comparison of ferroelectric properties in Hf0.5Zr0.5O2 between thermal and plasma-enhanced atomic layer deposition
238. Exploring argon plasma effect on ferroelectric Hf0.5Zr0.5O2 thin film atomic layer deposition
239. MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture
240. High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS
241. A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out
242. Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine
243. Impact of Random Phase Distribution in 3D Vertical NAND Architecture of Ferroelectric Transistors on In-Memory Computing
244. Investigating Ferroelectric Minor Loop Dynamics and History Effect—Part I: Device Characterization
245. Investigating Ferroelectric Minor Loop Dynamics and History Effect—Part II: Physical Modeling and Impact on Neural Network Training
246. Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint
247. Non-volatile, small-signal capacitance in ferroelectric capacitors
248. 8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator
249. Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses
250. Compute-in-Memory for AI: From Inference to Training
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