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In this letter, comprehensive static and dynamic electrical parameter degradations of p-GaN gate high electron mobility transistor (HEMT) under repetitive short-circuit (SC) stresses are presented. Meanwhile, the mechanisms behind those degradations are first distinguished. The results indicate that both the gate region and the access region are damaged by the SC stresses, dominating the shifts of electrical parameters. Moreover, a method by modeling the output capacitance is proposed to characterize damages in access region. Finally, the switching characteristics after the stresses are investigated, it is found that the switching speed benefits from the increase in the gate leakage current. Considering the aging of p-GaN HEMT under long-term operation conditions, all the damages brought by repetitive SC stresses should be eliminated to prevent the failure of p-GaN gate and the increase in conduction loss.

This letter presents a novel ultraviolet photon counting system based on a SiC SPAD array. The detector is made of 4H-SiC with a fairly low dark current in pA level and the array size is $1\times 128$ . In order to reduce the influence of dark count on image quality, this letter proposes an adaptive sampling readout circuit system, which can automatically adjust the SPAD hold-off time according to the photon density of the applications. Aiming at the nonuniform breakdown voltage of SPADs in a linear array, an adjustable bias voltage circuit is adopted to realize the accurate adjustment of pixel SPAD’s bias voltage. The ROIC is taped out in TSMC 0.18 $\mu {\mathrm{ m}}$ standard CMOS process and connected to the SPAD array by a gold bonding package. Based on the self-developed imaging system, UV photon counting imaging and deep violet- visible light fusion imaging are realized for the first time.

In this article, a new freewheeling circuit with a junction field-effect transistor (JFET) structure is developed to replace the traditional high voltage diode for freewheeling in the high voltage monolithic IC for the first time. The JFET structure has its pinch -off voltage lower than 40 V, and it can sustain the reverse voltage higher than 500 V in off -state. Adopting the new freewheeling circuit, the reverse recovery charge (QRR) and the peak reverse recovery current (IRRM) is decreased boffy about 89.5% and 33.6%, respectively, when the load current is 0.5 A. Based on the proposed freewheeling circuit, a deadtime control circuit is also developed in this article. By employing that control circuit, it is no need to detect the output signal state of the counter channel before controlling the deadtime, therefore the deadtime could be designed as small as possible to decrease the freewheeling loss. In this article, the high voltage monolithic IC is implemented by thick layer silicon on insulator technology. All the new devices and circuits are compatible with the technology for the traditional monolithic IC without any additional process.

A silicon-on-insulator (SOI) lateral diffused metal-oxide semiconductor (LDMOS) with potential modulation plates (PMPs) and deep-oxide trenches (DOTs) is proposed and studied through TCAD simulations, which aims to enhance the electron mobility and improve the ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ). The proposed SOI LDMOS consists of a conduction cell and an auxiliary cell. The surface electric potential in the conduction cell can be modulated by PMPs in both the ON-state and the OFF-state. In the ON-state, the gate voltage ( ${V}_{G}$ ) is delivered to the auxiliary cell and can be fully sustained by P-/N-well junction. Then, electrodes ( ${P}1$ – ${P}15$ ) arranged between the adjacent DOTs in the auxiliary cell deliver ${V}_{G}$ back to PMPs, which can effectively induce the electron accumulation on the silicon surface in the conduction cell. The enhanced electron accumulation in turn results in high electron mobility and low ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . In the OFF-state, the electric field and potential are reshaped by DOTs and PMPs, ensuring a high breakdown voltage (BV). In addition, the maximum lattice temperature ( ${T}_{\text {max}}$ ) and temperature rise ( $ {\Delta } {T} = {T}_{\text {max}} -{T}_{\text {in}}$ , ${T}_{\text {in}}$ : initial temperature) can be significantly decreased. Compared with the conventional SOI LDMOS, the proposed SOI LDMOS achieves 43.29% reduction in ${R}_{ \mathrm{\scriptscriptstyle ON}}$ at ${V}_{G} =15$ V without deteriorating BV and 50% decrease in $ {\Delta } {T} $ at ${I}_{\text {DS}} =0.2$ A (42 A/cm $^{{2}}$ ).

In this work, a high-voltage amorphous In-Ga-Zn-O (a-IGZO) thin-film-transistors (TFTs) with the stair gate-dielectric at the drain side were demonstrated. The electrical properties of the proposed TFTs were comprehensively investigated. The breakdown voltage ( ${V} _{\text {BD}}$ ) was significantly enhanced, and the ${V} _{\text {BD}}$ of over 60 V is achieved in the TFT with the stair length ( ${L} _{\text {stair}}$ ) of $3~\mu \text{m}$ . The TCAD simulation and emission microscope (EMMI) measurements are performed to reveal the working and breakdown mechanisms of the proposed stair gate-dielectric TFTs. The descending electron current density in the channel lowers the stair-gate TFTs’ ON-current. Meanwhile, the stair-gate-dielectric region endures a strong electric field and improves the ${V} _{\text {BD}}$ of the device. Finally, the exponential trade-off relationship between the ${V} _{\text {BD}}$ and the ON-state resistance ( ${R} _{\text{ON}}$ ) was established.

The 4H-SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) with the grounded p+ shielding region is one of the commercial devices with superior gate oxide reliability. However, the introduced JFET region seriously increases the influence of quasisaturation (QS) on device electrical performances, resulting in the poor output and transfer characteristics. In order to investigate the mechanism of QS effect, the output characteristic is physically analyzed by monitoring the variations of the electric field, the electron concentration, the electron velocity, and the depletion layer inside the cell structure. It is demonstrated that the channel electrons are injected into the JFET current path from the channel region by a forward bias to the channel and JFET junction at QS state. Moreover, based on the Lombardi CVT model, the influence of QS effect on devices with different channel electron mobilities is first studied. An improved SiC trench MOSFET with two-level doped current spreading layers is proposed to decrease the JFET resistance and suppress the QS effect. The QS current and the peak transconductance are improved by 42% and 23%, respectively. The specific ON-state resistance is decreased by 10% and the figure of merit is improved by 7%.

Four-switch buck-boost (FSBB) converter is widely used in battery applications due to the simple structure and the excellent performance of both voltage step-up and step-down. With the quadrangle control method, FSBB converter can realize zero voltage switching (ZVS) of all power switches, and thus can adapt to the high-frequency trends. However, the conventional quadrangle control method has two problems: 1) the efficiency degradation caused by the large root mean square (RMS) current of the inductor, and 2) the instability caused by the coupling relationship between multiple control variables. In this article, an improved quadrangle control method is proposed to solve the two problems, making FSBB converter a good candidate for high-frequency battery applications. First, the loss analysis is built to determine the relationship between loss and the control variables. Then, the conditions to achieve the minimum loss are obtained. Second, the decoupling compensation strategy is applied to free the coupling relationship to improve the stability. The proposed strategy can achieve three control goals: 1) ZVS of all power switches; 2) minimize the total loss; and 3) stable closed-loop system. Finally, a 1MHz 280W FSBB prototype is built to verify the proposed control method. The prototype achieves all control goals and 98.1% peak efficiency.

The gate voltage overshoot during the turn-on transient in the trench gate U-shaped (TGU) channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is investigated and novel structures are proposed for the first time with numerical simulation in this article. The TGU SOI-LIGBT features two U-shaped trench gates, G1 and G2, connected together. The U-shaped trench for G2 serves as a hole barrier trench. A large number of holes accumulate in the U-shaped region during the turn-on transient because of the U-shaped architecture and the hole-blocking effect of G2. The displacement current induced by the nonuniform distributed holes overcharges the gate and leads to high di / dt . In this article, the novel structures (Novel-1 and Novel-2) with G2 partially filled by the polysilicon are proposed for the improvement in gate voltage overshoot while keeping superior turn-on loss ( ${E}_{ \mathrm{ON}}$ ). The novel structures (Novel-1 and Novel-2) can suppress the hole accumulation and slow down the rising of the electric potential in the silicon region near the G2. The di / dt can be lowered and the displacement current that overcharges G2 can be effectively shielded. Compared with the conventional TGU structure, the di / dt of the Novel-2 are improved by 56.3% at the same ${E}_{ \mathrm{ON}}$ of 2.4 mJ/cm2.

New failure mechanism induced by current limits has been investigated for the superjunction MOSFET (SJ-MOSFET) under single-pulse unclamped inductive switching (UIS) test stress. It is found that the local charge imbalance ( ${Q}_{{n}} > {Q}_{{p}}$ ) at the chip corner produces a hotspot during the UIS test. The failure of the device induced by the hotspot depends on the magnitude of the avalanche current. For a low avalanche current, the avalanche current is redistributed from the local charge imbalance region to the charge balance region due to the lattice temperature increasing, resulting in the local heating toward the full-scale heating. However, for a high avalanche current, the negative differential resistance (NDR) effect plays a dominant role in the local charge imbalance region, decreasing the dynamic breakdown voltage (BV) sharply. Therefore, the hotspot is locked at the charge imbalance region; then, the device is destroyed in a short time. Finally, an SJ-MOSFET with more p-type charges at the chip corner is produced to improve the avalanche capability relating to the current limit, also verifying the mechanism analysis.