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As the new hash standard, Keccak-based secure hash function (SHA-3) will be used in various cryptographic applications. Its security will be of paramount importance to the systems built on top of it. This paper proposes efficient algebraic fault analysis (AFA) methods, and for the first time, applies them to all four modes of SHA-3 under relaxed fault models. Our AFA utilizes the clear algebraic properties of Keccak operations and is very suitable for the fault analysis of SHA-3. Both our analysis and experimental results show that the proposed AFA method is more efficient than the traditional differential fault analysis (DFA) under the single-byte fault model, requiring much fewer faults to recover a whole internal state of the hashing computation. Meanwhile, as AFA is able to exploit all the information available, it can be applied to SHA-3 modes with shorter digests and under more relaxed fault models, where often times the DFA method fails. Our results show that AFA can successfully break all the four SHA-3 modes under a 16-bit fault model, and break SHA3-512 under an even more relaxed fault model, 32-bit fault, all within several minutes. The successful AFA on SHA-3 demonstrates the vulnerability of Keccak algorithms to fault analysis, calling for protections against fault injection and fault analysis.

SHA-3 was an open competition initiated by NIST to design new generation of hash functions. This competition was a necessity to overcome the challenges imposed by multiple attacks on MDx family of hash functions including SHA-0 and SHA-1. For this competition, NIST announced a reference platform which did not cover Embedded and Mobile machines. This paper compares the performance of SHA-3 final round candidate algorithms on ARM Cortex-M4 processor (embedded processor) and presents the results. Cycles per Byte is used as performance metric. Cortex-M4 based Stellaris® LM4F232 Evaluation Board (EK-LM4F232) from Texas Instruments is used for performance evaluation.

Embedded multi-core systems are implemented as systems-on-chip that rely on packet store-and-forward networks-on-chip for communications. These systems do not use buses or global clock. Instead routers are used to move data between the cores, and each core uses its own local clock. This implies concurrent asynchronous computing. Implementing algorithms in such systems is very much facilitated using dataflow concepts. In this paper, we propose a methodology for implementing algorithms on dataflow platforms. The methodology can be applied to multi-threaded, multi-core platforms or a combination of these platforms as well. This methodology is based on a novel dataflow graph representation of the algorithm. We applied the proposed methodology to obtain a novel dataflow multi-core computing model for the secure hash algorithm-3. The resulting hardware was implemented in field-programmable gate array to verify the performance parameters. The proposed model of computation has advantages, such as flexible I/O timing in term of scheduling policy, execution of tasks as soon as possible, and self-timed event driven system. In other words, I/O timing and correctness of algorithm evaluation are dissociated in this paper. The main advantage of this proposal is ability to dynamically obfuscate algorithm evaluation to thwart side-channel attacks without having to redesign the system. This has important implications for cryptographic applications.

In this paper, based on the work pioneered by Aumasson and Meier, Dinur et al., and Guo et al., we construct some new delicate structures from the roundreduced versions of Keccakhash function family. The new constructed structures are called cross-linear structures, because linear polynomials appear across in different equations of these structures. And we apply cross-linear structures to do preimage attacks on some instances of the round-reduced Keccak. There are three main contributions in this paper. First, we construct a kind of cross-linear structures by setting the statuses carefully. With these cross-linear structures, guessing the value of one linear polynomial could lead to three linear equations (including the guessed one). Second, for some special cases, e.g. the 3-round Keccakchallenge instance Keccak[r=240, c=160, nr=3], a more special kind of cross-linear structures is constructed, and these structures can be used to obtain seven linear equations (including the guessed) if the values of two linear polynomials are guessed. Third, as applications of the cross-linear structures, we practically found a preimage for the 3-round KeccakChallenge instance Keccak[r=240, c=160, nr=3]. Besides, by constructing similar cross-linear structures, the complexity of the preimage attack on 3-round Keccak-256/SHA3-256/SHAKE256 can be lowered to 2150/2151/2153 operations, while the previous best known result on Keccak-256 is 2192., IACR Transactions on Symmetric Cryptology, Volume 2017, Issue 4

If X is sender of a message and Y is the receiver of the same, then X encrypts the same with Y’s public key and then sends the encrypted data to Y. It confirms about authenticity and authorization of receiver. If X sends message and Y receives, X encrypts the message with X’s private key and sends the encrypted data to Y. It confirms authenticity and authorization of the sender [1]. Such a schema could work properly. It involves the usage of a message digest or hash. Hash is a fingerprint or the summary of the message. It carries similar concept of cyclic redundancy check (CRC). Integrity of the data is verified with this process. This process actually confirms that the data should not be damaged between the path of sender and receiver [2]. Hashing confirms few things like (i) complexity of calculation of hash value of a message should be decreased; (ii) it follows a one-way encrypting procedure or technique; and (iii) different hash values should be generated by a particular hashing technique for any two different messages.

International Conference on Artificial Intelligence and Applied Mathematics in Engineering (ICAIAME) -- APR 20-22, 2019 -- Antalya, TURKEY, In view of the widespread use of information technologies, the security of data against third parties should be maintained. Blockchain technology is used for this data and especially for transactions in finance. However, although bitcoin is well known as the crypto currency, the use of the blockchain technology is gaining importance in different areas as well. Thus, consensus algorithms have been developed in order to increase the security and especially the integrity of the crypto currencies. These consensus algorithms indirectly influence the market value of crypto currencies. In this study, consensus algorithms of some crypto currencies have been investigated. In addition to the SHA256 algorithm, the advantages and disadvantages of using Shake and Keccak algorithms as a part of the consensus algorithms, have been analyzed. SHA256, Keccak and Shake algorithms are compared regarding to their performance. As a result, we recommend that the cryptographic hash function can be replaced with the Shake algorithm can be an extendable output function for new crypto currencies.

We present a high-assurance and high-speed implementation of the SHA-3 hash function. Our implementation is written in the Jasmin programming language, and is formally verified for functional correctness, provable security and timing attack resistance in the EasyCrypt proof assistant. Our implementation is the first to achieve simultaneously the four desirable properties (efficiency, correctness, provable security, and side-channel protection) for a non-trivial cryptographic primitive.Concretely, our mechanized proofs show that: 1) the SHA-3 hash function is indifferentiable from a random oracle, and thus is resistant against collision, first and second preimage attacks; 2) the SHA-3 hash function is correctly implemented by a vectorized x86 implementation. Furthermore, the implementation is provably protected against timing attacks in an idealized model of timing leaks. The proofs include new EasyCrypt libraries of independent interest for programmable random oracles and modular indifferentiability proofs., This work received support from the National Institute of Standards and Technologies under agreement number 60NANB15D248.This work was partially supported by Office of Naval Research under projects N00014-12-1-0914, N00014-15-1-2750 and N00014-19-1-2292.This work was partially funded by national funds via the Portuguese Foundation for Science and Technology (FCT) in the context of project PTDC/CCI-INF/31698/2017. Manuel Barbosa was supported by grant SFRH/BSAB/143018/2018 awarded by the FCT.This work was supported in part by the National Science Foundation under grant number 1801564.This work was supported in part by the FutureTPM project of the Horizon 2020 Framework Programme of the European Union, under GA number 779391.This work was supported by the ANR Scrypt project, grant number ANR-18-CE25-0014.This work was supported by the ANR TECAP project, grant number ANR-17-CE39-0004-01.

Two of the very well-known hash algorithms from SHA2 (SHA-2) family include SHA-256 and SHA-512. Nowadays, there exists another hash algorithms family -- SHA3(SHA-3), which includes SHA3-256 and SHA3-512 algorithms, also known as Keccak algorithms. This paper provides a comparison of the empirical performance calculations with these 4 algorithms with different input volumes of sequential data (where every next slice of information is dependent of previous one) to make it impossible for parallel computation. For the purpose of calculations, 4 totally different environments are used but with exact number of CPUs and approximately similar amount of memory (using only standard instances types) -- one personal computer from one side and 3 of the biggest public cloud providers from another -- Amazon AWS (t2.medium), Microsoft Azure (Standard D2s v3) and Google Cloud (n1-standard-2). The purpose of the research is to compare these environments in terms of additional compute calculations and additional storage space (volumes and prices) for the presented new security improvement of the Merkle-root calculation. The Merkle-root is an integral part of the blockchain and therefore, security improvement of this component is a security improvement of the whole blockchain structure.

The National Institute of Standards and Technology (NIST) chose in 2012 the winner of the third competition to decide a new hashing standard, establishing the new Secure Hash Algorithm-3 (SHA-3). Multiple FPGA implementations were published during the standardization process to compare performances, but also after the official announcement, improving and optimizing the state of the art further. In this work, we present new implementations to improve several different aspects from previous works. We introduce a new row-oriented architecture, never used before in the "race" for the most lightweight SHA-3 FPGA implementation. Featuring this new row-based processing, we present two architectures with different area-frequency trade-offs?. We use FPGA resources never considered before in the literature, and discuss the limitations they present. In addition to this, we present a pipelined implementation aiming for the best compromise between area and throughput. As a result, our lightweight implementation uses 44% fewer resources than the current state of the art. Moreover, our efficiency-tailored implementation is 70% more efficient than the previous best work on the Virtex-6 platform. In essence, in this work, we present the smallest and the most efficient SHA-3 FPGA tailored implementations to date.

The IoT makes communication possible between anything and adds the dimension “Any THING communication” to the Information and Communication Technologies (ICTs), which has already provided the “Any TIME” and the “Any PLACE” communication. With the impressive growth forecasts, the IoT is raising many challenges including information security and privacy issues, these need to be resolved to get maximum potential benefits from it. Observers see the IoT as a revolutionary fully interconnected ‘smart’ world of progress, but other thinking about the IoT is that it represents a darker world of surveillance, privacy and security violations, because in the IoT environment ‘Everything’ will be accessible through the Internet. This work presents a LabVIEW-FPGA based implementation of authenticated encryption, which can be used in an IoT environment using BITW technique.

In memory-computing (IMC) architectures provide a much needed solution to energy-efficiency barriers posed by Von-Neumann computing due to movement of data between the processor and the memory. Emerging non-volatile memories (NVM) such as Resistive RAM (ReRAM) implemented in a crossbar array are promising substrates to realize IMC due to excellent High Resistance State (HRS) to Low Resistance State (LRS) ratios and high-densities. Hardware security primitives such as SHA-3 require heavy data traffic between processing elements and memory. Therefore, they can be benefited substantially by in-memory acceleration. We propose SHINE, a high performance and area efficient hardware implementation of the Keccak function that forms the core of SHA-3 by exploiting ReRAM-based IMC. SHINE implements various functions in a Sum of Product (SOP) form in the crossbar array architecture. Simulation results show that it cuts down energy by ∼90.5% and increases throughput by 1.5X to 2.8X as compared to conventional CMOS based implementations such as [1] and [2].

Processing-In-Memory (PIM), which implements logic operations within memory cells, opens up a new direction on organizing data and computation. Leveraging resistive or magnetic characteristics of nonvolatile memory (NVM) devices, platforms such as PLiM and ReVAMP have been proposed. This paper presents a PIM implementation of SHA-3, a state-of-the-art secure hash algorithm using a Voltage-Gated Spin Hall-Effect (SHE) Driven magnetic tunnel junction (MTJ) based crossbar, which is able to achieve a complete set of Boolean operations. The work includes the design of the crossbar circuit, the instruction set, and both unpipelined and pipelined implementations of SHA-3. Experimental results show that the proposed SHE MTJ-based implementation is able to achieve 2.16X higher throughput than a state-of-the-art Resistive RAM based SHA-3 implementation. Further throughput improvement can be achieved with multiple message hash (MMH) pipelining.

Two low-power SHA-3 designs are provided on UltraScale FPGA using its embedded Digital Signal Processing (DSP) slice; one for the area constrained environments and the other for high-speed applications.All bitwise logical operations of SHA-3 are logically grouped in 48-bit wide parallel operations to get maximum benefit of Xilinx DSP48E2 slice structure.Logical Cascade Structure (LCS) strategy is used to confine maximum SHA-3 logic within same DSP slice column and also to get maximum benefit from its low-power dedicated interconnect.The DSP based compact SHA-3 design utilizes 79.10% less DSP slices and consumes only 1/7th of power while high-speed 1600-bit design provides 23.57 Gbps with consumption of only 1/5th of power. Display Omitted This work presents two low-power Secure Hash Algorithm-3 (SHA-3) designs on Field Programmable Gate Array (FPGA) using embedded Digital Signal Processing (DSP48E) slice, one for area constrained environments and the other for high-speed applications. The seven equations of SHA-3 are logically optimized to three and four stage pipelined organizations for our compact and high-speed designs, respectively. The maximum parallelism between all the bitwise operations of different stages of SHA-3 is explored with respect to the 48-bit structure of DSP slice. Further Logical Cascade Structure (LCS) design strategy is proposed in accordance with the DSP slice organization. These optimizations result in saving of resources and at the same time achieve low-power with high performance. Our compact design results in saving of 79.10% DSP slices and consumes only 1/7th of power while 1600-bit DSP design provides 23.57 Gbps throughput and consumes only 1/5th of power as compared to the conventional SHA-3 designs.

The need for securing data across the Internet has become a fundamental issue over the last decade. The Internet protocol security IPSec standard has been developed as one solution to the problem of end-to-end secure communications. IPSec implementation is computationally intensive and can significantly limit the performance of high-speed networks. To overcome this speed issue, hardware implementations of IPSec offer the best solution. This work presents a field programmable gate array-based reconfigurable IPSec authentication header AH core. AH is one of the two main IPSec protocols, namely, AH and encapsulating security payload, and it supports both transport and tunnel modes of operations. For the AH protocol, a newly selected cryptographic hash function called secure hash algorithm-3 SHA-3 is implemented and used in this work. SHA-3 is implemented using a unique two-phase implementation approach that combines all the steps of SHA-3. The resultant equations, after combining the SHA-3 steps, are implemented as a proposed high-speed architecture, which results in data throughput in the gigabits per second range. The AH core proposed here outperforms other published techniques and is capable of supporting IPv4 datagrams for both modes of operation transport and tunnel and also can be used to provide security services for Internet of things applications that require high data throughput speeds. Copyright © 2016 John Wiley & Sons, Ltd.

Currently, the PIN is still used to verify identity on web-based applications. PIN is widely used because it is easy authentication. However, a PIN has a potential security risk that is vulnerable to shoulder surfing attacks. The way to reduce shoulder surfing attacks is to create an interface that is difficult to attack with shoulder surfing attack techniques. One interface that can be applied is the incognito method. In this research, the application of the incognito method is implemented as a web login application. The application is built based on the web using the SHA3-256 algorithm to hash the PIN. The results of the stufy prove that the application built is resistant to shoulder surfing attack by attackers.

The Keccak hash function is the winner of the SHA-3 competition (2008–2012) and became the SHA-3 standard of NIST in 2015. In this paper, we focus on practical collision attacks against round-reduced SHA-3 and some Keccak variants. Following the framework developed by Dinur et al. at FSE 2012 where 4-round collisions were found by combining 3-round differential trails and 1-round connectors, we extend the connectors to up to three rounds and hence achieve collision attacks for up to 6 rounds. The extension is possible thanks to the large degree of freedom of the wide internal state. By linearizing S-boxes of the first round, the problem of finding solutions of 2-round connectors is converted to that of solving a system of linear equations. When linearization is applied to the first two rounds, 3-round connectors become possible. However, due to the quick reduction in the degree of freedom caused by linearization, the connector succeeds only when the 3-round differential trails satisfy some additional conditions. We develop dedicated strategies for searching differential trails and find that such special differential trails indeed exist. To summarize, we obtain the first real collisions on six instances, including three round-reduced instances of SHA-3, namely 5-round SHAKE128, SHA3-224 and SHA3-256, and three instances of Keccak contest, namely Keccak[1440, 160, 5, 160], Keccak[640, 160, 5, 160] and Keccak[1440, 160, 6, 160], improving the number of practically attacked rounds by two. It is remarked that the work here is still far from threatening the security of the full 24-round SHA-3 family. Ministry of Education (MOE) National Research Foundation (NRF) Accepted version This research is supported by the National Research Foundation, Prime Minis- ter’s Office, Singapore under its Strategic Capability Research Centres Funding Initiative, NTU Research Grant M4080456 and M4082123, and Ministry of Edu- cation Singapore Grant M4012049. Guohong Liao is partially supported by the National Natural Science Foundation of China (Grants No. 61572028). Guozhen Liu is partially supported by the State Scholarship Fund (No. 201706230141) organized by China Scholarship Council. Meicheng Liu is partially supported by the National Natural Science Foundation of China (Grants No. 61672516). Kexin Qiao and Ling Song are partially supported by the National Natural Science Foundation of China (Grants No. 61802399, 61802400, 61732021 and 61772519), the Youth Innovation Promotion Association CAS, and Chinese Ma- jor Program of National Cryptography Development Foundation (Grant No. MMJJ20180102).

This paper is about a proposal of the algorithm to derive encryption keys based on key-files using the hash algorithm SHA-3. For our upcoming design of block cipher with special key length, which is 111 bytes, we are facing the problem how to derive encryption keys, even there are for example scrypt or Argon2 key-derivation function, we would like to design algorithm specialized for generating hashes of the required length. Thus, we proposed whole new algorithm. We also wanted to forge encryption keys based on key-files and do not limit only for passwords as the source. So, this paper presents the design of the final algorithm and results from testing it. This work is also the first proposal and in the future is planned to test it more.

Recently the CAESAR competition has announced several finalists among the submitted authenticated encryption algorithms, after an open selection process during the last five years. Applications using these algorithms are rapidly increasing today. Devices implementing these applications are enormously susceptible to physical attacks, which are able to retrieve secret data through side-channel information such as power consumption or the electromagnetic radiations. In this work, we present a Side-Channel Analysis resistant hardware implementation of the whole family of authenticated encryption schemes Ketje . By changing just one parameter, any of the Ketje designs can be obtained, and tailored for different applications, either lightweight or high throughput. We introduce a new protected Keccak implementation, as well as unprotected and protected Ketje implementations, which allow both encryption and decryption modes in the same module. In order to secure these implementations we make use of the masking scheme known as Threshold Implementations and complement it with the technique of “Changing of the Guards”, achieving a first-order Side-Channel Analysis protected implementation with zero extra randomness needed. This way, no dedicated PRNG needs to be additionally implemented, avoiding issues such as the security of the PRNG itself or the quality of the randomness. We elaborate on the importance of the input dependencies and how the addition of linear blocks could thwart the security provided by a correctly protected module. This is of special importance when extending Keccak to implement Ketje . Furthermore, we provide an empirical evaluation of both Keccak and Ketje implementations, demonstrating how with our methodology we can construct a secure Ketje based on a previously secured Keccak .

Because of the recent break of the SHA-l hash function, it is expected that in the nearest future there will be an increasing interest in the new SHA-3 algorithm. SHA-3 implements a subset of the Keccak family and has been released as the NIST standard in 2015. SHA-3 based MAC is a keyed-hash message authentication function, which can be used to verify both the data integrity of the message and its source. Previous work demonstrated successful side channel attacks, in particular power attacks on hardware implementations of the SHA-3 based MAC. This work presents a new two step practical attack against SHA-3 based MAC implemented on an FPGA hardware. This new attack can successfully extract the 320-bit secret key with 200,000 traces at 90% success rate.

High performance and area efficient Secure Hash Algorithm (SHA-3) hardware realization is investigated and proposed in this work. In addition to the new and simplified round constant (RC) generator, the presented SHA-3 hash implementations employed architectural optimization approaches based on the concepts of unrolling, pipelining and subpipelining. This has therefore produced a total of five implementations of SHA-3 which are denoted as Cases I-V in both FPGA and ASIC. Considering the trade-offs between the performance and hardware cost, the best architecture in term of the throughput and area efficiency is identified in Case V. The architecture has the highest throughput of 16.51 Gbps and area efficiency of 11.47 Mbps/slices for the FPGA implementation. While in ASIC, our best implementation (Case V) achieves the highest throughput of 48 Gbps.

In the era of internet and computer networking the need for security have increased rapidly. Various crypto algorithms are used for secured data transmission and reception through the network, of which hash function possess a key role in various cryptographic protocols. Keccak algorithm is the winner of SHA-3 competition conducted by NIST. SHA-3 consists of different variant such as 224, 256, 384 and 512 bit. This paper discuss the design and implementation of SHA-3 256- bit core. The core is designed using Verilog HDL and prototyped using Xilinx® Virtex®-6FPGA.

is an asset in today's life. Internet plays major role for sharing the information between two parties. To protect the information from attacks there exist several algorithms. Cryptographic hash functions are the one that is used for the purpose of modern security. In mobile computing, portables devices are used to share information. Most of portable devices are based on ARM processors. In this work, a BLAKE algorithm from SHA-3 finalists is selected for analysis on ARM Cortex A8 Processor. BLAKE is a hash function selected by NIST in SHA-3 competition. Many factors need to be considered such as utilization of memories ROM or RAM, power consumption and cycles required for particular algorithm. In this paper, the objective is to compare the performance of all variants of BLAKE in terms of cycles required on ARM Cortex A8.

Hash functions are considered key components of nearly all cryptographic protocols, as well as of many security applications such as message authentication codes, data integrity, password storage, and random number generation. Many hash function algorithms have been proposed in order to ensure authentication and integrity of the data, including MD5, SHA-1, SHA-2, SHA-3 and RIPEMD. This paper involves an overview of these standard algorithms, and also provides a focus on their limitations against common attacks. These study shows that these standard hash function algorithms suffer collision attacks and time inefficiency. Other types of hash functions are also highlighted in comparison with the standard hash function algorithm in performing the resistance against common attacks. It shows that these algorithms are still weak to resist against collision attacks.

Kriptografija je u temeljima velikog dijela moderne računalne infrastrukture, stoga je vrlo bitno da se u nju možemo pouzdati. Sigurnost malih, ugradbenih uređaja čini jedan dio tog. Elektromagnetsko umetanje greške (EMFI) je moćna tehnika za izvođenje napada umetanjem pogreške, ali zahtijeva odabir dobrih parametara u prostoru daleko prevelikom da bi se mogao iscrpno pretražiti. U ovom radu se iznosi evolucijski algoritam za pretragu prostora parametara za umetanje greške, kao i logika iza njegovog razvoja. Ovaj algoritam se potom koristi za pronalazak grešaka koje se koriste za algebarsku analizu grešaka (AFA) na SHA-3 (Keccak) kriptografskom heš algoritmu; dana je usporedba rezultata sa slučajnom osnovicom. Cryptography underpins a large part of modern computer infrastructure, making its reliability very important. The security of embedded devices and their tamper-resistance is a small part of this. Electromagnetic fault injection (EMFI) is a powerful fault injection technique for conducting fault injection (FI) attacks, however it requires choosing parameters in a parameter space that's far too large to perform an exhaustive search, and presently there appears to be no good method for conducting the search for good parameters. In this thesis, an evolutionary algorithm for FI parameter search is presented, along with the rationale used in its development. This algorithm is used to find faults for an algebraic fault attack (AFA) on the SHA-3 (Keccak) cryptographic hash algorithm, and its results are compared with the random baseline.

Correlation Power Analysis, is recently demonstrated as a viable attack model for Keccak, which is the new hash function selected by NIST for SHA-3. Early studies show that CPA attacks can be launched on this algorithm with conventional CMOS implementations. To mitigate such power attacks, in this research we propose secure neural primitives using memristor neural logic blocks. Five different mitigation techniques are proposed, including baseline dualcore design, theta Plane Masking, neural logic block based theta Plane Masking, Analog neural logic block theta Plane Masking, and Analog dual-neural logic block theta Plane Masking. A framework for the CPA attack was designed and the mitigation techniques were assessed based on the number of power traces used, correlation coefficients, confidence ratios, and transistor count. Success rate of guessing a key during SHA-3 operations, while configured as a MAC, is used as a system benchmark. Secure neural primitives are shown to be robust to the CPA attacks.

A detailed review of a brief history, applications and contributions of the hash functions in today's cryptology are articulated here. The secured hash functions are applied in various fields to provide a secure data transfer and authentication of messages and other user linked information through a series of algorithms. From the establishment of the first hash function MD5, followed by SHA 1, this data encryption system has undergone several upgradations and advanced to SHA 2 and SHA 3, the details of which are discussed in this paper. The importance of the secure hash algorithm in network security and also the necessity to upgrade from SHA1 and SHA2 to the modern standards of SHA3 is also highlighted here.

In this paper, we propose two different hardware structure of SHA-3 hash algorithm for different width of circuit interface. They both support the four functions SHA3-224/256/384/512 of SHA-3 algorithm. The padding unit of our design is also implemented by hardware instead of software. Besides, a 3-round-in-1 structure is proposed to speed up the throughput of our circuit. We conduct an implementation based in SMIC 65 nm technology, SHA3-224, SHA3-256, SHA3-384 and SHA3-512 achieve the throughput of 65.5 Gbps, 61.8 Gbps, 47.2 Gbps and 32.7 Gbps respectively which are better than the reported designs.

In August 2015, SHA-3 Standard was published as the next generation of Secure Hashing Algorithm. Several optimized implementations of SHA-3 on a 24-core processor with software and hardware co-design are proposed in this paper. For software designs, a 4-core mapping scheme with shared-memory reduces the delay time by exploring the internal parallelism of the algorithm; the scheme of 5 cores with packet router improves flexibility; and 24-core mapping with circuit router fully explores the parallelism with higher energy efficiency. Hardware approaches: specific instructions and novel latch-based accelerators, are proposed to improve performance and energy efficiency. The three software mappings provide a speedup of 3.1, 3.6 and 19.6, respectively. Almost 2 times better performance and energy efficiency are obtained with three specific instructions. The implementation of 4 latch-based accelerators achieves a throughput of 81.9 Gbps at 850MHz with 3.7 pJ/bit energy consumption per bit.

The Keyed-Hash Message Authentication Codes (HMAC) is a widely used method to ensure the integrity and authentication of data. In this paper an FPGA-based efficient processor of the Keyed-Hash Message Authentication Codes (HMAC) using the Secure Hash Algorithm3-224 (SHA3-224) is presented. Any length of message and key can be processed by this processer. To achieve the high throughput which can reach up to 2.3Gbps, some optimizations such as pre-process, key reusing and two SHA-3 cores cooperation are employed. As a result, this proposed HMAC processor is applicable for a wide range of performance-oriented security systems.

Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware design. HLS tools provide us with advanced capabilities for design evaluation and a wide variety of optimization techniques. In this paper, the SHA-3 hashing algorithm and its implementation onto a Xilinx® Zynq-7000 SoPC is explored. The SHA-3 hashing algorithm is initially coded in C programming language and then implemented with Xilinx Vivado HLS. The HLS tool enabled us to quickly analyze our design to make suitable optimizations which led to increased throughput of the SHA-3 hashing algorithm, up to 2000 Mbps. After pipelining the synthesized hardware design, it was capable of hashing a block of 1088 bits in 70 clock cycles.

In this paper, three different approaches are considered for FPGA based implementations of the SHA-3 hash functions. While the performance of proposed unfolded and pipelined structures just match the state of the art, the dependencies of the structures which are folded slice-wise allow to further improve the efficiency of the existing state of the art. By solving the intra-round dependencies caused by the θ step-mapping with the pre-computation of values and by improving the memory mapping, it is possible to reduce the required area resources and obtain shorter datapath. This allows to achieve an efficiency improvement of at least 50% in regard to the state of art. This work also provides an overview of the achievable performance and cost for different folding/unrolling options.

In this paper, a new locking protocolis being proposed which will be applied on a distributed database system. Two Phase Locking protocol will be implemented along with Secure Hash Algorithm-3, 512 variant. The Two phase locking algorithm is used to provide resources to the user which reduces the chances of deadlock. A hash value is calculated for every data that is sent to the client by the database server and by the client to check the integrity of the data sent by the database server. The hash value will be computed using SHA-3 hashing algorithm. It describes the reliability of information before read-writes transactions after their successful commit.

This work is focused on FPGA based implementations of the SHA-3 hash functions. The existing literature classifies the existing implementations according to the adopted structural optimization techniques, namely: folding, pipelining and unrolling. Several structures have been proposed in the state-of-the-art, which vary mainly in the level of folding and the number of pipeline stages. While unfolded structures allow obtaining higher throughputs, folded structures require less area resources at a cost of lower throughputs. It should be noted that due to the dependencies within the round caused by the step-mappings, the complexity increases as the folding technique is adopted. As suggested by the literature, the best results are achieved when using a slice-wise approach, rather than a lane-wise folding. With this approach, the resulting structure is able to process 16 slices on each iteration. However, special care must be taken regarding data dependencies in the θ and ρ step-mappings, in order to provide the necessary input values for the computation of the slices on each iteration. The ρ step-mapping dependencies were solved by re-scheduling the round computation as R resc = θ ο ι ο χ ο π ο ρ. With this, it is possible to split the round computation into two parts, one computing θ and the other computing π,χ, and ι, with the ρ step-mapping embedded into the state memory. This approach, considering a tradeoff between performance and throughout, allows to mitigate the data dependency, thus allowing to improve the Throughput per Area efficiency regarding the existing state-of-the-art by up to 50%.

This paper presents an efficient algebraic fault analysis on all four modes of SHA-3 under relaxed fault models. This is the first work to apply algebraic techniques on fault analysis of SHA-3. Results show that algebraic fault analysis on SHA-3 is very efficient and effective due to the clear algebraic properties of Keccak operations. Comparing with previous work on differential fault analysis of SHA-3, algebraic fault analysis can identify the injected faults with much higher rates, and recover an entire internal state of the penultimate round with much fewer fault injections.

Emerging non-volatile memory (NVM) technologies with computation capabilities can be effectively leveraged for computing tasks on resource-constrained Internet of Things (IoT) nodes. Redox-based Resistive RAM (ReRAM) is a promising NVM technology due to its high density, low leakage power and ability to perform functionally complete set of Boolean operations. The secure transmission of IoT sensory data is of paramount importance to guard confidentiality and authenticity. However, encryption and authentication requires additional computing resources leading to significant performance overhead. An alternative approach, as explored in this current manuscript, is to use the in-memory computing capability of ReRAM. In particular, we study ReRAM based in-memory computing architecture for round function of cryptographic hash algorithm known as SHA-3 or Keccak. Our carefully done mapping reveals a bit/word-serial architecture for SHA-3. In that respect, the estimated throughput for ReRAM-based implementation is comparable to a highly optimized, bit-serial, lightweight CMOS realization.

The secure hash algorithm (SHA)-3 has been selected in 2012 and will be used to provide security to any application which requires hashing, pseudo-random number generation, and integrity checking. This algorithm has been selected based on various benchmarks such as security, performance, and complexity. In this paper, in order to provide reliable architectures for this algorithm, an efficient concurrent error detection scheme for the selected SHA-3 algorithm, i.e., Keccak, is proposed. To the best of our knowledge, effective countermeasures for potential reliability issues in the hardware implementations of this algorithm have not been presented to date. In proposing the error detection approach, our aim is to have acceptable complexity and performance overheads while maintaining high error coverage. In this regard, we present a low-complexity recomputing with rotated operands-based scheme which is a step-forward toward reducing the hardware overhead of the proposed error detection approach. Moreover, we perform injection-based fault simulations and show that the error coverage of close to 100% is derived. Furthermore, we have designed the proposed scheme and through ASIC analysis, it is shown that acceptable complexity and performance overheads are reached. By utilizing the proposed high-performance concurrent error detection scheme, more reliable and robust hardware implementations for the newly-standardized SHA-3 are realized.