1,649 results on '"Martin, D. F."'
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202. Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.
203. Current Calculation on VLSI Signal Interconnects.
204. Adaptive Mesh Refinement for MHD Fusion Applications
205. Superfast Full-Scale CPU-Accelerated Global Routing
206. ATLAS
207. AdaOPC
208. WaferHSL
209. Simultaneous escape routing and layer assignment for dense PCBs.
210. Floorplan design for multi-million gate FPGAs.
211. A provably good algorithm for high performance bus routing.
212. I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
213. A Two-Layer Bus Routing Algorithm for High-Speed Boards.
214. Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers.
215. Rectilinear Steiner Tree Construction Using Answer Set Programming.
216. On handling arbitrary rectilinear shape constraint.
217. Tradeoff routing resource, runtime and quality in buffered routing.
218. Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus.
219. Optical proximity correction (OPC): friendly maze routing.
220. The nature of optimization problem challenges in physical synthesis.
221. Small Bowel Obstruction
222. Other Forms of Colitis and Enterocolitis
223. Infective Diarrhoea
224. Inflammatory Bowel Disease
225. Intestinal and Colorectal Injury
226. Congenital Abnormalities
227. Malabsorption
228. The Small Intestine: Normal Structure and Function
229. Motility Disorders
230. Perianal Abscess and Fistula
231. Disorders of the Pelvic Floor
232. Irritable Bowel Syndrome
233. Diverticular Disease
234. Large Bowel Carcinoma
235. Benign Epithelial Tumours and Polyps
236. Tumours of the Small Intestine
237. Explicit gate delay model for timing evaluation.
238. Length-Matching Routing for High-Speed Printed Circuit Boards.
239. Bus-Driven Floorplanning.
240. Stable Multiway Circuit Partitioning for ECO.
241. A Min-Cost Flow Based Detailed Router for FPGAs.
242. OpenTimer v2: A New Parallel Incremental Timing Analysis Engine
243. OpenTimer v2: A Parallel Incremental Timing Analysis Engine
244. A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition.
245. A routing algorithm for graphene nanoribbon circuit.
246. Integrated Floorplanning and Interconnect Planning
247. Advances in PCB Routing.
248. NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing.
249. Correctly Model the Diagonal Capacity in Escape Routing.
250. A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach.
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